diff options
| author | vboxsync <vboxsync@cfe28804-0f27-0410-a406-dd0f0b0b656f> | 2022-09-14 11:57:13 +0000 |
|---|---|---|
| committer | vboxsync <vboxsync@cfe28804-0f27-0410-a406-dd0f0b0b656f> | 2022-09-14 11:57:13 +0000 |
| commit | 8fb0d89266918e9efdd48aa4267ae4177ec757b9 (patch) | |
| tree | 517a74b5930f425c85fa7854b4952f61894df1c1 /src/VBox | |
| parent | 3d02b442eee2b93b6b20c830ff11f82498c09082 (diff) | |
| download | VirtualBox-svn-8fb0d89266918e9efdd48aa4267ae4177ec757b9.tar.gz | |
VMM/PGM: Nested VMX: bugref:10092 Adjusted guest EPT masks and comments.
git-svn-id: https://www.virtualbox.org/svn/vbox/trunk@96736 cfe28804-0f27-0410-a406-dd0f0b0b656f
Diffstat (limited to 'src/VBox')
| -rw-r--r-- | src/VBox/VMM/VMMR3/PGM.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/VBox/VMM/VMMR3/PGM.cpp b/src/VBox/VMM/VMMR3/PGM.cpp index d8589788bac..dc9f4c02818 100644 --- a/src/VBox/VMM/VMMR3/PGM.cpp +++ b/src/VBox/VMM/VMMR3/PGM.cpp @@ -1719,18 +1719,19 @@ VMMR3DECL(int) PGMR3InitFinalize(PVM pVM) pVCpu->pgm.s.fGstEptMbzPdpteMask = fMbzPageFrameMask | EPT_PDPTE_MBZ_MASK; pVCpu->pgm.s.fGstEptMbzBigPdpteMask = fMbzPageFrameMask | fGstEptMbzBigPdpteMask; pVCpu->pgm.s.fGstEptMbzPml4eMask = fMbzPageFrameMask | EPT_PML4E_MBZ_MASK; - pVCpu->pgm.s.fGstEptPresentMask = EPT_PRESENT_MASK; - /* If any of the features (in the assert below) are enabled, we would have to shadow the relevant bits. */ + /* If any of the features in the assert below are enabled, additional bits would need to be shadowed. */ Assert( !pVM->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt && !pVM->cpum.ro.GuestFeatures.fVmxSppEpt && !pVM->cpum.ro.GuestFeatures.fVmxEptXcptVe && !(fEptVpidCap & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY)); /* We need to shadow reserved bits as guest EPT tables can set them to trigger EPT misconfigs. */ - pVCpu->pgm.s.fGstEptShadowedPteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK; - pVCpu->pgm.s.fGstEptShadowedPdeMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_LEAF; - pVCpu->pgm.s.fGstEptShadowedPdpteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_LEAF; + pVCpu->pgm.s.fGstEptShadowedPteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT; + pVCpu->pgm.s.fGstEptShadowedPdeMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT | EPT_E_LEAF; + pVCpu->pgm.s.fGstEptShadowedPdpteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT | EPT_E_LEAF; pVCpu->pgm.s.fGstEptShadowedPml4eMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_PML4E_MBZ_MASK; + /* If mode-based execute control for EPT is enabled, we would need to include bit 10 in the present mask. */ + pVCpu->pgm.s.fGstEptPresentMask = EPT_PRESENT_MASK; #endif } |