diff options
| author | Robert Moore <Robert.Moore@intel.com> | 2021-07-14 12:48:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-14 12:48:18 -0700 |
| commit | c4ddc96f990b116aa638c262696c1b1e8bfdeb6f (patch) | |
| tree | 395ae1ca9b4e8e34a707c18f45fd0928eacdb8ab | |
| parent | 8d49c0b2b78b8a8c5dae4d5ff28432729f4d59f2 (diff) | |
| parent | d95c7d206b5836c7770e8e9cd613859887fded8f (diff) | |
| download | acpica-c4ddc96f990b116aa638c262696c1b1e8bfdeb6f.tar.gz | |
Merge pull request #705 from Semihalf/dbg2_subtypes_update
Headers: Add new DBG2 Serial Port Subtypes
| -rw-r--r-- | source/include/actbl1.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/source/include/actbl1.h b/source/include/actbl1.h index 157a89b72..09e68293a 100644 --- a/source/include/actbl1.h +++ b/source/include/actbl1.h @@ -702,7 +702,7 @@ typedef struct acpi_csrt_descriptor * DBG2 - Debug Port Table 2 * Version 0 (Both main table and subtables) * - * Conforms to "Microsoft Debug Port Table 2 (DBG2)", December 10, 2015 + * Conforms to "Microsoft Debug Port Table 2 (DBG2)", September 21, 2020 * ******************************************************************************/ @@ -759,11 +759,24 @@ typedef struct acpi_dbg2_device #define ACPI_DBG2_16550_COMPATIBLE 0x0000 #define ACPI_DBG2_16550_SUBSET 0x0001 +#define ACPI_DBG2_MAX311XE_SPI 0x0002 #define ACPI_DBG2_ARM_PL011 0x0003 +#define ACPI_DBG2_MSM8X60 0x0004 +#define ACPI_DBG2_16550_NVIDIA 0x0005 +#define ACPI_DBG2_TI_OMAP 0x0006 +#define ACPI_DBG2_APM88XXXX 0x0008 +#define ACPI_DBG2_MSM8974 0x0009 +#define ACPI_DBG2_SAM5250 0x000A +#define ACPI_DBG2_INTEL_USIF 0x000B +#define ACPI_DBG2_IMX6 0x000C #define ACPI_DBG2_ARM_SBSA_32BIT 0x000D #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E #define ACPI_DBG2_ARM_DCC 0x000F #define ACPI_DBG2_BCM2835 0x0010 +#define ACPI_DBG2_SDM845_1_8432MHZ 0x0011 +#define ACPI_DBG2_16550_WITH_GAS 0x0012 +#define ACPI_DBG2_SDM845_7_372MHZ 0x0013 +#define ACPI_DBG2_INTEL_LPSS 0x0014 #define ACPI_DBG2_1394_STANDARD 0x0000 |