Merge branch 'for-next/omap-devicetree-prepare' into next

31 files changed, 1216 insertions, 134 deletions

diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
index ad46386d59..cdb88caa12 100644
--- a/arch/arm/boards/beagle/lowlevel.c
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -168,7 +168,7 @@ static void sdrc_init(void)
  */
 static int beagle_board_init(void)
 {
-	int in_sdram = running_in_sdram();
+	int in_sdram = omap3_running_in_sdram();
 
 	if (!in_sdram)
 		omap3_core_init();
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index e993c8928a..992e3e4046 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -121,23 +121,23 @@ static int beaglebone_board_init(void)
 	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
 	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
 
-	if (running_in_sdram())
+	if (am33xx_running_in_sdram())
 		return 0;
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	if (is_beaglebone_black()) {
-		pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
+		am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
 		am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs,
 				&ddr3_data);
 	} else {
-		pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
+		am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
 		am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs,
 				&ddr2_data);
 	}
 
 	am33xx_uart0_soft_reset();
 	am33xx_enable_uart0_pin_mux();
-	omap_uart_lowlevel_init();
+	omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
 	putc_ll('>');
 
 	return 0;
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
index fcb9571506..816f400c83 100644
--- a/arch/arm/boards/omap343xdsp/lowlevel.c
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -536,7 +536,7 @@ static void mux_config(void)
  */
 static int sdp343x_board_init(void)
 {
-	int in_sdram = running_in_sdram();
+	int in_sdram = omap3_running_in_sdram();
 
 	if (!in_sdram)
 		omap3_core_init();
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
index 98f1476bb5..56075c1e6f 100644
--- a/arch/arm/boards/omap3evm/lowlevel.c
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -148,7 +148,7 @@ static void mux_config(void)
  */
 static int omap3_evm_board_init(void)
 {
-	int in_sdram = running_in_sdram();
+	int in_sdram = omap3_running_in_sdram();
 
 	omap3_core_init();
 
diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c
index 48578cd46c..ded108e333 100644
--- a/arch/arm/boards/pcm051/lowlevel.c
+++ b/arch/arm/boards/pcm051/lowlevel.c
@@ -65,10 +65,10 @@ static int pcm051_board_init(void)
 	writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
 	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
 
-	if (running_in_sdram())
+	if (am33xx_running_in_sdram())
 		return 0;
 
-	pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
+	am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
 
 	am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
 			&MT41J256M8HX15E_2x256M8_regs,
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
index 353b58fad6..7a67493fd6 100644
--- a/arch/arm/boards/phycard-a-l1/lowlevel.c
+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c
@@ -239,7 +239,7 @@ static void pcaal1_mux_config(void)
  */
 static int pcaal1_board_init(void)
 {
-	int in_sdram = running_in_sdram();
+	int in_sdram = omap3_running_in_sdram();
 
 	if (!in_sdram)
 		omap3_core_init();
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
new file mode 100644
index 0000000000..08d6d87728
--- /dev/null
+++ b/arch/arm/dts/am33xx.dtsi
@@ -0,0 +1,809 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "ti,am33xx";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		mmc0 = &mmc1;
+		mmc1 = &mmc2;
+		mmc2 = &mmc3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		d_can0 = &dcan0;
+		d_can1 = &dcan1;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		phy0 = &usb0_phy;
+		phy1 = &usb1_phy;
+		ethernet0 = &cpsw_emac0;
+		ethernet1 = &cpsw_emac1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0>;
+
+			/*
+			 * To consider voltage drop between PMIC and SoC,
+			 * tolerance value is reduced to 2% from 4% and
+			 * voltage value is increased as a precaution.
+			 */
+			operating-points = <
+				/* kHz    uV */
+				720000  1285000
+				600000  1225000
+				500000  1125000
+				275000  1125000
+			>;
+			voltage-tolerance = <2>; /* 2 percentage */
+			clock-latency = <300000>; /* From omap-cpufreq driver */
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a8-pmu";
+		interrupts = <3>;
+	};
+
+	/*
+	 * The soc node represents the soc top level view. It is uses for IPs
+	 * that are not memory mapped in the MPU view or for the MPU itself.
+	 */
+	soc {
+		compatible = "ti,omap-infra";
+		mpu {
+			compatible = "ti,omap3-mpu";
+			ti,hwmods = "mpu";
+		};
+	};
+
+	am33xx_pinmux: pinmux@44e10800 {
+		compatible = "pinctrl-single";
+		reg = <0x44e10800 0x0238>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7f>;
+	};
+
+	/*
+	 * XXX: Use a flat representation of the AM33XX interconnect.
+	 * The real AM33XX interconnect network is quite complex.Since
+	 * that will not bring real advantage to represent that in DT
+	 * for the moment, just use a fake OCP bus entry to represent
+	 * the whole bus hierarchy.
+	 */
+	ocp {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		ti,hwmods = "l3_main";
+
+		intc: interrupt-controller@48200000 {
+			compatible = "ti,omap2-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,intc-size = <128>;
+			reg = <0x48200000 0x1000>;
+		};
+
+		edma: edma@49000000 {
+			compatible = "ti,edma3";
+			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+			reg =	<0x49000000 0x10000>,
+				<0x44e10f90 0x10>;
+			interrupts = <12 13 14>;
+			#dma-cells = <1>;
+			dma-channels = <64>;
+			ti,edma-regions = <4>;
+			ti,edma-slots = <256>;
+		};
+
+		gpio0: gpio@44e07000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x44e07000 0x1000>;
+			interrupts = <96>;
+		};
+
+		gpio1: gpio@4804c000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio2";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x4804c000 0x1000>;
+			interrupts = <98>;
+		};
+
+		gpio2: gpio@481ac000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio3";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x481ac000 0x1000>;
+			interrupts = <32>;
+		};
+
+		gpio3: gpio@481ae000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio4";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x481ae000 0x1000>;
+			interrupts = <62>;
+		};
+
+		uart0: serial@44e09000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart1";
+			clock-frequency = <48000000>;
+			reg = <0x44e09000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <72>;
+			status = "disabled";
+		};
+
+		uart1: serial@48022000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart2";
+			clock-frequency = <48000000>;
+			reg = <0x48022000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <73>;
+			status = "disabled";
+		};
+
+		uart2: serial@48024000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart3";
+			clock-frequency = <48000000>;
+			reg = <0x48024000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <74>;
+			status = "disabled";
+		};
+
+		uart3: serial@481a6000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart4";
+			clock-frequency = <48000000>;
+			reg = <0x481a6000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <44>;
+			status = "disabled";
+		};
+
+		uart4: serial@481a8000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart5";
+			clock-frequency = <48000000>;
+			reg = <0x481a8000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <45>;
+			status = "disabled";
+		};
+
+		uart5: serial@481aa000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart6";
+			clock-frequency = <48000000>;
+			reg = <0x481aa000 0x2000>;
+			reg-shift = <2>;
+			interrupts = <46>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@44e0b000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c1";
+			reg = <0x44e0b000 0x1000>;
+			interrupts = <70>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@4802a000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c2";
+			reg = <0x4802a000 0x1000>;
+			interrupts = <71>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@4819c000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c3";
+			reg = <0x4819c000 0x1000>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		mmc1: mmc@48060000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc1";
+			ti,dual-volt;
+			ti,needs-special-reset;
+			ti,needs-special-hs-handling;
+			dmas = <&edma 24
+				&edma 25>;
+			dma-names = "tx", "rx";
+			interrupts = <64>;
+			interrupt-parent = <&intc>;
+			reg = <0x48060000 0x1000>;
+			status = "disabled";
+		};
+
+		mmc2: mmc@481d8000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc2";
+			ti,needs-special-reset;
+			dmas = <&edma 2
+				&edma 3>;
+			dma-names = "tx", "rx";
+			interrupts = <28>;
+			interrupt-parent = <&intc>;
+			reg = <0x481d8000 0x1000>;
+			status = "disabled";
+		};
+
+		mmc3: mmc@47810000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc3";
+			ti,needs-special-reset;
+			interrupts = <29>;
+			interrupt-parent = <&intc>;
+			reg = <0x47810000 0x1000>;
+			status = "disabled";
+		};
+
+		hwspinlock: spinlock@480ca000 {
+			compatible = "ti,omap4-hwspinlock";
+			reg = <0x480ca000 0x1000>;
+			ti,hwmods = "spinlock";
+		};
+
+		wdt2: wdt@44e35000 {
+			compatible = "ti,omap3-wdt";
+			ti,hwmods = "wd_timer2";
+			reg = <0x44e35000 0x1000>;
+			interrupts = <91>;
+		};
+
+		dcan0: d_can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			reg = <0x481cc000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <52>;
+			status = "disabled";
+		};
+
+		dcan1: d_can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			reg = <0x481d0000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <55>;
+			status = "disabled";
+		};
+
+		timer1: timer@44e31000 {
+			compatible = "ti,am335x-timer-1ms";
+			reg = <0x44e31000 0x400>;
+			interrupts = <67>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
+
+		timer2: timer@48040000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48040000 0x400>;
+			interrupts = <68>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@48042000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48042000 0x400>;
+			interrupts = <69>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@48044000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48044000 0x400>;
+			interrupts = <92>;
+			ti,hwmods = "timer4";
+			ti,timer-pwm;
+		};
+
+		timer5: timer@48046000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48046000 0x400>;
+			interrupts = <93>;
+			ti,hwmods = "timer5";
+			ti,timer-pwm;
+		};
+
+		timer6: timer@48048000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48048000 0x400>;
+			interrupts = <94>;
+			ti,hwmods = "timer6";
+			ti,timer-pwm;
+		};
+
+		timer7: timer@4804a000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x4804a000 0x400>;
+			interrupts = <95>;
+			ti,hwmods = "timer7";
+			ti,timer-pwm;
+		};
+
+		rtc@44e3e000 {
+			compatible = "ti,da830-rtc";
+			reg = <0x44e3e000 0x1000>;
+			interrupts = <75
+				      76>;
+			ti,hwmods = "rtc";
+		};
+
+		spi0: spi@48030000 {
+			compatible = "ti,omap4-mcspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x48030000 0x400>;
+			interrupts = <65>;
+			ti,spi-num-cs = <2>;
+			ti,hwmods = "spi0";
+			dmas = <&edma 16
+				&edma 17
+				&edma 18
+				&edma 19>;
+			dma-names = "tx0", "rx0", "tx1", "rx1";
+			status = "disabled";
+		};
+
+		spi1: spi@481a0000 {
+			compatible = "ti,omap4-mcspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x481a0000 0x400>;
+			interrupts = <125>;
+			ti,spi-num-cs = <2>;
+			ti,hwmods = "spi1";
+			dmas = <&edma 42
+				&edma 43
+				&edma 44
+				&edma 45>;
+			dma-names = "tx0", "rx0", "tx1", "rx1";
+			status = "disabled";
+		};
+
+		usb: usb@47400000 {
+			compatible = "ti,am33xx-usb";
+			reg = <0x47400000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ti,hwmods = "usb_otg_hs";
+			status = "disabled";
+
+			usb_ctrl_mod: control@44e10000 {
+				compatible = "ti,am335x-usb-ctrl-module";
+				reg = <0x44e10620 0x10
+					0x44e10648 0x4>;
+				reg-names = "phy_ctrl", "wakeup";
+				status = "disabled";
+			};
+
+			usb0_phy: usb-phy@47401300 {
+				compatible = "ti,am335x-usb-phy";
+				reg = <0x47401300 0x100>;
+				reg-names = "phy";
+				status = "disabled";
+				ti,ctrl_mod = <&usb_ctrl_mod>;
+			};
+
+			usb0: usb@47401000 {
+				compatible = "ti,musb-am33xx";
+				status = "disabled";
+				reg = <0x47401400 0x400
+					0x47401000 0x200>;
+				reg-names = "mc", "control";
+
+				interrupts = <18>;
+				interrupt-names = "mc";
+				dr_mode = "otg";
+				mentor,multipoint = <1>;
+				mentor,num-eps = <16>;
+				mentor,ram-bits = <12>;
+				mentor,power = <500>;
+				phys = <&usb0_phy>;
+
+				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+					&cppi41dma  2 0 &cppi41dma  3 0
+					&cppi41dma  4 0 &cppi41dma  5 0
+					&cppi41dma  6 0 &cppi41dma  7 0
+					&cppi41dma  8 0 &cppi41dma  9 0
+					&cppi41dma 10 0 &cppi41dma 11 0
+					&cppi41dma 12 0 &cppi41dma 13 0
+					&cppi41dma 14 0 &cppi41dma  0 1
+					&cppi41dma  1 1 &cppi41dma  2 1
+					&cppi41dma  3 1 &cppi41dma  4 1
+					&cppi41dma  5 1 &cppi41dma  6 1
+					&cppi41dma  7 1 &cppi41dma  8 1
+					&cppi41dma  9 1 &cppi41dma 10 1
+					&cppi41dma 11 1 &cppi41dma 12 1
+					&cppi41dma 13 1 &cppi41dma 14 1>;
+				dma-names =
+					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+					"rx14", "rx15",
+					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+					"tx14", "tx15";
+			};
+
+			usb1_phy: usb-phy@47401b00 {
+				compatible = "ti,am335x-usb-phy";
+				reg = <0x47401b00 0x100>;
+				reg-names = "phy";
+				status = "disabled";
+				ti,ctrl_mod = <&usb_ctrl_mod>;
+			};
+
+			usb1: usb@47401800 {
+				compatible = "ti,musb-am33xx";
+				status = "disabled";
+				reg = <0x47401c00 0x400
+					0x47401800 0x200>;
+				reg-names = "mc", "control";
+				interrupts = <19>;
+				interrupt-names = "mc";
+				dr_mode = "otg";
+				mentor,multipoint = <1>;
+				mentor,num-eps = <16>;
+				mentor,ram-bits = <12>;
+				mentor,power = <500>;
+				phys = <&usb1_phy>;
+
+				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+					&cppi41dma 17 0 &cppi41dma 18 0
+					&cppi41dma 19 0 &cppi41dma 20 0
+					&cppi41dma 21 0 &cppi41dma 22 0
+					&cppi41dma 23 0 &cppi41dma 24 0
+					&cppi41dma 25 0 &cppi41dma 26 0
+					&cppi41dma 27 0 &cppi41dma 28 0
+					&cppi41dma 29 0 &cppi41dma 15 1
+					&cppi41dma 16 1 &cppi41dma 17 1
+					&cppi41dma 18 1 &cppi41dma 19 1
+					&cppi41dma 20 1 &cppi41dma 21 1
+					&cppi41dma 22 1 &cppi41dma 23 1
+					&cppi41dma 24 1 &cppi41dma 25 1
+					&cppi41dma 26 1 &cppi41dma 27 1
+					&cppi41dma 28 1 &cppi41dma 29 1>;
+				dma-names =
+					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+					"rx14", "rx15",
+					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+					"tx14", "tx15";
+			};
+
+			cppi41dma: dma-controller@07402000 {
+				compatible = "ti,am3359-cppi41";
+				reg =  <0x47400000 0x1000
+					0x47402000 0x1000
+					0x47403000 0x1000
+					0x47404000 0x4000>;
+				reg-names = "glue", "controller", "scheduler", "queuemgr";
+				interrupts = <17>;
+				interrupt-names = "glue";
+				#dma-cells = <2>;
+				#dma-channels = <30>;
+				#dma-requests = <256>;
+				status = "disabled";
+			};
+		};
+
+		epwmss0: epwmss@48300000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48300000 0x10>;
+			ti,hwmods = "epwmss0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+				  0x48300180 0x48300180 0x80   /* EQEP */
+				  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+			ecap0: ecap@48300100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48300100 0x80>;
+				ti,hwmods = "ecap0";
+				status = "disabled";
+			};
+
+			ehrpwm0: ehrpwm@48300200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48300200 0x80>;
+				ti,hwmods = "ehrpwm0";
+				status = "disabled";
+			};
+		};
+
+		epwmss1: epwmss@48302000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48302000 0x10>;
+			ti,hwmods = "epwmss1";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+				  0x48302180 0x48302180 0x80   /* EQEP */
+				  0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+			ecap1: ecap@48302100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48302100 0x80>;
+				ti,hwmods = "ecap1";
+				status = "disabled";
+			};
+
+			ehrpwm1: ehrpwm@48302200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48302200 0x80>;
+				ti,hwmods = "ehrpwm1";
+				status = "disabled";
+			};
+		};
+
+		epwmss2: epwmss@48304000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48304000 0x10>;
+			ti,hwmods = "epwmss2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+				  0x48304180 0x48304180 0x80   /* EQEP */
+				  0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+			ecap2: ecap@48304100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48304100 0x80>;
+				ti,hwmods = "ecap2";
+				status = "disabled";
+			};
+
+			ehrpwm2: ehrpwm@48304200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48304200 0x80>;
+				ti,hwmods = "ehrpwm2";
+				status = "disabled";
+			};
+		};
+
+		mac: ethernet@4a100000 {
+			compatible = "ti,cpsw";
+			ti,hwmods = "cpgmac0";
+			cpdma_channels = <8>;
+			ale_entries = <1024>;
+			bd_ram_size = <0x2000>;
+			no_bd_ram = <0>;
+			rx_descs = <64>;
+			mac_control = <0x20>;
+			slaves = <2>;
+			active_slave = <0>;
+			cpts_clock_mult = <0x80000000>;
+			cpts_clock_shift = <29>;
+			reg = <0x4a100000 0x800
+			       0x4a101200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			/*
+			 * c0_rx_thresh_pend
+			 * c0_rx_pend
+			 * c0_tx_pend
+			 * c0_misc_pend
+			 */
+			interrupts = <40 41 42 43>;
+			ranges;
+
+			davinci_mdio: mdio@4a101000 {
+				compatible = "ti,davinci_mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ti,hwmods = "davinci_mdio";
+				bus_freq = <1000000>;
+				reg = <0x4a101000 0x100>;
+			};
+
+			cpsw_emac0: slave@4a100200 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			cpsw_emac1: slave@4a100300 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			phy_sel: cpsw-phy-sel@44e10650 {
+				compatible = "ti,am3352-cpsw-phy-sel";
+				reg= <0x44e10650 0x4>;
+				reg-names = "gmii-sel";
+			};
+		};
+
+		ocmcram: ocmcram@40300000 {
+			compatible = "ti,am3352-ocmcram";
+			reg = <0x40300000 0x10000>;
+			ti,hwmods = "ocmcram";
+		};
+
+		wkup_m3: wkup_m3@44d00000 {
+			compatible = "ti,am3353-wkup-m3";
+			reg = <0x44d00000 0x4000	/* M3 UMEM */
+			       0x44d80000 0x2000>;	/* M3 DMEM */
+			ti,hwmods = "wkup_m3";
+			ti,no-reset-on-init;
+		};
+
+		elm: elm@48080000 {
+			compatible = "ti,am3352-elm";
+			reg = <0x48080000 0x2000>;
+			interrupts = <4>;
+			ti,hwmods = "elm";
+			status = "disabled";
+		};
+
+		lcdc: lcdc@4830e000 {
+			compatible = "ti,am33xx-tilcdc";
+			reg = <0x4830e000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <36>;
+			ti,hwmods = "lcdc";
+			status = "disabled";
+		};
+
+		tscadc: tscadc@44e0d000 {
+			compatible = "ti,am3359-tscadc";
+			reg = <0x44e0d000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <16>;
+			ti,hwmods = "adc_tsc";
+			status = "disabled";
+
+			tsc {
+				compatible = "ti,am3359-tsc";
+			};
+			am335x_adc: adc {
+				#io-channel-cells = <1>;
+				compatible = "ti,am3359-adc";
+			};
+		};
+
+		gpmc: gpmc@50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			ti,no-idle-on-init;
+			reg = <0x50000000 0x2000>;
+			interrupts = <100>;
+			gpmc,num-cs = <7>;
+			gpmc,num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
+		sham: sham@53100000 {
+			compatible = "ti,omap4-sham";
+			ti,hwmods = "sham";
+			reg = <0x53100000 0x200>;
+			interrupts = <109>;
+			dmas = <&edma 36>;
+			dma-names = "rx";
+		};
+
+		aes: aes@53500000 {
+			compatible = "ti,omap4-aes";
+			ti,hwmods = "aes";
+			reg = <0x53500000 0xa0>;
+			interrupts = <103>;
+			dmas = <&edma 6>,
+			       <&edma 5>;
+			dma-names = "tx", "rx";
+		};
+
+		mcasp0: mcasp@48038000 {
+			compatible = "ti,am33xx-mcasp-audio";
+			ti,hwmods = "mcasp0";
+			reg = <0x48038000 0x2000>,
+			      <0x46000000 0x400000>;
+			reg-names = "mpu", "dat";
+			interrupts = <80>, <81>;
+			interrupts-names = "tx", "rx";
+			status = "disabled";
+			dmas = <&edma 8>,
+				<&edma 9>;
+			dma-names = "tx", "rx";
+		};
+
+		mcasp1: mcasp@4803C000 {
+			compatible = "ti,am33xx-mcasp-audio";
+			ti,hwmods = "mcasp1";
+			reg = <0x4803C000 0x2000>,
+			      <0x46400000 0x400000>;
+			reg-names = "mpu", "dat";
+			interrupts = <82>, <83>;
+			interrupts-names = "tx", "rx";
+			status = "disabled";
+			dmas = <&edma 10>,
+				<&edma 11>;
+			dma-names = "tx", "rx";
+		};
+
+		rng: rng@48310000 {
+			compatible = "ti,omap4-rng";
+			ti,hwmods = "rng";
+			reg = <0x48310000 0x2000>;
+			interrupts = <111>;
+		};
+	};
+};
diff --git a/arch/arm/dts/include/dt-bindings b/arch/arm/dts/include/dt-bindings
new file mode 120000
index 0000000000..0cecb3d080
--- /dev/null
+++ b/arch/arm/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 42ff384c09..7cd7f89f22 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -22,11 +22,8 @@ menu "OMAP Features"
 config MACH_OMAP
 	bool
 
-choice
-	prompt "Select OMAP Variant"
-
 config ARCH_OMAP3
-	bool "OMAP3"
+	bool
 	select CPU_V7
 	select GENERIC_GPIO
 	select OMAP_CLOCK_SOURCE_S32K
@@ -34,7 +31,7 @@ config ARCH_OMAP3
 	  Say Y here if you are using Texas Instrument's OMAP343x based platform
 
 config ARCH_OMAP4
-	bool "OMAP4"
+	bool
 	select CPU_V7
 	select GENERIC_GPIO
 	select OMAP_CLOCK_SOURCE_S32K
@@ -42,15 +39,13 @@ config ARCH_OMAP4
 	  Say Y here if you are using Texas Instrument's OMAP4 based platform
 
 config ARCH_AM33XX
-	bool "AM33xx"
+	bool
 	select CPU_V7
 	select GENERIC_GPIO
 	select OMAP_CLOCK_SOURCE_DMTIMER0
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform
 
-endchoice
-
 # Blind enable all possible clocks.. think twice before you do this.
 config OMAP_CLOCK_SOURCE_S32K
 	bool
@@ -124,65 +119,65 @@ choice
 
 config MACH_OMAP343xSDP
 	bool "Texas Instrument's SDP343x"
-	depends on ARCH_OMAP3
+	select ARCH_OMAP3
 	help
 	  Say Y here if you are using SDP343x platform
 
 config MACH_BEAGLE
 	bool "Texas Instrument's Beagle Board"
 	select HAVE_DEFAULT_ENVIRONMENT_NEW
-	depends on ARCH_OMAP3
+	select ARCH_OMAP3
 	help
 	  Say Y here if you are using Beagle Board
 
 config MACH_BEAGLEBONE
 	bool "Texas Instrument's Beagle Bone"
-	depends on ARCH_AM33XX
+	select ARCH_AM33XX
 	help
 	  Say Y here if you are using Beagle Bone
 
 config MACH_OMAP3EVM
 	bool "Texas Instrument's OMAP3 EVM"
-	depends on ARCH_OMAP3
+	select ARCH_OMAP3
 	help
 	  Say Y here if you are using OMAP3EVM
 
 config MACH_PANDA
 	bool "Texas Instrument's Panda Board"
 	select HAVE_DEFAULT_ENVIRONMENT_NEW
-	depends on ARCH_OMAP4
+	select ARCH_OMAP4
 	help
 	  Say Y here if you are using OMAP4 Panda board
 
 config MACH_ARCHOSG9
 	bool "Archos G9 tablets"
-	depends on ARCH_OMAP4
+	select ARCH_OMAP4
 	help
 	  Say Y here if you are using OMAP4-based Archos G9 tablet
 
 config MACH_PCM049
 	bool "Phytec phyCORE pcm049"
-	depends on ARCH_OMAP4
+	select ARCH_OMAP4
 	help
 	  Say Y here if you are using Phytecs phyCORE pcm049 board
 	  based on OMAP4
 
 config MACH_PCAAL1
 	bool "Phytec phyCARD-A-L1"
-	depends on ARCH_OMAP3
+	select ARCH_OMAP3
 	help
 	  Say Y here if you are using a phyCARD-A-L1 PCA-A-L1
 
 config MACH_PCAAXL2
 	bool "Phytec phyCARD XL2"
-	depends on ARCH_OMAP4
+	select ARCH_OMAP4
 	help
 	  Say Y here if you are using a phyCARD-A-XL1 PCA-A-XL1
 
 config MACH_PCM051
 	bool "Phytec phyCORE pcm051"
 	select HAVE_DEFAULT_ENVIRONMENT_NEW
-	depends on ARCH_AM33XX
+	select ARCH_AM33XX
 	help
 	  Say Y here if you are using Phytecs phyCORE pcm051 board
 
@@ -193,6 +188,7 @@ if ARCH_OMAP
 choice
 	prompt "Select UART"
 	default OMAP_UART3
+	depends on MACH_OMAP3EVM
 
 	config OMAP_UART1
 		bool "Use UART1"
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index cf2d5ee7dd..2de78d7c7f 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
-obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
+obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
 obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
 pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
 obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
index 692b0ec97b..9105ddc8b8 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -276,7 +276,7 @@ static void ddr_pll_config(int osc, int ddrpll_M)
 	while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
 }
 
-void enable_ddr_clocks(void)
+void am33xx_enable_ddr_clocks(void)
 {
 	/* Enable the  EMIF_FW Functional clock */
 	__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
@@ -293,7 +293,7 @@ void enable_ddr_clocks(void)
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */
-void pll_init(int mpupll_M, int osc, int ddrpll_M)
+void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M)
 {
 	mpu_pll_config(mpupll_M, osc);
 	core_pll_config(osc);
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 3e2b6c4e15..68dc9338f6 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -30,7 +30,7 @@
 #include <mach/am33xx-generic.h>
 #include <mach/gpmc.h>
 
-void __noreturn reset_cpu(unsigned long addr)
+void __noreturn am33xx_reset_cpu(unsigned long addr)
 {
 	writel(AM33XX_PRM_RSTCTRL_RESET, AM33XX_PRM_RSTCTRL);
 
@@ -68,7 +68,7 @@ u32 am33xx_get_cpu_rev(void)
  *
  * @return base address
  */
-u32 get_base(void)
+static u32 get_base(void)
 {
 	u32 val;
 	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
@@ -84,7 +84,7 @@ u32 get_base(void)
  *
  * @return 1 if we are running in XIP mode, else return 0
  */
-u32 running_in_flash(void)
+u32 am33xx_running_in_flash(void)
 {
 	if (get_base() < 4)
 		return 1;	/* in flash */
@@ -98,7 +98,7 @@ u32 running_in_flash(void)
  *
  * @return  1 if we are running in SRAM, else return 0
  */
-u32 running_in_sram(void)
+u32 am33xx_running_in_sram(void)
 {
 	if (get_base() == 4)
 		return 1;	/* in SRAM */
@@ -113,7 +113,7 @@ u32 running_in_sram(void)
  *
  * @return 1 if we are running from SDRAM, else return 0
  */
-u32 running_in_sdram(void)
+u32 am33xx_running_in_sdram(void)
 {
 	if (get_base() > 4)
 		return 1;	/* in sdram */
@@ -147,7 +147,6 @@ static int am33xx_bootsource(void)
 	bootsource_set_instance(instance);
 	return 0;
 }
-postcore_initcall(am33xx_bootsource);
 
 int am33xx_register_ethaddr(int eth_id, int mac_id)
 {
@@ -199,7 +198,18 @@ static int am33xx_gpio_init(void)
 				0xf00, IORESOURCE_MEM, NULL);
 	return 0;
 }
-coredevice_initcall(am33xx_gpio_init);
+
+int am33xx_init(void)
+{
+	omap_gpmc_base = (void *)AM33XX_GPMC_BASE;
+
+	return am33xx_bootsource();
+}
+
+int am33xx_devices_init(void)
+{
+	return am33xx_gpio_init();
+}
 
 /* UART Defines */
 #define UART_SYSCFG_OFFSET	0x54
@@ -337,7 +347,7 @@ void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
 {
 	uint32_t val;
 
-	enable_ddr_clocks();
+	am33xx_enable_ddr_clocks();
 
 	am33xx_config_vtp();
 
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index bb84b38650..72f7236cb4 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -30,24 +30,7 @@
 #include <mach/gpmc.h>
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
-
-void __iomem *omap_gpmc_base;
-
-static int gpmc_init(void)
-{
-#if defined(CONFIG_ARCH_OMAP3)
-	omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
-#elif defined(CONFIG_ARCH_OMAP4)
-	omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE;
-#elif defined(CONFIG_ARCH_AM33XX)
-	omap_gpmc_base = (void *)AM33XX_GPMC_BASE;
-#else
-#error "Unknown ARCH"
-#endif
-
-	return 0;
-}
-pure_initcall(gpmc_init);
+#include <mach/generic.h>
 
 /**
  * @brief Do a Generic initialization of GPMC. if you choose otherwise,
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index ecd90b2229..65fbed6935 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -184,7 +184,7 @@
 
 #define CM_ALWON_GPMC_CLKCTRL           CM_PER_GPMC_CLKCTRL
 
-extern void pll_init(int mpupll_M, int osc, int ddrpll_M);
-extern void enable_ddr_clocks(void);
+void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M);
+void am33xx_enable_ddr_clocks(void);
 
 #endif  /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index ec22ad201a..e74a666f3f 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -22,4 +22,13 @@ static inline void am33xx_save_bootinfo(uint32_t *info)
 	omap_save_bootinfo(info);
 }
 
+u32 am33xx_running_in_flash(void);
+u32 am33xx_running_in_sram(void);
+u32 am33xx_running_in_sdram(void);
+
+void __noreturn am33xx_reset_cpu(unsigned long addr);
+
+int am33xx_init(void);
+int am33xx_devices_init(void);
+
 #endif /* __MACH_AM33XX_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h b/arch/arm/mach-omap/include/mach/debug_ll.h
index 2917558732..25ddd485be 100644
--- a/arch/arm/mach-omap/include/mach/debug_ll.h
+++ b/arch/arm/mach-omap/include/mach/debug_ll.h
@@ -18,31 +18,9 @@
 #define   __MACH_DEBUG_LL_H__
 
 #include <io.h>
-
-#ifdef CONFIG_ARCH_OMAP3
 #include <mach/omap3-silicon.h>
-
-#ifdef CONFIG_OMAP_UART1
-#define UART_BASE	OMAP3_UART1_BASE
-#else
-#define UART_BASE	OMAP3_UART3_BASE
-#endif
-
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
 #include <mach/omap4-silicon.h>
-#ifdef CONFIG_OMAP_UART1
-#define UART_BASE	OMAP44XX_UART1_BASE
-#else
-#define UART_BASE	OMAP44XX_UART3_BASE
-#endif
-#endif
-
-#ifdef CONFIG_ARCH_AM33XX
 #include <mach/am33xx-silicon.h>
-#define UART_BASE	AM33XX_UART0_BASE
-#endif
 
 #define LSR_THRE	0x20	/* Xmit holding register empty */
 #define LCR_BKSE	0x80	/* Bank select enable */
@@ -56,26 +34,47 @@
 #define MCR		(4 << 2)
 #define MDR		(8 << 2)
 
-static inline void omap_uart_lowlevel_init(void)
+static inline void omap_uart_lowlevel_init(void __iomem *base)
 {
-	writeb(0x00, UART_BASE + LCR);
-	writeb(0x00, UART_BASE + IER);
-	writeb(0x07, UART_BASE + MDR);
-	writeb(LCR_BKSE, UART_BASE + LCR);
-	writeb(26, UART_BASE + DLL); /* 115200 */
-	writeb(0, UART_BASE + DLM);
-	writeb(0x03, UART_BASE + LCR);
-	writeb(0x03, UART_BASE + MCR);
-	writeb(0x07, UART_BASE + FCR);
-	writeb(0x00, UART_BASE + MDR);
+	writeb(0x00, base + LCR);
+	writeb(0x00, base + IER);
+	writeb(0x07, base + MDR);
+	writeb(LCR_BKSE, base + LCR);
+	writeb(26, base + DLL); /* 115200 */
+	writeb(0, base + DLM);
+	writeb(0x03, base + LCR);
+	writeb(0x03, base + MCR);
+	writeb(0x07, base + FCR);
+	writeb(0x00, base + MDR);
 }
+
+#ifdef CONFIG_DEBUG_LL
+
+#ifdef CONFIG_DEBUG_OMAP3_UART
+#define OMAP_DEBUG_SOC OMAP3
+#elif defined CONFIG_DEBUG_OMAP4_UART
+#define OMAP_DEBUG_SOC OMAP44XX
+#elif defined CONFIG_DEBUG_AM33XX_UART
+#define OMAP_DEBUG_SOC AM33XX
+#else
+#error "unknown OMAP debug uart soc type"
+#endif
+
+#define __OMAP_UART_BASE(soc, num) soc##_UART##num##_BASE
+#define OMAP_UART_BASE(soc, num) __OMAP_UART_BASE(soc, num)
+
 static inline void PUTC_LL(char c)
 {
+	void __iomem *base = (void *)OMAP_UART_BASE(OMAP_DEBUG_SOC,
+			CONFIG_DEBUG_OMAP_UART_PORT);
+
 	/* Wait until there is space in the FIFO */
-	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
+	while ((readb(base + LSR) & LSR_THRE) == 0);
 	/* Send the character */
-	writeb(c, UART_BASE + THR);
+	writeb(c, base + THR);
 	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
+	while ((readb(base + LSR) & LSR_THRE) == 0);
 }
 #endif
+
+#endif
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
index b05fdeee91..f4e18f3244 100644
--- a/arch/arm/mach-omap/include/mach/generic.h
+++ b/arch/arm/mach-omap/include/mach/generic.h
@@ -10,28 +10,46 @@
 #define OMAP_I2C_REV_ON_3630            0x00000040
 #define OMAP_I2C_REV_ON_4430_PLUS       0x50400002
 
-#ifdef CONFIG_ARCH_OMAP
-#define cpu_is_omap2430()	(1)
-#else
-#define cpu_is_omap2430()	(0)
-#endif
+extern unsigned int __omap_cpu_type;
+
+#define OMAP_CPU_OMAP3		3
+#define OMAP_CPU_OMAP4		4
+#define OMAP_CPU_AM33XX		33
 
 #ifdef CONFIG_ARCH_OMAP3
-#define cpu_is_omap34xx()	(1)
+# ifdef omap_cpu_type
+#  undef omap_cpu_type
+#  define omap_cpu_type __omap_cpu_type
+# else
+#  define omap_cpu_type OMAP_CPU_OMAP3
+# endif
+# define cpu_is_omap3()		(omap_cpu_type == OMAP_CPU_OMAP3)
 #else
-#define cpu_is_omap34xx()	(0)
+# define cpu_is_omap3()		(0)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-#define cpu_is_omap4xxx()	(1)
+# ifdef omap_cpu_type
+#  undef omap_cpu_type
+#  define omap_cpu_type __omap_cpu_type
+# else
+#  define omap_cpu_type OMAP_CPU_OMAP4
+# endif
+# define cpu_is_omap4()		(omap_cpu_type == OMAP_CPU_OMAP4)
 #else
-#define cpu_is_omap4xxx()	(0)
+# define cpu_is_omap4()		(0)
 #endif
 
 #ifdef CONFIG_ARCH_AM33XX
-#define cpu_is_am33xx()		(1)
+# ifdef omap_cpu_type
+#  undef omap_cpu_type
+#  define omap_cpu_type __omap_cpu_type
+# else
+#  define omap_cpu_type OMAP_CPU_AM33XX
+# endif
+# define cpu_is_am33xx()		(omap_cpu_type == OMAP_CPU_AM33XX)
 #else
-#define cpu_is_am33xx()		(0)
+# define cpu_is_am33xx()	(0)
 #endif
 
 struct omap_barebox_part {
diff --git a/arch/arm/mach-omap/include/mach/omap3-generic.h b/arch/arm/mach-omap/include/mach/omap3-generic.h
index 7f0da4e331..2210d879fe 100644
--- a/arch/arm/mach-omap/include/mach/omap3-generic.h
+++ b/arch/arm/mach-omap/include/mach/omap3-generic.h
@@ -1,6 +1,7 @@
 #ifndef __MACH_OMAP3_GENERIC_H
 #define __MACH_OMAP3_GENERIC_H
 
+#include <sizes.h>
 #include <mach/generic.h>
 #include <mach/omap3-silicon.h>
 
@@ -18,4 +19,13 @@ static inline void omap3_save_bootinfo(uint32_t *info)
 	omap_save_bootinfo(info);
 }
 
+u32 omap3_running_in_flash(void);
+u32 omap3_running_in_sram(void);
+u32 omap3_running_in_sdram(void);
+
+void __noreturn omap3_reset_cpu(unsigned long addr);
+
+int omap3_init(void);
+int omap3_devices_init(void);
+
 #endif /* __MACH_OMAP3_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h
index 44f5a12788..85c92e1a5e 100644
--- a/arch/arm/mach-omap/include/mach/omap4-generic.h
+++ b/arch/arm/mach-omap/include/mach/omap4-generic.h
@@ -18,4 +18,9 @@ static inline void omap4_save_bootinfo(uint32_t *info)
 	omap_save_bootinfo(info);
 }
 
+void __noreturn omap4_reset_cpu(unsigned long addr);
+
+int omap4_init(void);
+int omap4_devices_init(void);
+
 #endif /* __MACH_OMAP4_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index fce5895554..fbac9b571f 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -91,10 +91,6 @@ u32 get_cpu_rev(void);
 u32 get_sdr_cs_size(u32 offset);
 u32 get_sdr_cs1_base(void);
 inline u32 get_sysboot_value(void);
-u32 get_base(void);
-u32 running_in_flash(void);
-u32 running_in_sram(void);
-u32 running_in_sdram(void);
 u32 get_boot_type(void);
 u32 get_device_type(void);
 
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 03aca492a1..6700f56f39 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -33,6 +33,7 @@
 #include <common.h>
 #include <io.h>
 #include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
 #include <mach/clocks.h>
 #include <mach/omap3-clock.h>
 #include <mach/timers.h>
@@ -170,7 +171,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
 
 	dp += clk_sel;
 
-	if (running_in_sram()) {
+	if (omap3_running_in_sram()) {
 		sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
 		wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
 
@@ -209,7 +210,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
 		/* Lock Mode */
 		sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
 		wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
-	} else if (running_in_flash()) {
+	} else if (omap3_running_in_flash()) {
 		/***Oopps.. Wrong .config!! *****/
 		hang();
 	}
@@ -403,7 +404,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
 
 	dp += clk_sel;
 
-	if (running_in_sram()) {
+	if (omap3_running_in_sram()) {
 		sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
 		wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
 
@@ -435,7 +436,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
 		/* Lock Mode */
 		sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
 		wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
-	} else if (running_in_flash()) {
+	} else if (omap3_running_in_flash()) {
 		/***Oopps.. Wrong .config!! *****/
 		hang();
 	}
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 8b661ff794..d36d63b6a6 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -52,7 +52,7 @@
  *
  * @return void
  */
-void __noreturn reset_cpu(unsigned long addr)
+void __noreturn omap3_reset_cpu(unsigned long addr)
 {
 	writel(OMAP3_PRM_RSTCTRL_RESET, OMAP3_PRM_REG(RSTCTRL));
 
@@ -213,7 +213,7 @@ inline u32 get_sysboot_value(void)
  *
  * @return base address
  */
-u32 get_base(void)
+static u32 get_base(void)
 {
 	u32 val;
 	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
@@ -229,7 +229,7 @@ u32 get_base(void)
  *
  * @return 1 if we are running in XIP mode, else return 0
  */
-u32 running_in_flash(void)
+u32 omap3_running_in_flash(void)
 {
 	if (get_base() < 4)
 		return 1;	/* in flash */
@@ -243,7 +243,7 @@ u32 running_in_flash(void)
  *
  * @return  1 if we are running in SRAM, else return 0
  */
-u32 running_in_sram(void)
+u32 omap3_running_in_sram(void)
 {
 	if (get_base() == 4)
 		return 1;	/* in SRAM */
@@ -258,13 +258,13 @@ u32 running_in_sram(void)
  *
  * @return 1 if we are running from SDRAM, else return 0
  */
-u32 running_in_sdram(void)
+u32 omap3_running_in_sdram(void)
 {
 	if (get_base() > 4)
 		return 1;	/* in sdram */
 	return 0;		/* running in SRAM or FLASH */
 }
-EXPORT_SYMBOL(running_in_sdram);
+EXPORT_SYMBOL(omap3_running_in_sdram);
 
 /**
  * @brief Is this an XIP type device or a stream one
@@ -408,7 +408,7 @@ void setup_auxcr(void);
 static void try_unlock_memory(void)
 {
 	int mode;
-	int in_sdram = running_in_sdram();
+	int in_sdram = omap3_running_in_sdram();
 
 	/* if GP device unlock device SRAM for general use */
 	/* secure code breaks for Secure/Emulation device - HS/E/T */
@@ -489,7 +489,13 @@ static int omap3_bootsource(void)
 
 	return 0;
 }
-postcore_initcall(omap3_bootsource);
+
+int omap3_init(void)
+{
+	omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
+
+	return omap3_bootsource();
+}
 
 /* GPMC timing for OMAP3 nand device */
 const struct gpmc_config omap3_nand_cfg = {
@@ -525,5 +531,9 @@ static int omap3_gpio_init(void)
 
 	return 0;
 }
-coredevice_initcall(omap3_gpio_init);
+
+int omap3_devices_init(void)
+{
+	return omap3_gpio_init();
+}
 #endif
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 6da5cae567..5dde51ad15 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -34,7 +34,7 @@
 #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0		0x0A0000FF
 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
 
-void __noreturn reset_cpu(unsigned long addr)
+void __noreturn omap4_reset_cpu(unsigned long addr)
 {
 	writel(OMAP44XX_PRM_RSTCTRL_RESET, OMAP44XX_PRM_RSTCTRL);
 
@@ -470,6 +470,9 @@ static int watchdog_init(void)
 {
 	void __iomem *wd2_base = (void *)OMAP44XX_WDT2_BASE;
 
+	if (!cpu_is_omap4())
+		return 0;
+
 	writel(WD_UNLOCK1, wd2_base + WATCHDOG_WSPR);
 	wait_for_command_complete();
 	writel(WD_UNLOCK2, wd2_base + WATCHDOG_WSPR);
@@ -524,7 +527,13 @@ static int omap4_bootsource(void)
 
 	return 0;
 }
-core_initcall(omap4_bootsource);
+
+int omap4_init(void)
+{
+	omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE;
+
+	return omap4_bootsource();
+}
 
 #define GPIO_MASK 0x1f
 
@@ -668,4 +677,8 @@ static int omap4_gpio_init(void)
 
 	return 0;
 }
-coredevice_initcall(omap4_gpio_init);
+
+int omap4_devices_init(void)
+{
+	return omap4_gpio_init();
+}
diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c
index 79e37e2341..47fa9ba958 100644
--- a/arch/arm/mach-omap/omap_generic.c
+++ b/arch/arm/mach-omap/omap_generic.c
@@ -21,19 +21,28 @@
 #include <fs.h>
 #include <malloc.h>
 #include <linux/stat.h>
+#include <mach/gpmc.h>
 #include <mach/generic.h>
 #include <mach/am33xx-silicon.h>
 #include <mach/omap3-silicon.h>
 #include <mach/omap4-silicon.h>
+#include <mach/am33xx-generic.h>
+#include <mach/omap3-generic.h>
+#include <mach/omap4-generic.h>
+
+void __iomem *omap_gpmc_base;
+
+unsigned int __omap_cpu_type;
 
 static void *omap_sram_start(void)
 {
 	if (cpu_is_am33xx())
 		return (void *)AM33XX_SRAM0_START;
-	if (cpu_is_omap34xx())
+	if (cpu_is_omap3())
 		return (void *)OMAP3_SRAM_BASE;
-	if (cpu_is_omap4xxx())
+	if (cpu_is_omap4())
 		return (void *)OMAP44XX_SRAM_BASE;
+	return NULL;
 }
 
 void __noreturn omap_start_barebox(void *barebox)
@@ -130,3 +139,63 @@ static int omap_env_init(void)
 }
 late_initcall(omap_env_init);
 #endif
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+	if (cpu_is_omap3())
+		omap3_reset_cpu(addr);
+	if (cpu_is_omap4())
+		omap4_reset_cpu(addr);
+	if (cpu_is_am33xx())
+		am33xx_reset_cpu(addr);
+	while (1);
+}
+
+static int omap_soc_from_dt(void)
+{
+        if (of_machine_is_compatible("ti,am33xx"))
+		return OMAP_CPU_AM33XX;
+        if (of_machine_is_compatible("ti,omap4"))
+		return OMAP_CPU_OMAP4;
+        if (of_machine_is_compatible("ti,omap3"))
+		return OMAP_CPU_OMAP3;
+
+	return 0;
+}
+
+static int omap_init(void)
+{
+	int ret;
+	struct device_node *root;
+
+	root = of_get_root_node();
+	if (root) {
+		__omap_cpu_type = omap_soc_from_dt();
+		if (!__omap_cpu_type)
+			hang();
+	}
+
+	if (cpu_is_omap3())
+		ret = omap3_init();
+	else if (cpu_is_omap4())
+		ret = omap4_init();
+	else if (cpu_is_am33xx())
+		ret = am33xx_init();
+	else
+		return -EINVAL;
+
+	if (root)
+		return ret;
+
+	if (cpu_is_omap3())
+		ret = omap3_devices_init();
+	else if (cpu_is_omap4())
+		ret = omap4_devices_init();
+	else if (cpu_is_am33xx())
+		ret = am33xx_devices_init();
+	else
+		return -EINVAL;
+
+	return ret;
+}
+postcore_initcall(omap_init);
diff --git a/common/Kconfig b/common/Kconfig
index 2b687514f8..4e460051c8 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -749,6 +749,27 @@ config DEBUG_IMX6Q_UART
 	  Say Y here if you want kernel low-level debugging support
 	  on i.MX6Q.
 
+config DEBUG_OMAP3_UART
+	bool "OMAP3 Debug UART"
+	depends on ARCH_OMAP3
+	help
+	  Say Y here if you want kernel low-level debugging support
+	  on OMAP3.
+
+config DEBUG_OMAP4_UART
+	bool "OMAP4 Debug UART"
+	depends on ARCH_OMAP4
+	help
+	  Say Y here if you want kernel low-level debugging support
+	  on OMAP4.
+
+config DEBUG_AM33XX_UART
+	bool "AM33XX Debug UART"
+	depends on ARCH_AM33XX
+	help
+	  Say Y here if you want kernel low-level debugging support
+	  on AM33XX.
+
 endchoice
 
 config DEBUG_IMX_UART_PORT
@@ -768,6 +789,19 @@ config DEBUG_IMX_UART_PORT
 	  Choose UART port on which kernel low-level debug messages
 	  should be output.
 
+config DEBUG_OMAP_UART_PORT
+	int "OMAP Debug UART Port Selection" if DEBUG_OMAP3_UART || \
+						DEBUG_OMAP4_UART || \
+						DEBUG_AM33XX_UART
+	default 1
+	depends on ARCH_OMAP
+	help
+	  Choose UART port on which kernel low-level debug messages
+	  should be output. Possible values are:
+	  OMAP3: 1 - 3
+	  OMAP4: 1 - 3
+	  AM33XX: 0 - 2
+
 config DEBUG_INITCALLS
 	bool "Trace initcalls"
 	help
diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c
index 19db461e0d..357d99a0db 100644
--- a/drivers/mci/omap_hsmmc.c
+++ b/drivers/mci/omap_hsmmc.c
@@ -620,6 +620,12 @@ static int omap_mmc_probe(struct device_d *dev)
 			hsmmc->mci.devname = pdata->devname;
 	}
 
+	if (dev->device_node) {
+		const char *alias = of_alias_get(dev->device_node);
+		if (alias)
+			hsmmc->mci.devname = xstrdup(alias);
+	}
+
 	dev->priv = hsmmc;
 	dev->detect = omap_mmc_detect,
 
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index 5eed83c2d9..2fca1b7ecd 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -13,22 +13,22 @@ $(obj)/%.socfpgaimg: $(obj)/% FORCE
 # ----------------------- Cyclone5 based boards ---------------------------
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
 FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
 
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit
 FILE_barebox-socfpga-sockit.img = start_socfpga_sockit.pblx
-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit.img
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit.img
 
 pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates_xload
 FILE_barebox-socfpga-socrates-xload.img = start_socfpga_socrates_xload.pblx.socfpgaimg
-xload-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates-xload.img
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates-xload.img
 
 pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates
 FILE_barebox-socfpga-socrates.img = start_socfpga_socrates.pblx
-barebox-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates.img
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates.img
 
 ifdef CONFIG_ARCH_SOCFPGA_XLOAD
-image-y += $(xload-y)
+image-y += $(socfpga-xload-y)
 else
-image-y += $(barebox-y)
+image-y += $(socfpga-barebox-y)
 endif
diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
new file mode 100644
index 0000000000..e6b1e0a808
--- /dev/null
+++ b/include/dt-bindings/gpio/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
new file mode 100644
index 0000000000..2fbc804e1a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -0,0 +1,42 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE		(1 << 3)
+#define INPUT_EN		(1 << 5)
+#define SLEWCTRL_FAST		(1 << 6)
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000000..bed35e36fd
--- /dev/null
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,53 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* omap3/4/5 specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
+#endif
+
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 3ff094f018..6ccf5726c7 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -29,6 +29,9 @@ else
 obj-y		+= $(lwl-y)
 endif
 
+obj-y		+= $(obj-pbl-y)
+pbl-y		+= $(obj-pbl-y)
+
 # for non dirs add pbl- prefix to the target
 # so we recompile the source with custom flags and custom quiet
 __pbl-y		:= $(notdir $(pbl-y))