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This is a port of Linux kernel commit
| commit 30a2c8aa3c520d54bcaf3015ca8141b0156448b1
| Author: Roger Pueyo Centelles <roger.pueyo@guifi.net>
| Date: Thu Feb 7 20:09:35 2019 +0100
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| mtd: spi-nor: Add support for en25qh64
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| The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found
| on recent wireless routers. Its 32, 128 and 256 Mbit siblings
| are already supported.
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| Tested on a COMFAST CF-E120A v3 router board.
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| Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net>
| Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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not found
When the linux,default-trigger is not found by barebox, then also check if
there might be a barebox,default-trigger.
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Currently we have two slightly different led-trigger tables. One in the
core module, and the other one in the led-triggers module. The one in the
core module, which is used to parse the device-tree triggers, is lacking
net-rx and net-tx.
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The iommu-map properties are needed for proper PCI support under Linux.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Rename 'arr' to 'msi_map' which is a better name when we add another
array in the next patch.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Isolation Context Identifiers (icid) have to be configured in the
hardware and communicated to the Kernel via device tree fixups. This
adds the missing bits and pieces to make the IOMMU work under Linux.
As of Linux-5.5 the SMMU doesn't work out of the box. This series has
been tested in conjunction with this Kernel series:
https://lore.kernel.org/patchwork/cover/997994/
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux depends on the icid values configured in the DPAA. Do not put
the hardware into reset in order to preserve the register values.
Without this, the IOMMU doesn't work properly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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struct ccsr_qman is ifdeffed for different versions of this structure.
CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use
the wrong version on LS1046a. Hardcode it to the v3 version to make
it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious
that it needs a change on non v3 versions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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include/soc/fsl/fsl_qbman.h contains function prototypes we do not
implement, drop them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The icid tables are generated with several macros which makes the code
hard to read. Drop the macros.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If the whole image already resides in DRAM, e.g. by starting the
image via the bootm handler we try to load the piggydata from storage,
which may well be different from our expected piggydata, already
present in DRAM.
Fix this by avoiding the special piggydata load function, but instead
load the whole image after DRAM is up and just replace the PBL part to
ensure we are still running the HAB validated code after TF-A hands
back control to our code in DRAM.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add an option that allows to just load the image into memory, but
return to the calling function instead of directly jumping to the
loaded image.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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the whole barebox with mbr and partition table were be signed by default.
change the signing to the executed image without signing the mbr,
partition table and header_gap by imx8mq
additional delete option full, from-dcdofs and skip-mbr
Signed-off-by: Maik Otto <m.otto@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The comment above nxp_imx8mq_evk_start is no longer accurate, as there
is no trampoline in DRAM anymore. Change the comment to reflect the current
boot flow.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Mostly cosmetic changes:
- reduce scope of local variabes
- wrap comment to fir 80 char limit
- check return value from imx8_esdhc_load_piggy
- drop intermediate function that only wraps a single other function
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use the variables defined in sections.h, instead of hand rolling the
same computation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Adds scripts for network detection in development case and
autoboot from the SD card.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The electrical issues that caused the i2c bus to lock up at higher frequencies
has been tracked down and solved by a improved i2c pin configuration, so it's
no longer required to reduce the bus frequency.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Ruslan Sushko <Ruslan.Sushko@zii.aero>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For the iNVM change to take effect we need to reset the i210 adapter.
As this is not really possible in isolation in Barebox, we just go
through a full machine reset cycle. As this should only happen once
during the lifetime of each device there is no need for a more
elaborate solution.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There are only two fixups we need to apply at the moment:
- The 27" RMB3 based unit has a eGalax Touchscreen instead of Synaptics.
- The 10.1" SCU/CCU unit has no DEB and thus no switch, but instead the
i210 ethernet is routed to the external connector directly.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We only have a single update target, so make it the default.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For NAND flash with eraseblock size 1 MB and more the current
barebox partition size is not sufficient. The 4 FCB copies alone occupy
the 4 MB partition size. Increase the partition size to 16 MB to be fit
for the future and leaving some blocks for bad block handling as well.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The SD card interface is still using the legacy partition binding.
Change this by switching to the new bindings.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The EEPROM is a configurable option. So make it configurable from the
dts file.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use the simpler name phycard instead of the article number pcaaxl3
for device tree file names and image names of the phyCARD-i.MX 6.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make use of SPDX license identifiers and update copyright notices and
model descriptions of the phyCARD-i.MX 6 SOM.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Bring the device tree nodes in alphabetical order and in this context
also remove the deprecated iomux group.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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So far changing the DCD table didn't trigger a rerun of the i.MX
image utility. To fix this, we need to have the DCD table as prerequisite
to the .imximg rule. The file name is contained in $(CFG_$(@F)), but
can't be used directly because $@ (and by extension @F) has no value
when first expanded in the read-in phase. If we expand a second time
during the target-update phase however, we would get the correct value.
GNU make provides .SECONDEXPANSION to expand all following prerequisites
a second time. Use it to have changes to the DCD table rebuild the
image.
Because we are now using imx_image_rule to generate the target, we must
escape each $ one more time to arrive at $$$$(CFG_$$$$(@F)).
In the final step, we replace $$$$(@F) with %.imximg, so we support the
rules not ending in .imximg as well.
Dependency file generation is still broken however and changed to headers
included in DCD tables won't be caught, but this functionality can be
fixed in a separate patch.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The next patch will add the .imxcfg file as a rule prerequisite, so the
target is rebuilt if it changes. Instead of duplicating it in all rules,
factor out the common parts into a imx_image_rule variable.
As the arguments are now going through an eval, any use of $ must be
escaped with another $ to become $$.
No functional change.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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So far arm_early_mmu_cache_flush has only been used in preparation for
executing newly-written code. For this reason, on ARMv7 and below,
it had always invalidate the icache after the dcache flush.
We don't do this on ARM64, but sync_caches_for_execution depends on this,
which had this comment that didn't hold true for ARM64:
> Despite the name arm_early_mmu_cache_flush not only flushes the
> data cache, but also invalidates the instruction cache.
It might be worthwhile to decouple dcache flushing from icache
invalidation, but for now, align what we do on ARM64 with what we do for
32-bit ARMs.
This fixes a potential read of stale instructions when loading
second-stage barebox from the PBL with MMU disabled.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On some ARM cores, cache contents are indeterminate after a Power-On
Reset. Turning on the MMU on such cores risks interpreting random cache
lines as valid, causing hard-to-debug errors.
For this reason, we always invalidate the dcache on <= ARMv7. Let's do
likewise for ARM64. Newer ARM cores tend to come up with their dcaches
invalidated already, but for some, like the Cortex-A72, L2 caches are
invalidated dependent on a signal sampled at reset, so better play
it safe.
The icache invalidate here seems to serve no useful purpose. It's kept
for now for symmetry with ARM32.
Note that this is wrong should barebox be entered with the MMU enabled,
but this is so far not the case with any ARM64 platform we support.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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