From 2ad6b513b31070bd0c003792ed1c3e7f5d740357 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 18:44:42 -0600 Subject: mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi --- README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'README') diff --git a/README b/README index 6b94f8482c..5c907c8f07 100644 --- a/README +++ b/README @@ -2249,6 +2249,14 @@ Low Level (hardware related) configuration options: If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with. +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + - CONFIG_ETHER_ON_FEC[12] Define to enable FEC[12] on a 8xx series processor. -- cgit v1.2.1