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authorYang Rong <rong.r.yang@intel.com>2015-12-28 10:40:14 +0800
committerYang Rong <rong.r.yang@intel.com>2016-01-05 15:23:16 +0800
commit31891068c8d57d28260dd2c7ef8ca4faf8cffe7e (patch)
tree6b66b97042b1ce57fff7d0c0671889e08da2e99a
parentaecf78ef4cfc649e5faf9ef613567a5d98ff480e (diff)
downloadbeignet-31891068c8d57d28260dd2c7ef8ca4faf8cffe7e.tar.gz
SKL: use the hw defautl value mocs index before linux 4.3.
From linux 4.3, kernel redefined the mocs table's value, But before 4.3, still used the hw defautl value. Signed-off-by: Yang Rong <rong.r.yang@intel.com> Reviewed-by: Ruiling Song <ruiling.song@intel.com>
-rw-r--r--src/intel/intel_gpgpu.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index dfe2af38..b55e0751 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -26,6 +26,7 @@
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
+#include <sys/utsname.h>
#include <fcntl.h>
#include <stddef.h>
#include <errno.h>
@@ -284,7 +285,20 @@ intel_gpgpu_get_cache_ctrl_gen9()
{
//Kernel-defined cache control registers 2:
//L3CC: WB; LeCC: WB; TC: LLC/eLLC;
- return (0x2 << 1);
+ int major = 0, minor = 0;
+ int mocs_index = 0x2;
+
+ struct utsname buf;
+ uname(&buf);
+ sscanf(buf.release, "%d.%d", &major, &minor);
+ //From linux 4.3, kernel redefined the mocs table's value,
+ //But before 4.3, still used the hw defautl value.
+ if(strcmp(buf.sysname, "Linux") == 0 &&
+ major == 4 && minor < 3) { /* linux kernel support skl from 4.x, so check from 4 */
+ mocs_index = 0x9;
+ }
+
+ return (mocs_index << 1);
}
static void