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-rw-r--r--src/cl_command_queue.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cl_command_queue.c b/src/cl_command_queue.c
index 05be801c..0be37a72 100644
--- a/src/cl_command_queue.c
+++ b/src/cl_command_queue.c
@@ -17,6 +17,7 @@
* Author: Benjamin Segovia <benjamin.segovia@intel.com>
*/
+#include "program.h" // for BTI_MAX_IMAGE_NUM
#include "cl_command_queue.h"
#include "cl_context.h"
#include "cl_program.h"
@@ -141,9 +142,11 @@ cl_command_queue_bind_image(cl_command_queue queue, cl_kernel k)
cl_gpgpu_bind_image(gpgpu, k->images[i].idx, image->base.bo, image->offset,
image->intel_fmt, image->image_type,
image->w, image->h, image->depth,
- image->row_pitch, image->tiling);
+ image->row_pitch, (cl_gpgpu_tiling)image->tiling);
+ // TODO, this workaround is for GEN7/GEN75 only, we may need to do it in the driver layer
+ // on demand.
if (image->image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY)
- cl_gpgpu_bind_image(gpgpu, k->images[i].idx + 128, image->base.bo, image->offset,
+ cl_gpgpu_bind_image(gpgpu, k->images[i].idx + BTI_MAX_IMAGE_NUM, image->base.bo, image->offset,
image->intel_fmt, image->image_type,
image->w, image->h, image->depth,
image->row_pitch, image->tiling);