From afd050f68315d5f38928e1b6ec7faa51e6e14bc2 Mon Sep 17 00:00:00 2001 From: "Song, Ruiling" Date: Wed, 13 Sep 2017 14:07:26 +0800 Subject: backend: use simd-1 for scalar dst in indirectMov. This fix a failure introduced by load-store optimization on IVB. the test case is: builtin_kernel_block_motion_estimate_intel Signed-off-by: Ruiling Song Reviewed-by: Yang Rong --- backend/src/backend/gen_context.cpp | 38 +++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 0b171ff9..6fc3159b 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -1949,23 +1949,33 @@ namespace gbe indirect_src = GenRegister::indirect(dst.type, 0, GEN_WIDTH_1, GEN_VERTICAL_STRIDE_ONE_DIMENSIONAL, GEN_HORIZONTAL_STRIDE_0); - p->push(); - p->curr.execWidth = 8; - p->curr.quarterControl = GEN_COMPRESSION_Q1; - p->MOV(a0, tmp); - p->MOV(dst, indirect_src); - p->pop(); - - if (simdWidth == 16) { + if (sel->isScalarReg(dst.reg())) { + p->push(); + p->curr.execWidth = 1; + p->curr.predicate = GEN_PREDICATE_NONE; + p->curr.noMask = 1; + p->MOV(a0, tmp); + p->MOV(dst, indirect_src); + p->pop(); + } else { p->push(); p->curr.execWidth = 8; - p->curr.quarterControl = GEN_COMPRESSION_Q2; - - const GenRegister nextDst = GenRegister::Qn(dst, 1); - const GenRegister nextOffset = GenRegister::Qn(tmp, 1); - p->MOV(a0, nextOffset); - p->MOV(nextDst, indirect_src); + p->curr.quarterControl = GEN_COMPRESSION_Q1; + p->MOV(a0, tmp); + p->MOV(dst, indirect_src); p->pop(); + + if (simdWidth == 16) { + p->push(); + p->curr.execWidth = 8; + p->curr.quarterControl = GEN_COMPRESSION_Q2; + + const GenRegister nextDst = GenRegister::Qn(dst, 1); + const GenRegister nextOffset = GenRegister::Qn(tmp, 1); + p->MOV(a0, nextOffset); + p->MOV(nextDst, indirect_src); + p->pop(); + } } } -- cgit v1.2.1