diff options
| author | Yao Qi <yao.qi@linaro.org> | 2016-09-16 14:58:31 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-09-21 12:29:53 +0100 |
| commit | fc6cda2ee85d2c2719db3b5ae3a1ae963f28416b (patch) | |
| tree | 6fffa61c201da1162d729cd919d3fc5608d1d70d | |
| parent | 44b8317a75390fd3713da6d8cc0f593c041fd8a2 (diff) | |
| download | binutils-gdb-fc6cda2ee85d2c2719db3b5ae3a1ae963f28416b.tar.gz | |
Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR. It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.
In this patch, I keep these reserved bits when write CPSR back to
hardware.
gdb:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
bits 20 to 23.
gdb/gdbserver:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
23.
| -rw-r--r-- | gdb/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/aarch32-linux-nat.c | 11 | ||||
| -rw-r--r-- | gdb/gdbserver/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/gdbserver/linux-aarch32-low.c | 4 |
4 files changed, 23 insertions, 2 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ef18a19a878..b7b9e542628 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2016-09-21 Yao Qi <yao.qi@linaro.org> + + * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep + bits 20 to 23. + 2016-09-20 Tom Tromey <tom@tromey.com> * python/py-value.c (convert_value_from_python): Make PyInt_Check diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c index 72bf644a3ed..2df672df6c9 100644 --- a/gdb/aarch32-linux-nat.c +++ b/gdb/aarch32-linux-nat.c @@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs, if (arm_apcs_32 && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM)) - regcache_raw_collect (regcache, ARM_PS_REGNUM, - ®s[ARM_CPSR_GREGNUM]); + { + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; + + regcache_raw_collect (regcache, ARM_PS_REGNUM, + ®s[ARM_CPSR_GREGNUM]); + /* Keep reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff) + | (cpsr & 0x00f00000)); + } } /* Supply VFP registers contents, stored in REGS, to REGCACHE. diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index c97c7779784..c1f1dff6c27 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,3 +1,8 @@ +2016-09-21 Yao Qi <yao.qi@linaro.org> + + * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to + 23. + 2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com> * server.c (start_inferior): Call target_mourn_inferior instead of diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c index e6971d5e537..463bce65172 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -62,11 +62,15 @@ arm_fill_gregset (struct regcache *regcache, void *buf) { int i; uint32_t *regs = (uint32_t *) buf; + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) collect_register (regcache, i, ®s[i]); collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + /* Keep reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff) + | (cpsr & 0x00f00000)); } /* Supply GP registers contents, stored in BUF, to REGCACHE. */ |