diff options
| author | Alan Modra <amodra@gmail.com> | 2017-02-16 15:13:56 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2017-02-16 22:39:51 +1030 |
| commit | a48cda7f860584f98825ee6715b0da2adf65bb1a (patch) | |
| tree | c206eba4e6b499ae21bd047476e985d0f007365f | |
| parent | 905712060597d0c7a13ffccbca40330c7ad3e3a8 (diff) | |
| download | binutils-gdb-a48cda7f860584f98825ee6715b0da2adf65bb1a.tar.gz | |
Fix more powerpc testsuite source errors
* testsuite/ld-powerpc/vxworks1-lib.s: Correct addi to addic.
* testsuite/ld-powerpc/vxworks1-lib.dd: Adjust to suit.
| -rw-r--r-- | ld/ChangeLog | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/vxworks1-lib.dd | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/vxworks1-lib.s | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index f875a8b5143..f0b0b0ed9e9 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,8 @@ +2017-02-16 Alan Modra <amodra@gmail.com> + + * testsuite/ld-powerpc/vxworks1-lib.s: Correct addi to addic. + * testsuite/ld-powerpc/vxworks1-lib.dd: Adjust to suit. + 2017-02-15 H.J. Lu <hongjiu.lu@intel.com> PR ld/21168 diff --git a/ld/testsuite/ld-powerpc/vxworks1-lib.dd b/ld/testsuite/ld-powerpc/vxworks1-lib.dd index 1c1861eb0ac..23440ebd7fe 100644 --- a/ld/testsuite/ld-powerpc/vxworks1-lib.dd +++ b/ld/testsuite/ld-powerpc/vxworks1-lib.dd @@ -39,7 +39,7 @@ Disassembly of section \.text: 80c14: 83 de 00 00 lwz r30,0\(r30\) 80c18: 80 3e 00 14 lwz r1,20\(r30\) 80c1c: 80 01 00 00 lwz r0,0\(r1\) - 80c20: 38 00 00 01 li r0,1 + 80c20: 30 00 00 01 addic r0,r0,1 80c24: 90 01 00 00 stw r0,0\(r1\) 80c28: 48 00 00 1d bl 80c44 <slocal> 80c2c: 4b ff fc 15 bl 80840 <_PROCEDURE_LINKAGE_TABLE_\+0x40> diff --git a/ld/testsuite/ld-powerpc/vxworks1-lib.s b/ld/testsuite/ld-powerpc/vxworks1-lib.s index 9dfcb0fe364..99ec4722b77 100644 --- a/ld/testsuite/ld-powerpc/vxworks1-lib.s +++ b/ld/testsuite/ld-powerpc/vxworks1-lib.s @@ -10,7 +10,7 @@ foo: lwz r30,__GOTT_INDEX__(r30) lwz r1,x@got(r30) lwz r0,0(r1) - addi r0,r0,1 + addic r0,r0,1 stw r0,0(r1) bl slocal bl sglobal@plt |