This commit was manufactured by cvs2svn to create tag 'csl-arm-2004-q1a'.csl-arm-2004-q1a

Sprout from binutils-2_15-branch 2004-03-22 04:06:07 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-'
Cherrypick from binutils-2_15-branch 2004-04-08 14:52:45 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    gas/testsuite/gas/dlx/lohi.d
    gas/testsuite/gas/dlx/lohi.s
    gas/testsuite/gas/sh/renesas-1.d
    gas/testsuite/gas/sh/renesas-1.s
    ld/emultempl/irix.em
Cherrypick from binutils-2_15-branch 2004-02-20 15:31:11 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    ld/testsuite/ld-scripts/align.s
    ld/testsuite/ld-scripts/align.t
Cherrypick from binutils-2_15-branch 2004-02-23 10:10:03 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    ld/testsuite/ld-scripts/provide-2.t
    ld/testsuite/ld-scripts/provide-3.t
Cherrypick from binutils-2_15-branch 2004-03-18 00:49:24 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    gas/testsuite/gas/cfi/cfi-sh-1.d
    gas/testsuite/gas/cfi/cfi-sh-1.s
Cherrypick from binutils-2_15-branch 2004-03-21 23:47:55 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    gas/testsuite/gas/cris/mulbug-err-1.s
    gas/testsuite/gas/cris/rd-mulbug-1.d
Cherrypick from binutils-2_15-branch 2004-02-19 14:08:32 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'binutils-':
    ld/testsuite/ld-scripts/data.exp
Cherrypick from master 2004-05-04 00:00:07 UTC Alan Modra <amodra@gmail.com> 'daily update':
    ChangeLog
    MAINTAINERS
    Makefile.def
    Makefile.in
    Makefile.tpl
    bfd/ChangeLog
    bfd/Makefile.am
    bfd/Makefile.in
    bfd/aclocal.m4
    bfd/aix386-core.c
    bfd/aout-adobe.c
    bfd/aout-target.h
    bfd/aout-tic30.c
    bfd/archive.c
    bfd/archures.c
    bfd/bfd-in.h
    bfd/bfd-in2.h
    bfd/bfd.c
    bfd/bfdio.c
    bfd/binary.c
    bfd/bout.c
    bfd/cache.c
    bfd/coff-alpha.c
    bfd/coff-i386.c
    bfd/coff-mips.c
    bfd/coff-rs6000.c
    bfd/coff-tic54x.c
    bfd/coff64-rs6000.c
    bfd/coffcode.h
    bfd/config.bfd
    bfd/config.in
    bfd/configure
    bfd/configure.in
    bfd/cpu-cr16c.c
    bfd/cpu-frv.c
    bfd/cpu-m68k.c
    bfd/cpu-sh.c
    bfd/doc/ChangeLog
    bfd/doc/Makefile.in
    bfd/doc/bfdint.texi
    bfd/dwarf2.c
    bfd/ecoff.c
    bfd/ecofflink.c
    bfd/ecoffswap.h
    bfd/elf-bfd.h
    bfd/elf-eh-frame.c
    bfd/elf-hppa.h
    bfd/elf-m10200.c
    bfd/elf-m10300.c
    bfd/elf.c
    bfd/elf32-arm.h
    bfd/elf32-avr.c
    bfd/elf32-cr16c.c
    bfd/elf32-cris.c
    bfd/elf32-d10v.c
    bfd/elf32-dlx.c
    bfd/elf32-fr30.c
    bfd/elf32-frv.c
    bfd/elf32-gen.c
    bfd/elf32-h8300.c
    bfd/elf32-hppa.c
    bfd/elf32-i370.c
    bfd/elf32-i386.c
    bfd/elf32-i860.c
    bfd/elf32-ip2k.c
    bfd/elf32-iq2000.c
    bfd/elf32-m32r.c
    bfd/elf32-m68hc1x.c
    bfd/elf32-m68hc1x.h
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    bfd/elf32-mcore.c
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    bfd/elf32-msp430.c
    bfd/elf32-openrisc.c
    bfd/elf32-ppc.c
    bfd/elf32-s390.c
    bfd/elf32-sh.c
    bfd/elf32-sh64.c
    bfd/elf32-sparc.c
    bfd/elf32-v850.c
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    bfd/elf32-xtensa.c
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    bfd/elfarm-nabi.c
    bfd/elfcode.h
    bfd/elflink.c
    bfd/elfxx-ia64.c
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    bfd/elfxx-target.h
    bfd/hppabsd-core.c
    bfd/hpux-core.c
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    bfd/ieee.c
    bfd/ihex.c
    bfd/irix-core.c
    bfd/libaout.h
    bfd/libbfd-in.h
    bfd/libbfd.c
    bfd/libbfd.h
    bfd/libecoff.h
    bfd/linker.c
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    bfd/mmo.c
    bfd/netbsd-core.c
    bfd/nlm-target.h
    bfd/oasys.c
    bfd/opncls.c
    bfd/osf-core.c
    bfd/pdp11.c
    bfd/pe-i386.c
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    bfd/po/SRC-POTFILES.in
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    bfd/stabs.c
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    bfd/trad-core.c
    bfd/versados.c
    bfd/version.h
    bfd/vms.c
    bfd/xsym.c
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    binutils/MAINTAINERS
    binutils/Makefile.am
    binutils/Makefile.in
    binutils/aclocal.m4
    binutils/ar.c
    binutils/arsup.c
    binutils/config.in
    binutils/configure
    binutils/deflex.l
    binutils/defparse.y
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    binutils/objdump.c
    binutils/po/binutils.pot
    binutils/ranlib.sh
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    binutils/strings.c
    binutils/testsuite/ChangeLog
    binutils/testsuite/binutils-all/ar.exp
    binutils/testsuite/binutils-all/objcopy.exp
    binutils/testsuite/binutils-all/readelf.ss-mips
    config.guess
    config.sub
    config/ChangeLog
    config/accross.m4
    config/acx.m4
    configure
    configure.in
    cpu/ChangeLog
    cpu/frv.cpu
    cpu/frv.opc
    cpu/m32r.cpu
    cpu/m32r.opc
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    cpu/sh64-media.cpu
    gas/ChangeLog
    gas/Makefile.am
    gas/Makefile.in
    gas/NEWS
    gas/aclocal.m4
    gas/config.in
    gas/config/m68k-parse.h
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    gas/config/tc-sh.h
    gas/config/tc-xtensa.c
    gas/configure
    gas/configure.in
    gas/doc/Makefile.in
    gas/doc/as.texinfo
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    gas/dwarf2dbg.c
    gas/ecoff.c
    gas/expr.c
    gas/po/gas.pot
    gas/read.c
    gas/stabs.c
    gas/testsuite/ChangeLog
    gas/testsuite/gas/alpha/elf-reloc-8.d
    gas/testsuite/gas/arm/arm.exp
    gas/testsuite/gas/arm/maverick.c
    gas/testsuite/gas/arm/maverick.d
    gas/testsuite/gas/arm/maverick.s
    gas/testsuite/gas/arm/reg-alias.d
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    gas/testsuite/gas/cfi/cfi-alpha-3.d
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    gas/testsuite/gas/cfi/cfi-common-3.d
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    gas/testsuite/gas/cfi/cfi-m68k.d
    gas/testsuite/gas/cfi/cfi-s390x-1.d
    gas/testsuite/gas/cfi/cfi-sparc64-1.d
    gas/testsuite/gas/cfi/cfi-x86_64.d
    gas/testsuite/gas/cfi/cfi.exp
    gas/testsuite/gas/cris/regreg.d
    gas/testsuite/gas/dlx/alltests.exp
    gas/testsuite/gas/dlx/itype.d
    gas/testsuite/gas/dlx/lhi.d
    gas/testsuite/gas/elf/elf.exp
    gas/testsuite/gas/elf/group0.s
    gas/testsuite/gas/elf/group0a.d
    gas/testsuite/gas/elf/group0b.d
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    gas/testsuite/gas/elf/group1a.d
    gas/testsuite/gas/elf/group1b.d
    gas/testsuite/gas/elf/section2.e-mips
    gas/testsuite/gas/elf/symver.d
    gas/testsuite/gas/frv/allinsn.d
    gas/testsuite/gas/frv/allinsn.exp
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    gas/testsuite/gas/frv/fr450-spr.d
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    gas/testsuite/gas/i386/i386.exp
    gas/testsuite/gas/i386/katmai.d
    gas/testsuite/gas/i386/padlock.d
    gas/testsuite/gas/i386/padlock.s
    gas/testsuite/gas/i386/secrel.d
    gas/testsuite/gas/i386/secrel.s
    gas/testsuite/gas/i860/dir-intel03-err.l
    gas/testsuite/gas/m32r/m32r.exp
    gas/testsuite/gas/m32r/m32r2.exp
    gas/testsuite/gas/m32r/parallel-2.d
    gas/testsuite/gas/m32r/parallel-2.s
    gas/testsuite/gas/m32r/seth.d
    gas/testsuite/gas/m32r/seth.s
    gas/testsuite/gas/m68hc11/m68hc11.exp
    gas/testsuite/gas/m68k/all.exp
    gas/testsuite/gas/m68k/mcf-emac.d
    gas/testsuite/gas/m68k/mcf-emac.s
    gas/testsuite/gas/m68k/mcf-mac.d
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    gas/testsuite/gas/macros/macros.exp
    gas/testsuite/gas/mips/lb-svr4pic-ilocks.d
    gas/testsuite/gas/mips/lb-xgot-ilocks.d
    gas/testsuite/gas/mips/ld-pic.s
    gas/testsuite/gas/mips/lifloat.s
    gas/testsuite/gas/mips/mips-abi32-pic.d
    gas/testsuite/gas/mips/mips-abi32-pic2.d
    gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
    gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
    gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
    gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
    gas/testsuite/gas/mips/mips.exp
    gas/testsuite/gas/mips/mips16-e.d
    gas/testsuite/gas/mips/mips16-f.d
    gas/testsuite/gas/mips/mipsel16-e.d
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    gas/testsuite/gas/mips/relax-swap1-mips2.d
    gas/testsuite/gas/mips/vr4122.d
    gas/testsuite/gas/mips/vr4122.s
    gas/testsuite/gas/ppc/altivec.d
    gas/testsuite/gas/ppc/altivec_xcoff.d
    gas/testsuite/gas/ppc/altivec_xcoff64.d
    gas/testsuite/gas/ppc/astest.d
    gas/testsuite/gas/ppc/astest2.d
    gas/testsuite/gas/ppc/astest2_64.d
    gas/testsuite/gas/ppc/astest64.d
    gas/testsuite/gas/ppc/booke.d
    gas/testsuite/gas/ppc/booke_xcoff.d
    gas/testsuite/gas/ppc/booke_xcoff64.d
    gas/testsuite/gas/ppc/e500.d
    gas/testsuite/gas/ppc/power4.d
    gas/testsuite/gas/ppc/power4.s
    gas/testsuite/gas/ppc/test1elf32.d
    gas/testsuite/gas/ppc/test1elf64.d
    gas/testsuite/gas/ppc/test1xcoff32.d
    gas/testsuite/gas/sh/basic.exp
    gas/testsuite/gas/sh/pcrel2.d
    gas/testsuite/gas/sh/sh64/err-dsp.s
    gas/testsuite/gas/sh/tlsd.d
    gas/testsuite/gas/sh/tlsnopic.d
    gas/testsuite/gas/sh/tlspic.d
    gas/testsuite/gas/symver/symver0.d
    gas/testsuite/gas/symver/symver1.d
    gas/testsuite/lib/gas-defs.exp
    gprof/ChangeLog
    gprof/Makefile.am
    gprof/Makefile.in
    gprof/gconfig.in
    gprof/po/gprof.pot
    gprof/po/sv.po
    include/ChangeLog
    include/bfdlink.h
    include/coff/ChangeLog
    include/coff/ecoff.h
    include/coff/internal.h
    include/coff/mips.h
    include/dyn-string.h
    include/elf/ChangeLog
    include/elf/arm.h
    include/elf/common.h
    include/elf/cr16c.h
    include/elf/frv.h
    include/elf/mips.h
    include/elf/sh.h
    include/hashtab.h
    include/opcode/ChangeLog
    include/opcode/i386.h
    include/opcode/m68k.h
    include/opcode/ppc.h
    include/splay-tree.h
    install-sh
    ld/ChangeLog
    ld/ChangeLog-0203
    ld/Makefile.am
    ld/Makefile.in
    ld/NEWS
    ld/config.in
    ld/configure.host
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    ld/emulparams/elf32bmip.sh
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    ld/emulparams/elf64bmip.sh
    ld/emulparams/mipsidt.sh
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    ld/emultempl/armelf.em
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    ld/ldlang.c
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    ld/ldlex.l
    ld/ldmain.c
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    ld/lexsup.c
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    ld/testsuite/ld-elf/merge.d
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    ld/testsuite/ld-elfweak/size_foo.c
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    ld/testsuite/ld-powerpc/tlstocso.d
    ld/testsuite/ld-scripts/align.exp
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    ld/testsuite/ld-scripts/data.d
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    libiberty/ChangeLog
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    mkinstalldirs
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    opcodes/aclocal.m4
    opcodes/config.in
    opcodes/configure
    opcodes/frv-asm.c
    opcodes/frv-desc.c
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    opcodes/po/POTFILES.in
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Delete:
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    bfd/mpw-config.in
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    binutils/mac-binutils.r
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    gas/mac-as.r
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    gas/testsuite/gas/mips/empic2.s
    gas/testsuite/gas/mips/empic3_e.d
    gas/testsuite/gas/mips/empic3_e.s
    gas/testsuite/gas/mips/empic3_g1.d
    gas/testsuite/gas/mips/empic3_g1.s
    gas/testsuite/gas/mips/empic3_g2.d
    gas/testsuite/gas/mips/empic3_g2.s
    gas/testsuite/gas/mips/jal-empic-elf-2.d
    gas/testsuite/gas/mips/jal-empic-elf-2.s
    gas/testsuite/gas/mips/jal-empic-elf-3.d
    gas/testsuite/gas/mips/jal-empic-elf-3.s
    gas/testsuite/gas/mips/jal-empic-elf.d
    gas/testsuite/gas/mips/jal-empic.d
    gas/testsuite/gas/mips/la-empic.d
    gas/testsuite/gas/mips/la-empic.s
    gas/testsuite/gas/mips/lb-empic.d
    gas/testsuite/gas/mips/ld-empic.d
    gas/testsuite/gas/mips/lif-empic.d
    gas/testsuite/gas/mips/telempic.d
    gas/testsuite/gas/mips/tempic.d
    gas/testsuite/gas/mips/ulh-empic.d
    include/mpw/ChangeLog
    include/mpw/README
    include/mpw/dir.h
    include/mpw/dirent.h
    include/mpw/fcntl.h
    include/mpw/grp.h
    include/mpw/mpw.h
    include/mpw/pwd.h
    include/mpw/spin.h
    include/mpw/stat.h
    include/mpw/sys/file.h
    include/mpw/sys/param.h
    include/mpw/sys/resource.h
    include/mpw/sys/stat.h
    include/mpw/sys/time.h
    include/mpw/sys/types.h
    include/mpw/utime.h
    include/mpw/varargs.h
    ld/emultempl/mipself.em
    ld/mac-ld.r
    ld/mpw-config.in
    ld/mpw-make.sed
    ld/testsuite/ld-empic/empic.exp
    ld/testsuite/ld-empic/relax.t
    ld/testsuite/ld-empic/relax1.c
    ld/testsuite/ld-empic/relax2.c
    ld/testsuite/ld-empic/relax3.c
    ld/testsuite/ld-empic/relax4.c
    ld/testsuite/ld-empic/run.c
    ld/testsuite/ld-empic/runtest1.c
    ld/testsuite/ld-empic/runtest2.c
    ld/testsuite/ld-empic/runtesti.s
    ld/testsuite/ld-frv/fdpic-pie-8-fail.d
    ld/testsuite/ld-mips-elf/empic1-ln.d
    ld/testsuite/ld-mips-elf/empic1-lp.d
    ld/testsuite/ld-mips-elf/empic1-mn.d
    ld/testsuite/ld-mips-elf/empic1-mp.d
    ld/testsuite/ld-mips-elf/empic1-ref.s
    ld/testsuite/ld-mips-elf/empic1-sn.d
    ld/testsuite/ld-mips-elf/empic1-sp.d
    ld/testsuite/ld-mips-elf/empic1-space.s
    ld/testsuite/ld-mips-elf/empic1-tgt.s
    ld/testsuite/ld-mips-elf/empic2-fwd-0.d
    ld/testsuite/ld-mips-elf/empic2-fwd-1.d
    ld/testsuite/ld-mips-elf/empic2-fwd-tgt.s
    ld/testsuite/ld-mips-elf/empic2-ref.s
    ld/testsuite/ld-mips-elf/empic2-rev-0.d
    ld/testsuite/ld-mips-elf/empic2-rev-1.d
    ld/testsuite/ld-mips-elf/empic2-rev-tgt.s
    ld/testsuite/ld-mips-elf/empic2-space.s
    ld/testsuite/ld-mips-elf/emrelocs-eb.d
    ld/testsuite/ld-mips-elf/emrelocs-el.d
    ld/testsuite/ld-mips-elf/emrelocs.ld
    ld/testsuite/ld-mips-elf/emrelocs1.s
    ld/testsuite/ld-mips-elf/emrelocs2.s
    ld/testsuite/ld-mips-elf/reloc-3-r.d
    ld/testsuite/ld-mips-elf/reloc-3-srec.d
    ld/testsuite/ld-mips-elf/reloc-3.ld
    ld/testsuite/ld-mips-elf/reloc-3a.s
    ld/testsuite/ld-mips-elf/reloc-3b.s
    libiberty/acconfig.h
    mpw-README
    mpw-build.in
    mpw-config.in
    mpw-configure
    mpw-install
    opcodes/mpw-config.in
    opcodes/mpw-make.sed

25 files changed, 1125 insertions, 1020 deletions

diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h
index c82e69fc65a..3b98b8a065c 100644
--- a/gas/config/m68k-parse.h
+++ b/gas/config/m68k-parse.h
@@ -1,6 +1,6 @@
 /* m68k-parse.h -- header file for m68k assembler
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
-   2003 Free Software Foundation, Inc.
+   2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -84,7 +84,12 @@ enum m68k_register
   ZPC,				/* Hack for Program space, but 0 addressing */
   SR,				/* Status Reg */
   CCR,				/* Condition code Reg */
-  ACC,				/* Accumulator Reg */
+  ACC,				/* Accumulator Reg0 (EMAC or ACC on MAC).  */
+  ACC1,				/* Accumulator Reg 1 (EMAC).  */
+  ACC2,				/* Accumulator Reg 2 (EMAC).  */
+  ACC3,				/* Accumulator Reg 3 (EMAC).  */
+  ACCEXT01,			/* Accumulator extension 0&1 (EMAC).  */
+  ACCEXT23,			/* Accumulator extension 2&3 (EMAC).  */
   MACSR,			/* MAC Status Reg */
   MASK,				/* Modulus Reg */
 
@@ -295,6 +300,8 @@ enum m68k_operand_type
   BASE,
   POST,
   PRE,
+  LSH,  /* MAC/EMAC scalefactor '<<'.  */
+  RSH,  /* MAC/EMAC scalefactor '>>'.  */
   REGLST
 };
 
@@ -322,6 +329,9 @@ struct m68k_op
 
   /* The outer displacement.  */
   struct m68k_exp odisp;
+
+  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
+  int trailing_ampersand;
 };
 
 #endif /* ! defined (M68K_PARSE_H) */
diff --git a/gas/config/m68k-parse.y b/gas/config/m68k-parse.y
index 813bfaad2c1..c56ad23d647 100644
--- a/gas/config/m68k-parse.y
+++ b/gas/config/m68k-parse.y
@@ -98,6 +98,7 @@ static struct m68k_op *op;
   struct m68k_exp exp;
   unsigned long mask;
   int onereg;
+  int trailing_ampersand;
 }
 
 %token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
@@ -109,6 +110,7 @@ static struct m68k_op *op;
 %type <exp> optcexpr optexprc
 %type <mask> reglist ireglist reglistpair
 %type <onereg> reglistreg
+%type <trailing_ampersand> optional_ampersand
 
 %%
 
@@ -116,14 +118,35 @@ static struct m68k_op *op;
 
 operand:
 	  generic_operand
-	| motorola_operand
+	| motorola_operand optional_ampersand
+		{
+		  op->trailing_ampersand = $2;
+		}
 	| mit_operand
 	;
 
+/* A trailing ampersand(for MAC/EMAC mask addressing).  */
+optional_ampersand:
+	/* empty */
+		{ $$ = 0; }
+	| '&'
+		{ $$ = 1; }
+	;
+
 /* A generic operand.  */
 
 generic_operand:
-	  DR
+	  '<' '<'
+		{
+		  op->mode = LSH;
+		}
+
+	| '>' '>'
+		{
+		  op->mode = RSH;
+		}
+
+	| DR
 		{
 		  op->mode = DREG;
 		  op->reg = $1;
@@ -757,12 +780,14 @@ yylex ()
     case '/':
     case '[':
     case ']':
+    case '<':
+    case '>':
       return *str++;
     case '+':
       /* It so happens that a '+' can only appear at the end of an
-         operand.  If it appears anywhere else, it must be a unary
-         plus on an expression.  */
-      if (str[1] == '\0')
+	 operand, or if it is trailed by an '&'(see mac load insn).
+	 If it appears anywhere else, it must be a unary.  */
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       break;
     case '-':
diff --git a/gas/config/obj-aout.c b/gas/config/obj-aout.c
index 6e5fd29191a..74e52a5f12d 100644
--- a/gas/config/obj-aout.c
+++ b/gas/config/obj-aout.c
@@ -1,6 +1,6 @@
 /* a.out object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
-   2001, 2002 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004 Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
 
@@ -419,17 +419,9 @@ obj_aout_type (ignore)
 	{
 	  ++input_line_pointer;
 	  if (strncmp (input_line_pointer, "object", 6) == 0)
-#ifdef BFD_ASSEMBLER
-	    aout_symbol (symbol_get_bfdsym (sym))->other = 1;
-#else
-	  S_SET_OTHER (sym, 1);
-#endif
+	    S_SET_OTHER (sym, 1);
 	  else if (strncmp (input_line_pointer, "function", 8) == 0)
-#ifdef BFD_ASSEMBLER
-	    aout_symbol (symbol_get_bfdsym (sym))->other = 2;
-#else
-	  S_SET_OTHER (sym, 2);
-#endif
+	    S_SET_OTHER (sym, 2);
 	}
     }
 
diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index 01ba0962442..f970110f957 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -469,6 +469,18 @@ struct section_stack
 
 static struct section_stack *section_stack;
 
+static bfd_boolean
+get_section (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
+{
+  const char *gname = inf;
+  const char *group_name = elf_group_name (sec);
+  
+  return (group_name == gname
+	  || (group_name != NULL
+	      && gname != NULL
+	      && strcmp (group_name, gname) == 0));
+}
+
 /* Handle the .section pseudo-op.  This code supports two different
    syntaxes.
 
@@ -520,8 +532,16 @@ obj_elf_change_section (const char *name,
   previous_section = now_seg;
   previous_subsection = now_subseg;
 
-  old_sec = bfd_get_section_by_name (stdoutput, name);
-  sec = subseg_new (name, 0);
+  old_sec = bfd_get_section_by_name_if (stdoutput, name, get_section,
+					(void *) group_name);
+  if (old_sec)
+    {
+      sec = old_sec;
+      subseg_set (sec, 0);
+    }
+  else
+    sec = subseg_force_new (name, 0);
+
   ssect = _bfd_elf_get_sec_type_attr (stdoutput, name);
 
   if (ssect != NULL)
@@ -580,10 +600,15 @@ obj_elf_change_section (const char *name,
 		       || strcmp (name, ".strtab") == 0
 		       || strcmp (name, ".symtab") == 0))
 	    override = TRUE;
+	  /* .note.GNU-stack can have SHF_EXECINSTR.  */
+	  else if (attr == SHF_EXECINSTR
+		   && strcmp (name, ".note.GNU-stack") == 0)
+	    override = TRUE;
 	  else
 	    {
-	      as_warn (_("setting incorrect section attributes for %s"),
-		       name);
+	      if (group_name == NULL)
+		as_warn (_("setting incorrect section attributes for %s"),
+			 name);
 	      override = TRUE;
 	    }
 	}
@@ -609,6 +634,9 @@ obj_elf_change_section (const char *name,
   flags = md_elf_section_flags (flags, attr, type);
 #endif
 
+  if (linkonce)
+    flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
+
   if (old_sec == NULL)
     {
       symbolS *secsym;
@@ -617,8 +645,6 @@ obj_elf_change_section (const char *name,
       if (type == SHT_NOBITS)
 	seg_info (sec)->bss = 1;
 
-      if (linkonce)
-	flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
       bfd_set_section_flags (stdoutput, sec, flags);
       if (flags & SEC_MERGE)
 	sec->entsize = entsize;
@@ -644,9 +670,6 @@ obj_elf_change_section (const char *name,
 	as_warn (_("ignoring changed section attributes for %s"), name);
       if ((flags & SEC_MERGE) && old_sec->entsize != (unsigned) entsize)
 	as_warn (_("ignoring changed section entity size for %s"), name);
-      if ((attr & SHF_GROUP) != 0
-	  && strcmp (elf_group_name (old_sec), group_name) != 0)
-	as_warn (_("ignoring new section group for %s"), name);
     }
 
 #ifdef md_elf_section_change_hook
@@ -787,7 +810,7 @@ obj_elf_section_name (void)
 	end++;
       if (end == input_line_pointer)
 	{
-	  as_warn (_("missing name"));
+	  as_bad (_("missing name"));
 	  ignore_rest_of_line ();
 	  return NULL;
 	}
@@ -938,7 +961,7 @@ obj_elf_section (int push)
 	      SKIP_WHITESPACE ();
 	      if (*input_line_pointer != '#')
 		{
-		  as_warn (_("character following name is not '#'"));
+		  as_bad (_("character following name is not '#'"));
 		  ignore_rest_of_line ();
 		  return;
 		}
diff --git a/gas/config/obj-som.c b/gas/config/obj-som.c
index 454042a4f41..a736c9658ea 100644
--- a/gas/config/obj-som.c
+++ b/gas/config/obj-som.c
@@ -248,7 +248,7 @@ obj_som_init_stab_section (seg)
      (just created above).  Also set some attributes which BFD does
      not understand.  In particular, access bits, sort keys, and load
      quadrant.  */
-  obj_set_subsection_attributes (seg, space, 0x1f, 73, 0);
+  obj_set_subsection_attributes (seg, space, 0x1f, 73, 0, 0, 0, 0);
   bfd_set_section_alignment (stdoutput, seg, 2);
 
   /* Make some space for the first special stab entry and zero the memory.
@@ -271,7 +271,7 @@ obj_som_init_stab_section (seg)
      not understand.  In particular, access bits, sort keys, and load
      quadrant.  */
   seg = bfd_get_section_by_name (stdoutput, "$GDB_STRINGS$");
-  obj_set_subsection_attributes (seg, space, 0x1f, 72, 0);
+  obj_set_subsection_attributes (seg, space, 0x1f, 72, 0, 0, 0, 0);
   bfd_set_section_alignment (stdoutput, seg, 2);
 
   subseg_set (saved_seg, saved_subseg);
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index b99fc0b8f72..60cfa34652a 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -905,11 +905,6 @@ arc_extoper (opertype)
   name = input_line_pointer;
   c = get_symbol_end ();
   name = xstrdup (name);
-  if (NULL == name)
-    {
-      ignore_rest_of_line ();
-      return;
-    }
 
   p = name;
   while (*p)
@@ -1153,11 +1148,6 @@ arc_extinst (ignore)
   name = input_line_pointer;
   c = get_symbol_end ();
   name = xstrdup (name);
-  if (NULL == name)
-    {
-      ignore_rest_of_line ();
-      return;
-    }
   strcpy (syntax, name);
   name_len = strlen (name);
 
@@ -1305,18 +1295,7 @@ arc_extinst (ignore)
   strcat (syntax, "%S%L");
 
   ext_op = (struct arc_opcode *) xmalloc (sizeof (struct arc_opcode));
-  if (NULL == ext_op)
-    {
-      ignore_rest_of_line ();
-      return;
-    }
-
   ext_op->syntax = xstrdup (syntax);
-  if (NULL == ext_op->syntax)
-    {
-      ignore_rest_of_line ();
-      return;
-    }
 
   ext_op->mask  = I (-1) | ((0x3 == opcode) ? C (-1) : 0);
   ext_op->value = I (opcode) | ((0x3 == opcode) ? C (subopcode) : 0);
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 69b2c21998a..3f21c84a6ce 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1,5 +1,5 @@
 /* tc-arm.c -- Assemble for the ARM
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -191,6 +191,9 @@ static int march_cpu_opt = -1;
 static int march_fpu_opt = -1;
 static int mfpu_opt = -1;
 static int mfloat_abi_opt = -1;
+#ifdef OBJ_ELF
+static int meabi_flags = EF_ARM_EABI_UNKNOWN;
+#endif
 
 /* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  */
@@ -2551,6 +2554,9 @@ static int arm_parse_cpu PARAMS ((char *));
 static int arm_parse_arch PARAMS ((char *));
 static int arm_parse_fpu PARAMS ((char *));
 static int arm_parse_float_abi PARAMS ((char *));
+#ifdef OBJ_ELF
+static int arm_parse_eabi PARAMS ((char *));
+#endif
 #if 0 /* Suppressed - for now.  */
 #if defined OBJ_COFF || defined OBJ_ELF
 static void arm_add_note PARAMS ((const char *, const char *, unsigned int));
@@ -2823,13 +2829,6 @@ validate_offset_imm (val, hwse)
 
 
 #ifdef OBJ_ELF
-enum mstate
-{
-  MAP_DATA,
-  MAP_ARM,
-  MAP_THUMB
-};
-
 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
    (This text is taken from version B-02 of the spec):
 
@@ -2904,10 +2903,11 @@ enum mstate
    the EABI (which is still under development), so they are not
    implemented here.  */
 
+static enum mstate mapstate = MAP_UNDEFINED;
+
 static void
 mapping_state (enum mstate state)
 {
-  static enum mstate mapstate = MAP_DATA;
   symbolS * symbolP;
   const char * symname;
   int type;
@@ -2933,10 +2933,14 @@ mapping_state (enum mstate state)
       symname = "$t";
       type = BSF_FUNCTION;
       break;
+    case MAP_UNDEFINED:
+      return;     
     default:
       abort ();
     }
 
+  seg_info (now_seg)->tc_segment_info_data = state;
+
   symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
   symbol_table_insert (symbolP);
   symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
@@ -2977,16 +2981,7 @@ arm_elf_change_section (void)
   if ((flags & SEC_ALLOC) == 0)
     return;
 
-  if (flags & SEC_CODE)
-    {
-      if (thumb_mode)
-	mapping_state (MAP_THUMB);
-      else
-	mapping_state (MAP_ARM);
-    }
-  else
-    /* This section does not contain code.  Therefore it must contain data.  */
-    mapping_state (MAP_DATA);    
+  mapstate = seg_info (now_seg)->tc_segment_info_data;
 }
 #else
 #define mapping_state(a)
@@ -3109,6 +3104,8 @@ s_ltorg (ignored)
       || pool->next_free_entry == 0)
     return;
 
+  mapping_state (MAP_DATA);
+
   /* Align pool as you have word accesses.
      Only make a frag if we have to.  */
   if (!need_pass_2)
@@ -3598,7 +3595,7 @@ co_proc_number (str)
 	}
       else
 	{
-	  inst.error = _("bad or missing co-processor number");
+	  inst.error = all_reg_maps[REG_TYPE_CP].expected;
 	  return FAIL;
 	}
     }
@@ -3653,7 +3650,7 @@ cp_reg_required_here (str, where)
 
   /* In the few cases where we might be able to accept something else
      this error can be overridden.  */
-  inst.error = _("co-processor register expected");
+  inst.error = all_reg_maps[REG_TYPE_CN].expected;
 
   /* Restore the start point.  */
   *str = start;
@@ -3676,7 +3673,7 @@ fp_reg_required_here (str, where)
 
   /* In the few cases where we might be able to accept something else
      this error can be overridden.  */
-  inst.error = _("floating point register expected");
+  inst.error = all_reg_maps[REG_TYPE_FN].expected;
 
   /* Restore the start point.  */
   *str = start;
@@ -10856,11 +10853,16 @@ mav_parse_offset (str, negative)
   for (offset = 0; *p && ISDIGIT (*p); ++p)
     offset = offset * 10 + *p - '0';
 
-  if (offset > 0xff)
+  if (offset > 0x3fc)
     {
       inst.error = _("offset out of range");
       return 0;
     }
+  if (offset & 0x3)
+    {
+      inst.error = _("offset not a multiple of 4");
+      return 0;
+    }
 
   *str = p;
 
@@ -11437,7 +11439,7 @@ create_register_alias (newname, p)
       char *copy_of_str;
       char *r;
 
-#ifdef IGNORE_OPCODE_CASE
+#ifndef IGNORE_OPCODE_CASE
       newname = original_case_string;
 #endif
       copy_of_str = newname;
@@ -11685,40 +11687,57 @@ md_begin ()
 
   cpu_variant = mcpu_cpu_opt | mfpu_opt;
 
-#if defined OBJ_COFF || defined OBJ_ELF
   {
     unsigned int flags = 0;
 
-    /* Set the flags in the private structure.  */
-    if (uses_apcs_26)      flags |= F_APCS26;
-    if (support_interwork) flags |= F_INTERWORK;
-    if (uses_apcs_float)   flags |= F_APCS_FLOAT;
-    if (pic_code)          flags |= F_PIC;
-    if ((cpu_variant & FPU_ANY) == FPU_NONE
-	 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only.  */
-      {
-	flags |= F_SOFT_FLOAT;
-      }
-    switch (mfloat_abi_opt)
+#if defined OBJ_ELF
+    flags = meabi_flags;
+
+    switch (meabi_flags)
       {
-      case ARM_FLOAT_ABI_SOFT:
-      case ARM_FLOAT_ABI_SOFTFP:
-	flags |= F_SOFT_FLOAT;
+      case EF_ARM_EABI_UNKNOWN:
+#endif
+#if defined OBJ_COFF || defined OBJ_ELF
+	/* Set the flags in the private structure.  */
+	if (uses_apcs_26)      flags |= F_APCS26;
+	if (support_interwork) flags |= F_INTERWORK;
+	if (uses_apcs_float)   flags |= F_APCS_FLOAT;
+	if (pic_code)          flags |= F_PIC;
+	if ((cpu_variant & FPU_ANY) == FPU_NONE
+	     || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only.  */
+	  flags |= F_SOFT_FLOAT;
+
+	switch (mfloat_abi_opt)
+	  {
+	  case ARM_FLOAT_ABI_SOFT:
+	  case ARM_FLOAT_ABI_SOFTFP:
+	    flags |= F_SOFT_FLOAT;
+	    break;
+
+	  case ARM_FLOAT_ABI_HARD:
+	    if (flags & F_SOFT_FLOAT)
+	      as_bad (_("hard-float conflicts with specified fpu"));
+	    break;
+	  }
+
+	/* Using VFP conventions (even if soft-float).  */
+	if (cpu_variant & FPU_VFP_EXT_NONE)
+	  flags |= F_VFP_FLOAT;
+#endif
+#if defined OBJ_ELF
+	if (cpu_variant & FPU_ARCH_MAVERICK)
+	    flags |= EF_ARM_MAVERICK_FLOAT;
 	break;
 
-      case ARM_FLOAT_ABI_HARD:
-	if (flags & F_SOFT_FLOAT)
-	  as_bad (_("hard-float conflicts with specified fpu"));
+      case EF_ARM_EABI_VER3:
+	/* No additional flags to set.  */
 	break;
-      }
-    /* Using VFP conventions (even if soft-float).  */
-    if (cpu_variant & FPU_VFP_EXT_NONE) flags |= F_VFP_FLOAT;
 
-#if defined OBJ_ELF
-    if (cpu_variant & FPU_ARCH_MAVERICK)
-	flags |= EF_ARM_MAVERICK_FLOAT;
+      default:
+	abort ();
+      }
 #endif
-
+#if defined OBJ_COFF || defined OBJ_ELF
     bfd_set_private_flags (stdoutput, flags);
 
     /* We have run out flags in the COFF header to encode the
@@ -11738,8 +11757,8 @@ md_begin ()
 	    bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
 	  }
       }
-  }
 #endif
+  }
 
   /* Record the CPU type as well.  */
   switch (cpu_variant & ARM_CPU_MASK)
@@ -13450,6 +13469,22 @@ static struct arm_float_abi_option_table arm_float_abis[] =
   {NULL, 0}
 };
 
+struct arm_eabi_option_table
+{
+  char *name;
+  unsigned int value;
+};
+
+#ifdef OBJ_ELF
+/* We only know hot to output GNU and ver 3 (AAELF) formats.  */
+static struct arm_eabi_option_table arm_eabis[] =
+{
+  {"gnu",	EF_ARM_EABI_UNKNOWN},
+  {"3",		EF_ARM_EABI_VER3},
+  {NULL, 0}
+};
+#endif
+
 struct arm_long_option_table
 {
   char *option;		/* Substring to match.  */
@@ -13613,6 +13648,24 @@ arm_parse_float_abi (str)
   return 0;
 }
 
+#ifdef OBJ_ELF
+static int
+arm_parse_eabi (str)
+     char * str;
+{
+  struct arm_eabi_option_table *opt;
+
+  for (opt = arm_eabis; opt->name != NULL; opt++)
+    if (strcmp (opt->name, str) == 0)
+      {
+	meabi_flags = opt->value;
+	return 1;
+      }
+  as_bad (_("unknown EABI `%s'\n"), str);
+  return 0;
+}
+#endif
+
 struct arm_long_option_table arm_long_opts[] =
 {
   {"mcpu=", N_("<cpu name>\t  assemble for CPU <cpu name>"),
@@ -13623,6 +13676,10 @@ struct arm_long_option_table arm_long_opts[] =
    arm_parse_fpu, NULL},
   {"mfloat-abi=", N_("<abi>\t  assemble for floating point ABI <abi>"),
    arm_parse_float_abi, NULL},
+#ifdef OBJ_ELF
+  {"meabi=", N_("<ver>\t  assemble for eabi version <ver>"),
+   arm_parse_eabi, NULL},
+#endif
   {NULL, NULL, 0, NULL}
 };
 
@@ -13817,6 +13874,9 @@ arm_cleanup ()
     {
       /* Put it at the end of the relevent section.  */
       subseg_set (pool->section, pool->sub_section);
+#ifdef OBJ_ELF
+      arm_elf_change_section ();
+#endif
       s_ltorg (0);
     }
 }
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index 58396cc565f..4e791a083f4 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -1,5 +1,5 @@
 /* This file is tc-arm.h
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2004
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -47,67 +47,47 @@
 #define LITTLE_ENDIAN 	1234
 #define BIG_ENDIAN 	4321
 
-#if defined OBJ_AOUT
-#if defined TE_RISCIX
-# define TARGET_FORMAT "a.out-riscix"
-#elif defined TE_LINUX
-# define ARM_BI_ENDIAN
-# define TARGET_FORMAT "a.out-arm-linux"
-#elif defined TE_NetBSD
-# define TARGET_FORMAT "a.out-arm-netbsd"
-#else
-# define ARM_BI_ENDIAN
-# define TARGET_FORMAT \
-  (target_big_endian ? "a.out-arm-big" : "a.out-arm-little")
-#endif
-#endif /* OBJ_AOUT */
-
-#ifdef OBJ_AIF
-#define TARGET_FORMAT "aif"
-#endif
-
 struct fix;
 
-#if defined OBJ_COFF || defined OBJ_ELF
+#if defined OBJ_AOUT
+# if defined TE_RISCIX
+#  define TARGET_FORMAT "a.out-riscix"
+# elif defined TE_LINUX
+#  define ARM_BI_ENDIAN
+#  define TARGET_FORMAT "a.out-arm-linux"
+# elif defined TE_NetBSD
+#  define TARGET_FORMAT "a.out-arm-netbsd"
+# else
+#  define ARM_BI_ENDIAN
+#  define TARGET_FORMAT (target_big_endian ? "a.out-arm-big" : "a.out-arm-little")
+# endif
+#elif defined OBJ_AIF
+# define TARGET_FORMAT "aif"
+#elif defined OBJ_COFF
 # define ARM_BI_ENDIAN
-
-# define TC_VALIDATE_FIX(FIX, SEGTYPE, LABEL) arm_validate_fix (FIX)
-  extern void arm_validate_fix PARAMS ((struct fix *));
-#endif
-
-#ifdef OBJ_COFF
 # if defined TE_PE
-#   ifdef TE_EPOC
-#    define TARGET_FORMAT (target_big_endian ? "epoc-pe-arm-big" : "epoc-pe-arm-little")
-#   else
-#    define TARGET_FORMAT (target_big_endian ? "pe-arm-big" : "pe-arm-little")
-#   endif
+#  if defined TE_EPOC
+#   define TARGET_FORMAT (target_big_endian ? "epoc-pe-arm-big" : "epoc-pe-arm-little")
+#  else
+#   define TARGET_FORMAT (target_big_endian ? "pe-arm-big" : "pe-arm-little")
+#  endif
 # else
 #  define TARGET_FORMAT (target_big_endian ? "coff-arm-big" : "coff-arm-little")
 # endif
-#endif
-
-#ifdef OBJ_ELF
-# define TARGET_FORMAT elf32_arm_target_format()
-  extern const char * elf32_arm_target_format PARAMS ((void));
-
-# define md_elf_section_change_hook() arm_elf_change_section
-  extern void arm_elf_change_section (void);
+#elif defined OBJ_ELF
+# define ARM_BI_ENDIAN
+# define TARGET_FORMAT	elf32_arm_target_format ()
 #endif
 
 #define TC_FORCE_RELOCATION(FIX) arm_force_relocation (FIX)
-extern int arm_force_relocation PARAMS ((struct fix *));
 
-#define md_convert_frag(b, s, f) {as_fatal (_("arm convert_frag\n"));}
+#define md_convert_frag(b, s, f) { as_fatal (_("arm convert_frag\n")); }
 
 #define md_cleanup() arm_cleanup ()
- extern void arm_cleanup PARAMS ((void));
 
 #define md_start_line_hook() arm_start_line_hook ()
- extern void arm_start_line_hook PARAMS ((void));
 
 #define tc_frob_label(S) arm_frob_label (S)
- extern void arm_frob_label PARAMS ((symbolS *));
 
 /* We also need to mark assembler created symbols:  */
 #define tc_frob_fake_label(S) arm_frob_label (S)
@@ -119,19 +99,9 @@ extern int arm_force_relocation PARAMS ((struct fix *));
 #define TC_FIX_TYPE PTR
 #define TC_INIT_FIX_DATA(FIX) ((FIX)->tc_fix_data = NULL)
 
-#if defined OBJ_ELF || defined OBJ_COFF
-#define EXTERN_FORCE_RELOC 1
-
-#define tc_fix_adjustable(FIX) arm_fix_adjustable (FIX)
-bfd_boolean arm_fix_adjustable PARAMS ((struct fix *));
-
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
-#define MD_APPLY_SYM_VALUE(FIX) 0
-#endif
-
 /* We need to keep some local information on symbols.  */
 
-#define TC_SYMFIELD_TYPE unsigned int
+#define TC_SYMFIELD_TYPE 	unsigned int
 #define ARM_GET_FLAG(s)   	(*symbol_get_tc (s))
 #define ARM_SET_FLAG(s,v) 	(*symbol_get_tc (s) |= (v))
 #define ARM_RESET_FLAG(s,v) 	(*symbol_get_tc (s) &= ~(v))
@@ -148,23 +118,10 @@ bfd_boolean arm_fix_adjustable PARAMS ((struct fix *));
 #define ARM_SET_INTERWORK(s,t)  ((t) ? ARM_SET_FLAG (s, ARM_FLAG_INTERWORK) : ARM_RESET_FLAG (s, ARM_FLAG_INTERWORK))
 #define THUMB_SET_FUNC(s,t)     ((t) ? ARM_SET_FLAG (s, THUMB_FLAG_FUNC)    : ARM_RESET_FLAG (s, THUMB_FLAG_FUNC))
 
-#define TC_START_LABEL(C,STR) \
-  (c == ':' || (c == '/' && arm_data_in_code ()))
-int arm_data_in_code PARAMS ((void));
-
-#define tc_canonicalize_symbol_name(str) \
- arm_canonicalize_symbol_name (str);
-char * arm_canonicalize_symbol_name PARAMS ((char *));
-
-#define obj_adjust_symtab() arm_adjust_symtab ()
- extern void arm_adjust_symtab PARAMS ((void));
-
-#ifdef OBJ_ELF
-#define obj_frob_symbol(sym, punt)  armelf_frob_symbol ((sym), & (punt))
-void armelf_frob_symbol PARAMS ((symbolS *, int *));
-#endif
-
-#define tc_aout_pre_write_hook(x)	{;}	/* not used */
+#define TC_START_LABEL(C,STR)            (c == ':' || (c == '/' && arm_data_in_code ()))
+#define tc_canonicalize_symbol_name(str) arm_canonicalize_symbol_name (str);
+#define obj_adjust_symtab() 		 arm_adjust_symtab ()
+#define tc_aout_pre_write_hook(x)	 {;}	/* not used */
 
 #define LISTING_HEADER "ARM GAS "
 
@@ -172,9 +129,6 @@ void armelf_frob_symbol PARAMS ((symbolS *, int *));
 
 #define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
 #define LOCAL_LABELS_FB   1
-#ifdef OBJ_ELF
-#define LOCAL_LABEL_PREFIX '.'
-#endif
 
 /* This expression evaluates to true if the relocation is for a local
    object for which we still want to do the relocation at runtime.
@@ -192,29 +146,15 @@ void armelf_frob_symbol PARAMS ((symbolS *, int *));
    || TC_FORCE_RELOCATION (FIX))
 
 #define TC_CONS_FIX_NEW cons_fix_new_arm
- extern void cons_fix_new_arm PARAMS ((fragS *, int, int, expressionS *));
-
-#ifdef OBJ_ELF
-#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
-#else
-#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
-#endif
-
-#ifdef OBJ_ELF
-#define DWARF2_LINE_MIN_INSN_LENGTH 2
-#endif
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE 31
 
 /* For frags in code sections we need to record whether they contain
    ARM code or THUMB code.  This is that if they have to be aligned,
    they can contain the correct type of no-op instruction.  */
-#define TC_FRAG_TYPE	int
+#define TC_FRAG_TYPE		int
 #define TC_FRAG_INIT(fragp)	arm_init_frag (fragp)
-extern void arm_init_frag PARAMS ((struct frag *));
-
-#define HANDLE_ALIGN(fragp) arm_handle_align (fragp)
-extern void arm_handle_align PARAMS ((struct frag *));
+#define HANDLE_ALIGN(fragp)	arm_handle_align (fragp)
 
 #define md_do_align(N, FILL, LEN, MAX, LABEL)					\
   if (FILL == NULL && (N) != 0 && ! need_pass_2 && subseg_text_p (now_seg))	\
@@ -222,4 +162,50 @@ extern void arm_handle_align PARAMS ((struct frag *));
       arm_frag_align_code (N, MAX);						\
       goto LABEL;								\
     }
-extern void arm_frag_align_code PARAMS ((int, int));
+
+#ifdef OBJ_ELF
+# define DWARF2_LINE_MIN_INSN_LENGTH 	2
+# define obj_frob_symbol(sym, punt)	armelf_frob_symbol ((sym), & (punt))
+# define md_elf_section_change_hook()	arm_elf_change_section ()
+# define GLOBAL_OFFSET_TABLE_NAME	"_GLOBAL_OFFSET_TABLE_"
+# define LOCAL_LABEL_PREFIX 		'.'
+# define TC_SEGMENT_INFO_TYPE 		enum mstate
+
+enum mstate
+{
+  MAP_UNDEFINED = 0, /* Must be zero, for seginfo in new sections.  */
+  MAP_DATA,
+  MAP_ARM,
+  MAP_THUMB
+};
+
+#else /* Not OBJ_ELF.  */
+#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
+#endif
+
+#if defined OBJ_ELF || defined OBJ_COFF
+
+# define EXTERN_FORCE_RELOC 			1
+# define tc_fix_adjustable(FIX) 		arm_fix_adjustable (FIX)
+/* Values passed to md_apply_fix3 don't include the symbol value.  */
+# define MD_APPLY_SYM_VALUE(FIX) 		0
+# define TC_VALIDATE_FIX(FIX, SEGTYPE, LABEL)	arm_validate_fix (FIX)
+
+#endif
+
+extern void arm_frag_align_code (int, int);
+extern void arm_validate_fix (struct fix *);
+extern const char * elf32_arm_target_format (void);
+extern void arm_elf_change_section (void);
+extern int arm_force_relocation (struct fix *);
+extern void arm_cleanup (void);
+extern void arm_start_line_hook (void);
+extern void arm_frob_label (symbolS *);
+extern int arm_data_in_code (void);
+extern char * arm_canonicalize_symbol_name (char *);
+extern void arm_adjust_symtab (void);
+extern void armelf_frob_symbol (symbolS *, int *);
+extern void cons_fix_new_arm (fragS *, int, int, expressionS *);
+extern void arm_init_frag (struct frag *);
+extern void arm_handle_align (struct frag *);
+extern bfd_boolean arm_fix_adjustable (struct fix *);
diff --git a/gas/config/tc-dlx.c b/gas/config/tc-dlx.c
index 4b72b564de9..82b4aa249b0 100644
--- a/gas/config/tc-dlx.c
+++ b/gas/config/tc-dlx.c
@@ -1,5 +1,5 @@
 /* tc-ldx.c -- Assemble for the DLX
-   Copyright 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -397,6 +397,18 @@ md_assemble (str)
 			  the_insn.size, & the_insn.exp, the_insn.pcrel,
 			  the_insn.reloc);
 
+      /* Turn off complaints that the addend is
+	 too large for things like foo+100000@ha.  */
+      switch (the_insn.reloc)
+	{
+	case RELOC_DLX_HI16:
+	case RELOC_DLX_LO16:
+	  fixP->fx_no_overflow = 1;
+	  break;
+	default:
+	  break;
+	}
+
       switch (fixP->fx_r_type)
 	{
 	case RELOC_DLX_REL26:
@@ -410,6 +422,7 @@ md_assemble (str)
 	  bitP->fx_bit_add = 0x03FFFFFF;
 	  fixP->fx_bit_fixP = bitP;
 	  break;
+	case RELOC_DLX_LO16:
 	case RELOC_DLX_REL16:
 	  bitP = malloc (sizeof (bit_fixS));
 	  bitP->fx_bit_size = 16;
@@ -955,7 +968,8 @@ machine_ip (str)
 	      continue;
 	    }
 
-	  the_insn.reloc        = (the_insn.HI) ? RELOC_DLX_HI16 : RELOC_DLX_16;
+	  the_insn.reloc        = (the_insn.HI) ? RELOC_DLX_HI16 
+	    : (the_insn.LO ? RELOC_DLX_LO16 : RELOC_DLX_16);
 	  the_insn.reloc_offset = 2;
 	  the_insn.size         = 2;
 	  the_insn.pcrel        = 0;
@@ -1164,6 +1178,7 @@ md_apply_fix3 (fixP, valP, seg)
 
   switch (fixP->fx_r_type)
     {
+    case RELOC_DLX_LO16:
     case RELOC_DLX_REL16:
       if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
 	{
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index 96e630bf298..6c6528bfb8e 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -163,6 +163,7 @@ static FRV_VLIW vliw;
 #endif
 
 static unsigned long frv_mach = bfd_mach_frv;
+static bfd_boolean fr400_audio;
 
 /* Flags to set in the elf header */
 static flagword frv_flags = DEFAULT_FLAGS;
@@ -354,10 +355,24 @@ md_parse_option (c, arg)
 	    frv_mach = bfd_mach_fr550;
 	  }
 
+	else if (strcmp (p, "fr450") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR450;
+	    frv_mach = bfd_mach_fr450;
+	  }
+
+	else if (strcmp (p, "fr405") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR405;
+	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = TRUE;
+	  }
+
 	else if (strcmp (p, "fr400") == 0)
 	  {
 	    cpu_flags = EF_FRV_CPU_FR400;
 	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = FALSE;
 	  }
 
 	else if (strcmp (p, "fr300") == 0)
@@ -446,7 +461,7 @@ md_show_usage (stream)
   fprintf (stream, _("-mpic        Note small position independent code\n"));
   fprintf (stream, _("-mPIC        Note large position independent code\n"));
   fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n"));
-  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr300|frv|simple|tomcat}\n"));
+  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
   fprintf (stream, _("             Record the cpu type\n"));
   fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
   fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
@@ -1042,6 +1057,36 @@ fr550_check_acc_range (FRV_VLIW *vliw, frv_insn *insn)
   return 0; /* all is ok */
 }
 
+/* Return true if the target implements instruction INSN.  */
+
+static bfd_boolean
+target_implements_insn_p (const CGEN_INSN *insn)
+{
+  switch (frv_mach)
+    {
+    default:
+      /* bfd_mach_frv or generic.  */
+      return TRUE;
+
+    case bfd_mach_fr300:
+    case bfd_mach_frvsimple:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_SIMPLE);
+
+    case bfd_mach_fr400:
+      return ((fr400_audio || !CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_AUDIO))
+	      && CGEN_INSN_MACH_HAS_P (insn, MACH_FR400));
+
+    case bfd_mach_fr450:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR450);
+
+    case bfd_mach_fr500:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR500);
+
+    case bfd_mach_fr550:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR550);
+    }
+}
+
 void
 md_assemble (str)
      char * str;
@@ -1125,6 +1170,11 @@ md_assemble (str)
      instructions, don't do vliw checking.  */
   else if (frv_mach != bfd_mach_frv)
     {
+      if (!target_implements_insn_p (insn.insn))
+	{
+	  as_bad (_("Instruction not supported by this architecture"));
+	  return;
+	}
       packing_constraint = frv_vliw_add_insn (& vliw, insn.insn);
       if (frv_mach == bfd_mach_fr550 && ! packing_constraint)
 	packing_constraint = fr550_check_acc_range (& vliw, & insn);
diff --git a/gas/config/tc-generic.c b/gas/config/tc-generic.c
index e69de29bb2d..b9e52f6dec9 100644
--- a/gas/config/tc-generic.c
+++ b/gas/config/tc-generic.c
@@ -0,0 +1,22 @@
+/* This file is tc-generic.c
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* This file is tc-generic.c and is intended to be a template for
+   target cpu specific files.  */
diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c
index 7fbcd0a6e04..72abe1dedb5 100644
--- a/gas/config/tc-hppa.c
+++ b/gas/config/tc-hppa.c
@@ -363,6 +363,9 @@ struct default_subspace_dict
     /* Nonzero if this subspace contains only code.  */
     char code_only;
 
+    /* Nonzero if this is a comdat subspace.  */
+    char comdat;
+
     /* Nonzero if this is a common subspace.  */
     char common;
 
@@ -555,13 +558,13 @@ static sd_chain_struct *create_new_space PARAMS ((char *, int, int,
 						  asection *, int));
 static ssd_chain_struct *create_new_subspace PARAMS ((sd_chain_struct *,
 						      char *, int, int,
-						      int, int, int,
+						      int, int, int, int,
 						      int, int, int, int,
 						      int, asection *));
 static ssd_chain_struct *update_subspace PARAMS ((sd_chain_struct *,
 						  char *, int, int, int,
 						  int, int, int, int,
-						  int, int, int,
+						  int, int, int, int,
 						  asection *));
 static sd_chain_struct *is_defined_space PARAMS ((char *));
 static ssd_chain_struct *is_defined_subspace PARAMS ((char *));
@@ -1117,12 +1120,12 @@ static const struct selector_entry selector_table[] =
 
 static struct default_subspace_dict pa_def_subspaces[] =
 {
-  {"$CODE$", 1, 1, 1, 0, 0, 0, 24, 0x2c, 0, 8, 0, 0, SUBSEG_CODE},
-  {"$DATA$", 1, 1, 0, 0, 0, 0, 24, 0x1f, 1, 8, 1, 1, SUBSEG_DATA},
-  {"$LIT$", 1, 1, 0, 0, 0, 0, 16, 0x2c, 0, 8, 0, 0, SUBSEG_LIT},
-  {"$MILLICODE$", 1, 1, 0, 0, 0, 0, 8, 0x2c, 0, 8, 0, 0, SUBSEG_MILLI},
-  {"$BSS$", 1, 1, 0, 0, 0, 1, 80, 0x1f, 1, 8, 1, 1, SUBSEG_BSS},
-  {NULL, 0, 1, 0, 0, 0, 0, 255, 0x1f, 0, 4, 0, 0, 0}
+  {"$CODE$", 1, 1, 1, 0, 0, 0, 0, 24, 0x2c, 0, 8, 0, 0, SUBSEG_CODE},
+  {"$DATA$", 1, 1, 0, 0, 0, 0, 0, 24, 0x1f, 1, 8, 1, 1, SUBSEG_DATA},
+  {"$LIT$", 1, 1, 0, 0, 0, 0, 0, 16, 0x2c, 0, 8, 0, 0, SUBSEG_LIT},
+  {"$MILLICODE$", 1, 1, 0, 0, 0, 0, 0, 8, 0x2c, 0, 8, 0, 0, SUBSEG_MILLI},
+  {"$BSS$", 1, 1, 0, 0, 0, 0, 1, 80, 0x1f, 1, 8, 1, 1, SUBSEG_BSS},
+  {NULL, 0, 1, 0, 0, 0, 0, 0, 255, 0x1f, 0, 4, 0, 0, 0}
 };
 
 static struct default_space_dict pa_def_spaces[] =
@@ -1399,6 +1402,8 @@ cons_fix_new_hppa (frag, where, size, exp)
   /* Get a base relocation type.  */
   if (is_DP_relative (*exp))
     rel_type = R_HPPA_GOTOFF;
+  else if (is_PC_relative (*exp))
+    rel_type = R_HPPA_PCREL_CALL;
   else if (is_complex (*exp))
     rel_type = R_HPPA_COMPLEX;
   else
@@ -6386,6 +6391,7 @@ pa_comm (unused)
 
   if (symbol)
     {
+      symbol_get_bfdsym (symbol)->flags |= BSF_OBJECT;
       S_SET_VALUE (symbol, size);
       S_SET_SEGMENT (symbol, bfd_und_section_ptr);
       S_SET_EXTERNAL (symbol);
@@ -7451,7 +7457,7 @@ pa_subspace (create_new)
      int create_new;
 {
   char *name, *ss_name, c;
-  char loadable, code_only, common, dup_common, zero, sort;
+  char loadable, code_only, comdat, common, dup_common, zero, sort;
   int i, access, space_index, alignment, quadrant, applicable, flags;
   sd_chain_struct *space;
   ssd_chain_struct *ssd;
@@ -7477,6 +7483,7 @@ pa_subspace (create_new)
       sort = 0;
       access = 0x7f;
       loadable = 1;
+      comdat = 0;
       common = 0;
       dup_common = 0;
       code_only = 0;
@@ -7511,6 +7518,7 @@ pa_subspace (create_new)
 	      if (strcasecmp (pa_def_subspaces[i].name, ss_name) == 0)
 		{
 		  loadable = pa_def_subspaces[i].loadable;
+		  comdat = pa_def_subspaces[i].comdat;
 		  common = pa_def_subspaces[i].common;
 		  dup_common = pa_def_subspaces[i].dup_common;
 		  code_only = pa_def_subspaces[i].code_only;
@@ -7574,6 +7582,11 @@ pa_subspace (create_new)
 		  *input_line_pointer = c;
 		  loadable = 0;
 		}
+	      else if ((strncasecmp (name, "comdat", 6) == 0))
+		{
+		  *input_line_pointer = c;
+		  comdat = 1;
+		}
 	      else if ((strncasecmp (name, "common", 6) == 0))
 		{
 		  *input_line_pointer = c;
@@ -7606,8 +7619,17 @@ pa_subspace (create_new)
 	flags |= (SEC_ALLOC | SEC_LOAD);
       if (code_only)
 	flags |= SEC_CODE;
-      if (common || dup_common)
-	flags |= SEC_IS_COMMON;
+
+      /* These flags are used to implement various flavors of initialized
+	 common.  The SOM linker discards duplicate subspaces when they
+	 have the same "key" symbol name.  This support is more like
+	 GNU linkonce than BFD common.  Further, pc-relative relocations
+	 are converted to section relative relocations in BFD common
+	 sections.  This complicates the handling of relocations in
+	 common sections containing text and isn't currently supported
+	 correctly in the SOM BFD backend.  */
+      if (comdat || common || dup_common)
+	flags |= SEC_LINK_ONCE;
 
       flags |= SEC_RELOC | SEC_HAS_CONTENTS;
 
@@ -7649,16 +7671,16 @@ pa_subspace (create_new)
       if (ssd)
 
 	current_subspace = update_subspace (space, ss_name, loadable,
-					    code_only, common, dup_common,
-					    sort, zero, access, space_index,
-					    alignment, quadrant,
+					    code_only, comdat, common,
+					    dup_common, sort, zero, access,
+					    space_index, alignment, quadrant,
 					    section);
       else
 	current_subspace = create_new_subspace (space, ss_name, loadable,
-						code_only, common,
+						code_only, comdat, common,
 						dup_common, zero, sort,
 						access, space_index,
-					      alignment, quadrant, section);
+						alignment, quadrant, section);
 
       demand_empty_rest_of_line ();
       current_subspace->ssd_seg = section;
@@ -7779,6 +7801,7 @@ pa_spaces_begin ()
       create_new_subspace (space, name,
 			   pa_def_subspaces[i].loadable,
 			   pa_def_subspaces[i].code_only,
+			   pa_def_subspaces[i].comdat,
 			   pa_def_subspaces[i].common,
 			   pa_def_subspaces[i].dup_common,
 			   pa_def_subspaces[i].zero,
@@ -7880,12 +7903,12 @@ create_new_space (name, spnum, loadable, defined, private,
    order as defined by the SORT entries.  */
 
 static ssd_chain_struct *
-create_new_subspace (space, name, loadable, code_only, common,
+create_new_subspace (space, name, loadable, code_only, comdat, common,
 		     dup_common, is_zero, sort, access, space_index,
 		     alignment, quadrant, seg)
      sd_chain_struct *space;
      char *name;
-     int loadable, code_only, common, dup_common, is_zero;
+     int loadable, code_only, comdat, common, dup_common, is_zero;
      int sort;
      int access;
      int space_index;
@@ -7942,8 +7965,8 @@ create_new_subspace (space, name, loadable, code_only, common,
     }
 
 #ifdef obj_set_subsection_attributes
-  obj_set_subsection_attributes (seg, space->sd_seg, access,
-				 sort, quadrant);
+  obj_set_subsection_attributes (seg, space->sd_seg, access, sort,
+				 quadrant, comdat, common, dup_common);
 #endif
 
   return chain_entry;
@@ -7953,12 +7976,13 @@ create_new_subspace (space, name, loadable, code_only, common,
    various arguments.   Return the modified subspace chain entry.  */
 
 static ssd_chain_struct *
-update_subspace (space, name, loadable, code_only, common, dup_common, sort,
-		 zero, access, space_index, alignment, quadrant, section)
+update_subspace (space, name, loadable, code_only, comdat, common, dup_common,
+		 sort, zero, access, space_index, alignment, quadrant, section)
      sd_chain_struct *space;
      char *name;
      int loadable;
      int code_only;
+     int comdat;
      int common;
      int dup_common;
      int zero;
@@ -7974,8 +7998,8 @@ update_subspace (space, name, loadable, code_only, common, dup_common, sort,
   chain_entry = is_defined_subspace (name);
 
 #ifdef obj_set_subsection_attributes
-  obj_set_subsection_attributes (section, space->sd_seg, access,
-				 sort, quadrant);
+  obj_set_subsection_attributes (section, space->sd_seg, access, sort,
+				 quadrant, comdat, common, dup_common);
 #endif
 
   return chain_entry;
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5de6a55d2f5..f37c259249f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -76,6 +76,9 @@ static void set_code_flag PARAMS ((int));
 static void set_16bit_gcc_code_flag PARAMS ((int));
 static void set_intel_syntax PARAMS ((int));
 static void set_cpu_arch PARAMS ((int));
+#ifdef TE_PE
+static void pe_directive_secrel PARAMS ((int));
+#endif
 static char *output_invalid PARAMS ((int c));
 static int i386_operand PARAMS ((char *operand_string));
 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
@@ -444,6 +447,9 @@ const pseudo_typeS md_pseudo_table[] =
   {"att_syntax", set_intel_syntax, 0},
   {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
   {"loc", dwarf2_directive_loc, 0},
+#ifdef TE_PE
+  {"secrel32", pe_directive_secrel, 0},
+#endif
   {0, 0, 0}
 };
 
@@ -3638,6 +3644,50 @@ x86_cons (exp, size)
 }
 #endif
 
+#ifdef TE_PE
+
+#define O_secrel (O_max + 1)
+
+void
+x86_pe_cons_fix_new (frag, off, len, exp)
+     fragS *frag;
+     unsigned int off;
+     unsigned int len;
+     expressionS *exp;
+{
+  enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
+
+  if (exp->X_op == O_secrel)
+    {
+      exp->X_op = O_symbol;
+      r = BFD_RELOC_32_SECREL;
+    }
+
+  fix_new_exp (frag, off, len, exp, 0, r);
+}
+
+static void
+pe_directive_secrel (dummy)
+     int dummy ATTRIBUTE_UNUSED;
+{
+  expressionS exp;
+
+  do
+    {
+      expression (&exp);
+      if (exp.X_op == O_symbol)
+	exp.X_op = O_secrel;
+
+      emit_expr (&exp, 4);
+    }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;
+  demand_empty_rest_of_line ();
+}
+
+#endif
+
 static int i386_immediate PARAMS ((char *));
 
 static int
@@ -5165,6 +5215,9 @@ tc_gen_reloc (section, fixp)
     case BFD_RELOC_RVA:
     case BFD_RELOC_VTABLE_ENTRY:
     case BFD_RELOC_VTABLE_INHERIT:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       code = fixp->fx_r_type;
       break;
     default:
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 14b522b5649..5c48f58d4a5 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -408,6 +408,12 @@ extern void x86_cons_fix_new
   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 #endif
 
+#ifdef TE_PE
+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
+extern void x86_pe_cons_fix_new
+  PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
+#endif
+
 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 
 #define NO_RELOC BFD_RELOC_NONE
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index fe66ffa4ece..f5526c98010 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -636,6 +636,9 @@ static struct gr {
   valueT value;
 } gr_values[128] = {{ 1, 0, 0 }};
 
+/* Remember the alignment frag.  */
+static fragS *align_frag;
+
 /* These are the routines required to output the various types of
    unwind records.  */
 
@@ -702,6 +705,7 @@ static int ar_is_in_integer_unit PARAMS ((int regnum));
 static void set_section PARAMS ((char *name));
 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
 					  unsigned int, unsigned int));
+static void dot_align (int);
 static void dot_radix PARAMS ((int));
 static void dot_special_section PARAMS ((int));
 static void dot_proc PARAMS ((int));
@@ -898,9 +902,10 @@ static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
 static int calc_record_size PARAMS ((unw_rec_list *));
 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
-					 unsigned long, fragS *));
+					 unsigned long, fragS *,
+					 int));
 static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
-static void fixup_unw_records PARAMS ((unw_rec_list *));
+static void fixup_unw_records PARAMS ((unw_rec_list *, int));
 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
 static void generate_unwind_image PARAMS ((const char *));
@@ -1092,14 +1097,36 @@ ia64_flush_insns ()
      here.  Give an error for others.  */
   for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
     {
-      if (ptr->r.type == prologue || ptr->r.type == prologue_gr
-	  || ptr->r.type == body || ptr->r.type == endp)
+      switch (ptr->r.type)
 	{
+	case prologue:
+	case prologue_gr:
+	case body:
+	case endp:
 	  ptr->slot_number = (unsigned long) frag_more (0);
 	  ptr->slot_frag = frag_now;
+	  break;
+
+	  /* Allow any record which doesn't have a "t" field (i.e.,
+	     doesn't relate to a particular instruction).  */
+	case unwabi:
+	case br_gr:
+	case copy_state:
+	case fr_mem:
+	case frgr_mem:
+	case gr_gr:
+	case gr_mem:
+	case label_state:
+	case rp_br:
+	case spill_base:
+	case spill_mask:
+	  /* nothing */
+	  break;
+
+	default:
+	  as_bad (_("Unwind directive not followed by an instruction."));
+	  break;
 	}
-      else
-	as_bad (_("Unwind directive not followed by an instruction."));
     }
   unwind.current_entry = NULL;
 
@@ -1109,9 +1136,8 @@ ia64_flush_insns ()
     as_bad ("qualifying predicate not followed by instruction");
 }
 
-void
-ia64_do_align (nbytes)
-     int nbytes;
+static void
+ia64_do_align (int nbytes)
 {
   char *saved_input_line_pointer = input_line_pointer;
 
@@ -2590,14 +2616,16 @@ set_imask (region, regmask, t, type)
 
 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
    SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
-   containing FIRST_ADDR.  */
+   containing FIRST_ADDR.  If BEFORE_RELAX, then we use worst-case estimates
+   for frag sizes.  */
 
 unsigned long
-slot_index (slot_addr, slot_frag, first_addr, first_frag)
+slot_index (slot_addr, slot_frag, first_addr, first_frag, before_relax)
      unsigned long slot_addr;
      fragS *slot_frag;
      unsigned long first_addr;
      fragS *first_frag;
+     int before_relax;
 {
   unsigned long index = 0;
 
@@ -2612,10 +2640,10 @@ slot_index (slot_addr, slot_frag, first_addr, first_frag)
     {
       unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
 
-      if (finalize_syms)
+      if (! before_relax)
 	{
-	  /* We can get the final addresses only after relaxation is
-	     done. */
+	  /* We can get the final addresses only during and after
+	     relaxation.  */
 	  if (first_frag->fr_next && first_frag->fr_next->fr_address)
 	    index += 3 * ((first_frag->fr_next->fr_address
 			   - first_frag->fr_address
@@ -2694,8 +2722,9 @@ optimize_unw_records (list)
    within each record to generate an image.  */
 
 static void
-fixup_unw_records (list)
+fixup_unw_records (list, before_relax)
      unw_rec_list *list;
+     int before_relax;
 {
   unw_rec_list *ptr, *region = 0;
   unsigned long first_addr = 0, rlen = 0, t;
@@ -2706,7 +2735,7 @@ fixup_unw_records (list)
       if (ptr->slot_number == SLOT_NUM_NOT_SET)
 	as_bad (" Insn slot not set in unwind record.");
       t = slot_index (ptr->slot_number, ptr->slot_frag,
-		      first_addr, first_frag);
+		      first_addr, first_frag, before_relax);
       switch (ptr->r.type)
 	{
 	case prologue:
@@ -2730,7 +2759,8 @@ fixup_unw_records (list)
 		  last_frag = last->slot_frag;
 		  break;
 		}
-	    size = slot_index (last_addr, last_frag, first_addr, first_frag);
+	    size = slot_index (last_addr, last_frag, first_addr, first_frag,
+			       before_relax);
 	    rlen = ptr->r.record.r.rlen = size;
 	    if (ptr->r.type == body)
 	      /* End of region.  */
@@ -2830,6 +2860,35 @@ fixup_unw_records (list)
     }
 }
 
+/* Estimate the size of a frag before relaxing.  We only have one type of frag
+   to handle here, which is the unwind info frag.  */
+
+int
+ia64_estimate_size_before_relax (fragS *frag,
+				 asection *segtype ATTRIBUTE_UNUSED)
+{
+  unw_rec_list *list;
+  int len, size, pad;
+
+  /* ??? This code is identical to the first part of ia64_convert_frag.  */
+  list = (unw_rec_list *) frag->fr_opcode;
+  fixup_unw_records (list, 0);
+
+  len = calc_record_size (list);
+  /* pad to pointer-size boundary.  */
+  pad = len % md.pointer_size;
+  if (pad != 0)
+    len += md.pointer_size - pad;
+  /* Add 8 for the header + a pointer for the personality offset.  */
+  size = len + 8 + md.pointer_size;
+
+  /* fr_var carries the max_chars that we created the fragment with.
+     We must, of course, have allocated enough memory earlier.  */
+  assert (frag->fr_var >= size);
+
+  return frag->fr_fix + size;
+}
+
 /* This function converts a rs_machine_dependent variant frag into a
   normal fill frag with the unwind image from the the record list.  */
 void
@@ -2839,8 +2898,9 @@ ia64_convert_frag (fragS *frag)
   int len, size, pad;
   valueT flag_value;
 
+  /* ??? This code is identical to ia64_estimate_size_before_relax.  */
   list = (unw_rec_list *) frag->fr_opcode;
-  fixup_unw_records (list);
+  fixup_unw_records (list, 0);
 
   len = calc_record_size (list);
   /* pad to pointer-size boundary.  */
@@ -2974,6 +3034,14 @@ convert_expr_to_xy_reg (e, xy, regp)
 }
 
 static void
+dot_align (int arg)
+{
+  /* The current frag is an alignment frag.  */
+  align_frag = frag_now;
+  s_align_bytes (arg);
+}
+
+static void
 dot_radix (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
@@ -3264,7 +3332,7 @@ generate_unwind_image (text_name)
 
   /* Generate the unwind record.  */
   list = optimize_unw_records (unwind.list);
-  fixup_unw_records (list);
+  fixup_unw_records (list, 1);
   size = calc_record_size (list);
 
   if (size > 0 || unwind.force_unwind_entry)
@@ -3549,7 +3617,7 @@ dot_saveb (dummy)
     add_unwind_entry (output_br_mem (brmask));
 
   if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    ignore_rest_of_line ();
+    demand_empty_rest_of_line ();
 }
 
 static void
@@ -3581,7 +3649,7 @@ dot_spill (dummy)
 
   sep = parse_operand (&e);
   if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    ignore_rest_of_line ();
+    demand_empty_rest_of_line ();
 
   if (e.X_op != O_constant)
     as_bad ("Operand to .spill must be a constant");
@@ -3857,7 +3925,7 @@ dot_unwabi (dummy)
     }
   sep = parse_operand (&e2);
   if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    ignore_rest_of_line ();
+    demand_empty_rest_of_line ();
 
   if (e1.X_op != O_constant)
     {
@@ -3952,7 +4020,7 @@ dot_prologue (dummy)
 	as_bad ("No second operand to .prologue");
       sep = parse_operand (&e2);
       if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-	ignore_rest_of_line ();
+	demand_empty_rest_of_line ();
 
       if (e1.X_op == O_constant)
 	{
@@ -4900,7 +4968,7 @@ const pseudo_typeS md_pseudo_table[] =
     { "lb", dot_scope, 0 },
     { "le", dot_scope, 1 },
 #endif
-    { "align", s_align_bytes, 0 },
+    { "align", dot_align, 0 },
     { "regstk", dot_regstk, 0 },
     { "rotr", dot_rot, DYNREG_GR },
     { "rotf", dot_rot, DYNREG_FR },
@@ -9933,7 +10001,27 @@ md_assemble (str)
   flags = idesc->flags;
 
   if ((flags & IA64_OPCODE_FIRST) != 0)
-    insn_group_break (1, 0, 0);
+    {
+      /* The alignment frag has to end with a stop bit only if the
+	 next instruction after the alignment directive has to be
+	 the first instruction in an instruction group.  */
+      if (align_frag)
+	{
+	  while (align_frag->fr_type != rs_align_code)
+	    {
+	      align_frag = align_frag->fr_next;
+	      if (!align_frag)
+		break;
+	    }
+	  /* align_frag can be NULL if there are directives in
+	     between.  */
+	  if (align_frag && align_frag->fr_next == frag_now)
+	    align_frag->tc_frag_data = 1;
+	}
+
+      insn_group_break (1, 0, 0);
+    }
+  align_frag = NULL;
 
   if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
     {
@@ -10766,16 +10854,43 @@ ia64_handle_align (fragp)
   static const unsigned char le_nop[]
     = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
 	0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
+  static const unsigned char le_nop_stop[]
+    = { 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
 
   int bytes;
   char *p;
+  const unsigned char *nop;
 
   if (fragp->fr_type != rs_align_code)
     return;
 
+  /* Check if this frag has to end with a stop bit.  */
+  nop = fragp->tc_frag_data ? le_nop_stop : le_nop;
+
   bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
   p = fragp->fr_literal + fragp->fr_fix;
 
+  /* If no paddings are needed, we check if we need a stop bit.  */ 
+  if (!bytes && fragp->tc_frag_data)
+    {
+      if (fragp->fr_fix < 16)
+#if 1
+	/* FIXME: It won't work with
+	   .align 16
+	   alloc r32=ar.pfs,1,2,4,0
+	 */
+	;
+#else
+	as_bad_where (fragp->fr_file, fragp->fr_line,
+		      _("Can't add stop bit to mark end of instruction group"));
+#endif
+      else
+	/* Bundles are always in little-endian byte order. Make sure
+	   the previous bundle has the stop bit.  */
+	*(p - 16) |= 1;
+    }
+
   /* Make sure we are on a 16-byte boundary, in case someone has been
      putting data into a text section.  */
   if (bytes & 15)
@@ -10788,7 +10903,7 @@ ia64_handle_align (fragp)
     }
 
   /* Instruction bundles are always little-endian.  */
-  memcpy (p, le_nop, 16);
+  memcpy (p, nop, 16);
   fragp->fr_var = 16;
 }
 
diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h
index d1a04ee0187..dcc2c299602 100644
--- a/gas/config/tc-ia64.h
+++ b/gas/config/tc-ia64.h
@@ -86,7 +86,6 @@ struct ia64_fix
     enum ia64_opnd opnd;
   };
 
-extern void ia64_do_align PARAMS((int n));
 extern void ia64_end_of_source PARAMS((void));
 extern void ia64_start_line PARAMS((void));
 extern int ia64_unrecognized_line PARAMS((int ch));
@@ -115,6 +114,7 @@ extern void ia64_handle_align PARAMS ((fragS *f));
 extern void ia64_after_parse_args PARAMS ((void));
 extern void ia64_dwarf2_emit_offset PARAMS ((symbolS *, unsigned int));
 extern void ia64_check_label PARAMS ((symbolS *));
+extern int ia64_estimate_size_before_relax (fragS *, asection *);
 extern void ia64_convert_frag (fragS *);
 
 #define md_end()       			ia64_end_of_source ()
@@ -138,7 +138,7 @@ extern void ia64_convert_frag (fragS *);
 #define md_create_short_jump(p,f,t,fr,s) \
 					as_fatal ("ia64_create_short_jump")
 #define md_estimate_size_before_relax(f,s) \
-					(f)->fr_var
+					ia64_estimate_size_before_relax(f,s)
 #define md_elf_section_letter		ia64_elf_section_letter
 #define md_elf_section_flags		ia64_elf_section_flags
 #define TC_FIX_TYPE			struct ia64_fix
@@ -154,6 +154,10 @@ extern void ia64_convert_frag (fragS *);
 #define TC_DWARF2_EMIT_OFFSET		ia64_dwarf2_emit_offset
 #define tc_check_label(l)		ia64_check_label (l)
 
+/* Record if an alignment frag should end with a stop bit.  */
+#define TC_FRAG_TYPE			int
+#define TC_FRAG_INIT(FRAGP)		do {(FRAGP)->tc_frag_data = 0;}while (0)
+
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (15 + 16)
 
 #define WORKING_DOT_WORD	/* don't do broken word processing for now */
diff --git a/gas/config/tc-iq2000.c b/gas/config/tc-iq2000.c
index 0ab650aa283..9f591d39a27 100644
--- a/gas/config/tc-iq2000.c
+++ b/gas/config/tc-iq2000.c
@@ -1,5 +1,5 @@
 /* tc-iq2000.c -- Assembler for the Sitera IQ2000.
-   Copyright (C) 2003 Free Software Foundation.
+   Copyright (C) 2003, 2004 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -357,7 +357,7 @@ static const char * li_expn    = "\n\
  ori \\rt,%0,\\imm\n\
  .elseif (\\imm & 0xffff0000 == 0xffff0000)\n\
  addi \\rt,%0,\\imm\n\
- .elseif (\\imm & 0x0000ffff == 0)
+ .elseif (\\imm & 0x0000ffff == 0)\n\
  lui \\rt,%uhi(\\imm)\n\
  .else\n\
  lui \\rt,%uhi(\\imm)\n\
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index fb1c61354fb..e990d9d941c 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -1,5 +1,5 @@
 /* tc-m32r.c -- Assembler for the Renesas M32R.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -109,7 +109,7 @@ static int enable_special = 0;
 
 /* Non-zero if -bitinst has been specified, in which case support
    for extended M32R bit-field instruction set should be enabled.  */
-static int enable_special_m32r = 0;
+static int enable_special_m32r = 1;
 
 /* Non-zero if -float has been specified, in which case support for
    extended M32R floating point instruction set should be enabled.  */
@@ -216,7 +216,8 @@ struct option md_longopts[] =
 #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
 #define OPTION_SPECIAL		  (OPTION_NO_IGNORE_PARALLEL + 1)
 #define OPTION_SPECIAL_M32R       (OPTION_SPECIAL + 1)
-#define OPTION_SPECIAL_FLOAT      (OPTION_SPECIAL_M32R + 1)
+#define OPTION_NO_SPECIAL_M32R    (OPTION_SPECIAL_M32R + 1)
+#define OPTION_SPECIAL_FLOAT      (OPTION_NO_SPECIAL_M32R + 1)
 #define OPTION_WARN_UNMATCHED 	  (OPTION_SPECIAL_FLOAT + 1)
 #define OPTION_NO_WARN_UNMATCHED  (OPTION_WARN_UNMATCHED + 1)
   {"m32r",  no_argument, NULL, OPTION_M32R},
@@ -238,6 +239,7 @@ struct option md_longopts[] =
   {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
   {"hidden", no_argument, NULL, OPTION_SPECIAL},
   {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
+  {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
   {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
   /* Sigh.  I guess all warnings must now have both variants.  */
   {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
@@ -353,6 +355,10 @@ md_parse_option (c, arg)
       enable_special_m32r = 1;
       break;
 
+    case OPTION_NO_SPECIAL_M32R:
+      enable_special_m32r = 0;
+      break;
+
     case OPTION_SPECIAL_FLOAT:
       enable_special_float = 1;
       break;
@@ -410,6 +416,8 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -no-parallel            disable -parallel\n"));
   fprintf (stream, _("\
+  -no-bitinst             disallow the M32R2's extended bit-field instructions\n"));
+  fprintf (stream, _("\
   -O                      try to optimize code.  Implies -parallel\n"));
 
   fprintf (stream, _("\
@@ -1374,6 +1382,14 @@ md_assemble (str)
 	 prev_insn.insn is NULL when we're on a 32 bit boundary.  */
       on_32bit_boundary_p = prev_insn.insn == NULL;
 
+      /* Change a frag to, if each insn to swap is in a different frag.
+         It must keep only one instruction in a frag.  */
+      if (parallel() && on_32bit_boundary_p)
+        {
+          frag_wane (frag_now);
+          frag_new (0);
+        }
+
       /* Look to see if this instruction can be combined with the
 	 previous instruction to make one, parallel, 32 bit instruction.
 	 If the previous instruction (potentially) changed the flow of
@@ -1434,13 +1450,25 @@ md_assemble (str)
 	  else if (insn.frag->fr_opcode == insn.addr)
 	    insn.frag->fr_opcode = prev_insn.addr;
 
-	  /* Update the addresses in any fixups.
-	     Note that we don't have to handle the case where each insn is in
-	     a different frag as we ensure they're in the same frag above.  */
-	  for (i = 0; i < prev_insn.num_fixups; ++i)
-	    prev_insn.fixups[i]->fx_where += 2;
-	  for (i = 0; i < insn.num_fixups; ++i)
-	    insn.fixups[i]->fx_where -= 2;
+          /* Change a frag to, if each insn is in a different frag.
+	     It must keep only one instruction in a frag.  */
+          if (prev_insn.frag != insn.frag)
+            {
+              for (i = 0; i < prev_insn.num_fixups; ++i)
+                prev_insn.fixups[i]->fx_frag = insn.frag;
+              for (i = 0; i < insn.num_fixups; ++i)
+                insn.fixups[i]->fx_frag = prev_insn.frag;
+            }
+          else
+	    {
+	      /* Update the addresses in any fixups.
+		 Note that we don't have to handle the case where each insn is in
+		 a different frag as we ensure they're in the same frag above.  */
+	      for (i = 0; i < prev_insn.num_fixups; ++i)
+		prev_insn.fixups[i]->fx_where += 2;
+	      for (i = 0; i < insn.num_fixups; ++i)
+		insn.fixups[i]->fx_where -= 2;
+	    }
 	}
 
       /* Keep track of whether we've seen a pair of 16 bit insns.
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index 5bef34b4efd..86fa9dc7a81 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -371,52 +371,52 @@ struct m68k_cpu
 
 static const struct m68k_cpu archs[] =
   {
-    { m68000,  "68000", 0 },
-    { m68010,  "68010", 0 },
-    { m68020,  "68020", 0 },
-    { m68030,  "68030", 0 },
-    { m68040,  "68040", 0 },
-    { m68060,  "68060", 0 },
-    { cpu32,   "cpu32", 0 },
-    { m68881,  "68881", 0 },
-    { m68851,  "68851", 0 },
-    { mcf5200, "5200",  0 },
-    { mcf5206e,"5206e", 0 },
-    { mcf528x, "528x",  0 },
-    { mcf5307, "5307",  0 },
-    { mcf5407, "5407",  0 },
-    { mcfv4e,  "cfv4e", 0 },
+    { m68000,		"68000", 0 },
+    { m68010,		"68010", 0 },
+    { m68020,		"68020", 0 },
+    { m68030,		"68030", 0 },
+    { m68040,		"68040", 0 },
+    { m68060,		"68060", 0 },
+    { cpu32,		"cpu32", 0 },
+    { m68881,		"68881", 0 },
+    { m68851,		"68851", 0 },
+    { mcf5200,		"5200",  0 },
+    { mcf5206e,		"5206e", 0 },
+    { mcf528x|mcfmac,	"528x",  0 },
+    { mcf5307|mcfmac,	"5307",  0 },
+    { mcf5407|mcfmac,	"5407",  0 },
+    { mcfv4e|mcfemac,	"cfv4e", 0 },
     /* Aliases (effectively, so far as gas is concerned) for the above
        cpus.  */
-    { m68020, "68k", 1 },
-    { m68000, "68008", 1 },
-    { m68000, "68302", 1 },
-    { m68000, "68306", 1 },
-    { m68000, "68307", 1 },
-    { m68000, "68322", 1 },
-    { m68000, "68356", 1 },
-    { m68000, "68ec000", 1 },
-    { m68000, "68hc000", 1 },
-    { m68000, "68hc001", 1 },
-    { m68020, "68ec020", 1 },
-    { m68030, "68ec030", 1 },
-    { m68040, "68ec040", 1 },
-    { m68060, "68ec060", 1 },
-    { cpu32,  "68330", 1 },
-    { cpu32,  "68331", 1 },
-    { cpu32,  "68332", 1 },
-    { cpu32,  "68333", 1 },
-    { cpu32,  "68334", 1 },
-    { cpu32,  "68336", 1 },
-    { cpu32,  "68340", 1 },
-    { cpu32,  "68341", 1 },
-    { cpu32,  "68349", 1 },
-    { cpu32,  "68360", 1 },
-    { m68881, "68882", 1 },
-    { mcf5200, "5202", 1 },
-    { mcf5200, "5204", 1 },
-    { mcf5200, "5206", 1 },
-    { mcf5407, "cfv4", 1 },
+    { m68020,		"68k", 1 },
+    { m68000,		"68008", 1 },
+    { m68000,		"68302", 1 },
+    { m68000,		"68306", 1 },
+    { m68000,		"68307", 1 },
+    { m68000,		"68322", 1 },
+    { m68000,		"68356", 1 },
+    { m68000,		"68ec000", 1 },
+    { m68000,		"68hc000", 1 },
+    { m68000,		"68hc001", 1 },
+    { m68020,		"68ec020", 1 },
+    { m68030,		"68ec030", 1 },
+    { m68040,		"68ec040", 1 },
+    { m68060,		"68ec060", 1 },
+    { cpu32,		"68330", 1 },
+    { cpu32,		"68331", 1 },
+    { cpu32,		"68332", 1 },
+    { cpu32,		"68333", 1 },
+    { cpu32,		"68334", 1 },
+    { cpu32,		"68336", 1 },
+    { cpu32,		"68340", 1 },
+    { cpu32,		"68341", 1 },
+    { cpu32,		"68349", 1 },
+    { cpu32,		"68360", 1 },
+    { m68881,		"68882", 1 },
+    { mcf5200,		"5202", 1 },
+    { mcf5200,		"5204", 1 },
+    { mcf5200,		"5206", 1 },
+    { mcf5407|mcfmac,	"cfv4", 1 },
   };
 
 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
@@ -1505,6 +1505,14 @@ m68k_ip (instring)
 		    ++losing;
 		  break;
 
+		case '4':
+		  if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
+		      && (opP->mode != DISP
+			   || opP->reg < ADDR0
+			   || opP->reg > ADDR7))
+		    ++losing;
+		  break;
+
 		case 'B':	/* FOO */
 		  if (opP->mode != ABSL
 		      || (flag_long_jumps
@@ -1552,6 +1560,12 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'e':
+		  if (opP->reg != ACC && opP->reg != ACC1
+		      && opP->reg != ACC2 && opP->reg != ACC3)
+		    losing++;
+		  break;
+
 		case 'F':
 		  if (opP->mode != FPREG)
 		    losing++;
@@ -1562,6 +1576,11 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'g':
+		  if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
+		    losing++;
+		  break;
+
 		case 'H':
 		  if (opP->reg != MASK)
 		    losing++;
@@ -1574,6 +1593,11 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'i':
+		  if (opP->mode != LSH && opP->mode != RSH)
+		    losing++;
+		  break;
+
 		case 'J':
 		  if (opP->mode != CONTROL
 		      || opP->reg < USP
@@ -1994,6 +2018,7 @@ m68k_ip (instring)
 	case 'w':
 	case 'y':
 	case 'z':
+	case '4':
 #ifndef NO_68851
 	case '|':
 #endif
@@ -2519,6 +2544,16 @@ m68k_ip (instring)
 	      as_bad (_("unknown/incorrect operand"));
 	      /* abort (); */
 	    }
+
+	  /* If s[0] is '4', then this is for the mac instructions
+	     that can have a trailing_ampersand set.  If so, set 0x100
+	     bit on tmpreg so install_gen_operand can check for it and
+	     set the appropriate bit (word2, bit 5).  */
+	  if (s[0] == '4')
+	    {
+	      if (opP->trailing_ampersand)
+		tmpreg |= 0x100;
+	    }
 	  install_gen_operand (s[1], tmpreg);
 	  break;
 
@@ -2737,6 +2772,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - DATA);
 	  break;
 
+	case 'e':  /* EMAC ACCx, reg/reg.  */
+	  install_operand (s[1], opP->reg - ACC);
+	  break;
+	  
 	case 'E':		/* Ignore it.  */
 	  break;
 
@@ -2744,6 +2783,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - FP0);
 	  break;
 
+	case 'g':  /* EMAC ACCEXTx.  */
+	  install_operand (s[1], opP->reg - ACCEXT01);
+	  break;
+
 	case 'G':		/* Ignore it.  */
 	case 'H':
 	  break;
@@ -2753,6 +2796,10 @@ m68k_ip (instring)
 	  install_operand (s[1], tmpreg);
 	  break;
 
+	case 'i':  /* MAC/EMAC scale factor.  */
+	  install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
+	  break;
+
 	case 'J':		/* JF foo.  */
 	  switch (opP->reg)
 	    {
@@ -3286,25 +3333,46 @@ install_operand (mode, val)
       the_ins.opcode[0] |= ((val & 0x7) << 9);
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'n':
+    case 'n': /* MAC/EMAC Rx on !load.  */
       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
       the_ins.opcode[0] |= ((val & 0x7) << 9);
+      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'o':
+    case 'o': /* MAC/EMAC Rx on load.  */
       the_ins.opcode[1] |= val << 12;
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'M':
+    case 'M': /* MAC/EMAC Ry on !load.  */
       the_ins.opcode[0] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
-    case 'N':
+    case 'N': /* MAC/EMAC Ry on load.  */
       the_ins.opcode[1] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
     case 'h':
       the_ins.opcode[1] |= ((val != 1) << 10);
       break;
+    case 'F':
+      the_ins.opcode[0] |= ((val & 0x3) << 9);
+      break;
+    case 'f':
+      the_ins.opcode[0] |= ((val & 0x3) << 0);
+      break;
+    case 'G':
+      the_ins.opcode[0] |= ((~val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'H':
+      the_ins.opcode[0] |= ((val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'I':
+      the_ins.opcode[1] |= ((val & 0x3) << 9);
+      break;
+    case ']':
+      the_ins.opcode[0] |= (val & 0x1) <<10;
+      break;
     case 'c':
     default:
       as_fatal (_("failed sanity check."));
@@ -3318,6 +3386,11 @@ install_gen_operand (mode, val)
 {
   switch (mode)
     {
+    case '/':  /* Special for mask loads for mac/msac insns with
+		  possible mask; trailing_ampersend set in bit 8.  */
+      the_ins.opcode[0] |= (val & 0x3f);
+      the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
+      break;
     case 's':
       the_ins.opcode[0] |= val;
       break;
@@ -3507,6 +3580,12 @@ static const struct init_entry init_table[] =
   { "cc", CCR },
 
   { "acc", ACC },
+  { "acc0", ACC },
+  { "acc1", ACC1 },
+  { "acc2", ACC2 },
+  { "acc3", ACC3 },
+  { "accext01", ACCEXT01 },
+  { "accext23", ACCEXT23 },
   { "macsr", MACSR },
   { "mask", MASK },
 
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index beaa11a5aaf..6f0db0912ff 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -111,9 +111,7 @@ static char *mips_regmask_frag;
 extern int target_big_endian;
 
 /* The name of the readonly data section.  */
-#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
-			    ? ".data" \
-			    : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
+#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
 			    ? ".rdata" \
 			    : OUTPUT_FLAVOR == bfd_target_coff_flavour \
 			    ? ".rdata" \
@@ -281,13 +279,11 @@ static int mips_32bitmode = 0;
 
 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
 
-/* We can only have 64bit addresses if the object file format
-   supports it.  */
+/* We can only have 64bit addresses if the object file format supports it.  */
 #define HAVE_32BIT_ADDRESSES                           \
    (HAVE_32BIT_GPRS                                    \
-    || ((bfd_arch_bits_per_address (stdoutput) == 32   \
-         || ! HAVE_64BIT_OBJECTS)                      \
-        && mips_pic != EMBEDDED_PIC))
+    || (bfd_arch_bits_per_address (stdoutput) == 32    \
+        || ! HAVE_64BIT_OBJECTS))                      \
 
 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
 
@@ -346,7 +342,6 @@ static int mips_32bitmode = 0;
    || mips_opts.arch == CPU_R10000                    \
    || mips_opts.arch == CPU_R12000                    \
    || mips_opts.arch == CPU_RM7000                    \
-   || mips_opts.arch == CPU_SB1                       \
    || mips_opts.arch == CPU_VR5500                    \
    )
 
@@ -357,8 +352,6 @@ static int mips_32bitmode = 0;
    level I.  */
 #define gpr_interlocks \
   (mips_opts.isa != ISA_MIPS1  \
-   || mips_opts.arch == CPU_VR5400  \
-   || mips_opts.arch == CPU_VR5500  \
    || mips_opts.arch == CPU_R3900)
 
 /* Whether the processor uses hardware interlocks to avoid delays
@@ -374,9 +367,6 @@ static int mips_32bitmode = 0;
     && mips_opts.isa != ISA_MIPS2                     \
     && mips_opts.isa != ISA_MIPS3)                    \
    || mips_opts.arch == CPU_R4300                     \
-   || mips_opts.arch == CPU_VR5400                    \
-   || mips_opts.arch == CPU_VR5500                    \
-   || mips_opts.arch == CPU_SB1                       \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads
@@ -622,7 +612,7 @@ static const unsigned int mips16_to_32_reg_map[] =
   16, 17, 2, 3, 4, 5, 6, 7
 };
 
-static int mips_fix_4122_bugs;
+static int mips_fix_vr4120;
 
 /* We don't relax branches by default, since this causes us to expand
    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
@@ -1089,8 +1079,6 @@ mips_target_format (void)
 {
   switch (OUTPUT_FLAVOR)
     {
-    case bfd_target_aout_flavour:
-      return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
     case bfd_target_ecoff_flavour:
       return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
     case bfd_target_coff_flavour:
@@ -1247,8 +1235,7 @@ md_begin (void)
   /* set the default alignment for the text section (2**2) */
   record_alignment (text_section, 2);
 
-  if (USE_GLOBAL_POINTER_OPT)
-    bfd_set_gp_size (stdoutput, g_switch_value);
+  bfd_set_gp_size (stdoutput, g_switch_value);
 
   if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
     {
@@ -1863,11 +1850,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
       if (prev_prev_nop && nops == 0)
 	++nops;
 
-      if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
+      if (mips_fix_vr4120 && prev_insn.insn_mo->name)
 	{
 	  /* We're out of bits in pinfo, so we must resort to string
 	     ops here.  Shortcuts are selected based on opcodes being
-	     limited to the VR4122 instruction set.  */
+	     limited to the VR4120 instruction set.  */
 	  int min_nops = 0;
 	  const char *pn = prev_insn.insn_mo->name;
 	  const char *tn = ip->insn_mo->name;
@@ -2494,11 +2481,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      || (mips_opts.mips16
 		  && (pinfo & MIPS16_INSN_WRITE_31)
 		  && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
-	      /* If we are generating embedded PIC code, the branch
-		 might be expanded into a sequence which uses $at, so
-		 we can't swap with an instruction which reads it.  */
-	      || (mips_pic == EMBEDDED_PIC
-		  && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
 	      /* If the previous previous instruction has a load
 		 delay, and sets a register that the branch reads, we
 		 can not swap.  */
@@ -2841,7 +2823,7 @@ mips_emit_delays (bfd_boolean insns)
 	    ++nops;
 	}
 
-      if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
+      if (mips_fix_vr4120 && prev_insn.insn_mo->name)
 	{
 	  int min_nops = 0;
 	  const char *pn = prev_insn.insn_mo->name;
@@ -3143,9 +3125,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 		  || *r == BFD_RELOC_MIPS_GOT_PAGE
 		  || *r == BFD_RELOC_MIPS_GOT_OFST
 		  || *r == BFD_RELOC_MIPS_GOT_LO16
-		  || *r == BFD_RELOC_MIPS_CALL_LO16
-		  || (ep->X_op == O_subtract
-		      && *r == BFD_RELOC_PCREL_LO16));
+		  || *r == BFD_RELOC_MIPS_CALL_LO16);
 	  continue;
 
 	case 'u':
@@ -3158,9 +3138,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 			      || *r == BFD_RELOC_HI16
 			      || *r == BFD_RELOC_GPREL16
 			      || *r == BFD_RELOC_MIPS_GOT_HI16
-			      || *r == BFD_RELOC_MIPS_CALL_HI16))
-		      || (ep->X_op == O_subtract
-			  && *r == BFD_RELOC_PCREL_HI16_S)));
+			      || *r == BFD_RELOC_MIPS_CALL_HI16))));
 	  continue;
 
 	case 'p':
@@ -3789,6 +3767,13 @@ load_register (int reg, expressionS *ep, int dbl)
     macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
 }
 
+static inline void
+load_delay_nop (void)
+{
+  if (!gpr_interlocks)
+    macro_build (NULL, "nop", "");
+}
+
 /* Load an address into a register.  */
 
 static void
@@ -3922,7 +3907,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	  ep->X_add_number = 0;
 	  macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  relax_start (ep->X_add_symbol);
 	  relax_switch ();
 	  macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
@@ -4007,7 +3992,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    }
 	  macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
 		       BFD_RELOC_LO16);
 	  relax_end ();
@@ -4022,14 +4007,6 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    }
 	}
     }
-  else if (mips_pic == EMBEDDED_PIC)
-    {
-      /* We always do
-	   addiu	$reg,$gp,<sym>		(BFD_RELOC_GPREL16)
-       */
-      macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
-		   reg, mips_gp_register, BFD_RELOC_GPREL16);
-    }
   else
     abort ();
 }
@@ -4888,50 +4865,6 @@ macro (struct mips_cl_insn *ip)
 	  used_at = 0;
 	}
 
-      /* When generating embedded PIC code, we permit expressions of
-	 the form
-	   la	$treg,foo-bar
-	   la	$treg,foo-bar($breg)
-	 where bar is an address in the current section.  These are used
-	 when getting the addresses of functions.  We don't permit
-	 X_add_number to be non-zero, because if the symbol is
-	 external the relaxing code needs to know that any addend is
-	 purely the offset to X_op_symbol.  */
-      if (mips_pic == EMBEDDED_PIC
-	  && offset_expr.X_op == O_subtract
-	  && (symbol_constant_p (offset_expr.X_op_symbol)
-	      ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
-	      : (symbol_equated_p (offset_expr.X_op_symbol)
-		 && (S_GET_SEGMENT
-		     (symbol_get_value_expression (offset_expr.X_op_symbol)
-		      ->X_add_symbol)
-		     == now_seg)))
-	  && (offset_expr.X_add_number == 0
-	      || OUTPUT_FLAVOR == bfd_target_elf_flavour))
-	{
-	  if (breg == 0)
-	    {
-	      tempreg = treg;
-	      used_at = 0;
-	      macro_build (&offset_expr, "lui", "t,u",
-			   tempreg, BFD_RELOC_PCREL_HI16_S);
-	    }
-	  else
-	    {
-	      macro_build (&offset_expr, "lui", "t,u",
-			   tempreg, BFD_RELOC_PCREL_HI16_S);
-	      macro_build (NULL,
-			   (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
-			   "d,v,t", tempreg, tempreg, breg);
-	    }
-	  macro_build (&offset_expr,
-		       (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
-		       "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
-	  if (! used_at)
-	    return;
-	  break;
-	}
-
       if (offset_expr.X_op != O_symbol
 	  && offset_expr.X_op != O_constant)
 	{
@@ -4941,7 +4874,7 @@ macro (struct mips_cl_insn *ip)
 
       if (offset_expr.X_op == O_constant)
 	load_register (tempreg, &offset_expr,
-		       ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+		       (mips_pic == NO_PIC
 			? (dbl || HAVE_64BIT_ADDRESSES)
 			: HAVE_64BIT_ADDRESSES));
       else if (mips_pic == NO_PIC)
@@ -5069,12 +5002,12 @@ macro (struct mips_cl_insn *ip)
 		  /* We're going to put in an addu instruction using
 		     tempreg, so we may as well insert the nop right
 		     now.  */
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		}
 	      relax_switch ();
 	      macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			   tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	      relax_end ();
@@ -5086,7 +5019,7 @@ macro (struct mips_cl_insn *ip)
 		   && offset_expr.X_add_number < 0x8000)
 	    {
 	      load_got_offset (tempreg, &offset_expr);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      add_got_offset (tempreg, &offset_expr);
 	    }
 	  else
@@ -5105,7 +5038,7 @@ macro (struct mips_cl_insn *ip)
 		 not using a base register.  */
 	      if (breg == treg)
 		{
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  breg = 0;
@@ -5288,13 +5221,13 @@ macro (struct mips_cl_insn *ip)
 		  /* We're going to put in an addu instruction using
 		     tempreg, so we may as well insert the nop right
 		     now.  */
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		}
 	    }
 	  else if (expr1.X_add_number >= -0x8000
 		   && expr1.X_add_number < 0x8000)
 	    {
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	    }
@@ -5314,7 +5247,7 @@ macro (struct mips_cl_insn *ip)
 	      else
 		{
 		  assert (tempreg == AT);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  dreg = treg;
@@ -5341,7 +5274,7 @@ macro (struct mips_cl_insn *ip)
 	  if (expr1.X_add_number >= -0x8000
 	      && expr1.X_add_number < 0x8000)
 	    {
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	      /* FIXME: If add_number is 0, and there was no base
@@ -5357,7 +5290,7 @@ macro (struct mips_cl_insn *ip)
 		  /* We must add in the base register now, as in the
 		     external symbol case.  */
 		  assert (tempreg == AT);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  tempreg = treg;
@@ -5481,14 +5414,6 @@ macro (struct mips_cl_insn *ip)
 	    }
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* We use
-	       addiu	$tempreg,$gp,<sym>	(BFD_RELOC_GPREL16)
-	     */
-	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
-		       mips_gp_register, BFD_RELOC_GPREL16);
-	}
       else
 	abort ();
 
@@ -5496,7 +5421,7 @@ macro (struct mips_cl_insn *ip)
 	{
 	  char *s;
 
-	  if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+	  if (mips_pic == NO_PIC)
 	    s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
 	  else
 	    s = ADDRESS_ADD_INSN;
@@ -5526,8 +5451,7 @@ macro (struct mips_cl_insn *ip)
       dreg = RA;
       /* Fall through.  */
     case M_JAL_2:
-      if (mips_pic == NO_PIC
-	  || mips_pic == EMBEDDED_PIC)
+      if (mips_pic == NO_PIC)
 	macro_build (NULL, "jalr", "d,s", dreg, sreg);
       else if (mips_pic == SVR4_PIC)
 	{
@@ -5643,7 +5567,7 @@ macro (struct mips_cl_insn *ip)
 		  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			       PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
 			       mips_gp_register);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  relax_switch ();
 		}
 	      else
@@ -5658,7 +5582,7 @@ macro (struct mips_cl_insn *ip)
 		  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			       PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
 			       PIC_CALL_REG);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  relax_switch ();
 		  if (gpdelay)
 		    macro_build (NULL, "nop", "");
@@ -5666,7 +5590,7 @@ macro (struct mips_cl_insn *ip)
 	      macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			   PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
 			   mips_gp_register);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
 	      relax_end ();
@@ -5698,13 +5622,6 @@ macro (struct mips_cl_insn *ip)
 		}
 	    }
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  macro_build (&offset_expr, "bal", "p");
-	  /* The linker may expand the call to a longer sequence which
-	     uses $at, so we must break rather than return.  */
-	  break;
-	}
       else
 	abort ();
 
@@ -5900,46 +5817,6 @@ macro (struct mips_cl_insn *ip)
 				       ^ 0x80000000) - 0x80000000);
 	}
 
-      /* For embedded PIC, we allow loads where the offset is calculated
-         by subtracting a symbol in the current segment from an unknown
-         symbol, relative to a base register, e.g.:
-		<op>	$treg, <sym>-<localsym>($breg)
-	 This is used by the compiler for switch statements.  */
-      if (mips_pic == EMBEDDED_PIC
-          && offset_expr.X_op == O_subtract
-          && (symbol_constant_p (offset_expr.X_op_symbol)
-              ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
-              : (symbol_equated_p (offset_expr.X_op_symbol)
-                 && (S_GET_SEGMENT
-                     (symbol_get_value_expression (offset_expr.X_op_symbol)
-                      ->X_add_symbol)
-                     == now_seg)))
-          && breg != 0
-          && (offset_expr.X_add_number == 0
-              || OUTPUT_FLAVOR == bfd_target_elf_flavour))
-        {
-          /* For this case, we output the instructions:
-                lui     $tempreg,<sym>          (BFD_RELOC_PCREL_HI16_S)
-                addiu   $tempreg,$tempreg,$breg
-                <op>    $treg,<sym>($tempreg)   (BFD_RELOC_PCREL_LO16)
-             If the relocation would fit entirely in 16 bits, it would be
-             nice to emit:
-                <op>    $treg,<sym>($breg)      (BFD_RELOC_PCREL_LO16)
-             instead, but that seems quite difficult.  */
-          macro_build (&offset_expr, "lui", "t,u", tempreg,
-		       BFD_RELOC_PCREL_HI16_S);
-          macro_build (NULL,
-		       ((bfd_arch_bits_per_address (stdoutput) == 32
-			 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
-			? "addu" : "daddu"),
-		       "d,v,t", tempreg, tempreg, breg);
-          macro_build (&offset_expr, s, fmt, treg,
-		       BFD_RELOC_PCREL_LO16, tempreg);
-          if (! used_at)
-            return;
-          break;
-        }
-
       if (offset_expr.X_op != O_constant
 	  && offset_expr.X_op != O_symbol)
 	{
@@ -6166,7 +6043,7 @@ macro (struct mips_cl_insn *ip)
 	    as_bad (_("PIC code offset overflow (max 16 signed bits)"));
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
 		       lw_reloc_type, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  relax_start (offset_expr.X_add_symbol);
 	  relax_switch ();
 	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
@@ -6216,7 +6093,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "nop", "");
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
 		       tempreg, BFD_RELOC_LO16);
 	  relax_end ();
@@ -6265,29 +6142,6 @@ macro (struct mips_cl_insn *ip)
 		       BFD_RELOC_MIPS_GOT_OFST, tempreg);
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* If there is no base register, we want
-	       <op>	$treg,<sym>($gp)	(BFD_RELOC_GPREL16)
-	     If there is a base register, we want
-	       addu	$tempreg,$breg,$gp
-	       <op>	$treg,<sym>($tempreg)	(BFD_RELOC_GPREL16)
-	     */
-	  assert (offset_expr.X_op == O_symbol);
-	  if (breg == 0)
-	    {
-	      macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
-			   mips_gp_register);
-	      used_at = 0;
-	    }
-	  else
-	    {
-	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
-			   tempreg, breg, mips_gp_register);
-	      macro_build (&offset_expr, s, fmt, treg,
-			   BFD_RELOC_GPREL16, tempreg);
-	    }
-	}
       else
 	abort ();
 
@@ -6375,15 +6229,6 @@ macro (struct mips_cl_insn *ip)
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* For embedded PIC we pick up the entire address off $gp in
-	     a single instruction.  */
-	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
-		       mips_gp_register, BFD_RELOC_GPREL16);
-	  offset_expr.X_op = O_constant;
-	  offset_expr.X_add_number = 0;
-	}
       else
 	abort ();
 
@@ -6564,11 +6409,6 @@ macro (struct mips_cl_insn *ip)
       fmt = "t,o(b)";
 
     ldd_std:
-      /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
-	 loads for the case of doing a pair of loads to simulate an 'ld'.
-	 This is not currently done by the compiler, and assembly coders
-	 writing embedded-pic code can cope.  */
-
       if (offset_expr.X_op != O_symbol
 	  && offset_expr.X_op != O_constant)
 	{
@@ -6691,7 +6531,7 @@ macro (struct mips_cl_insn *ip)
 	      || expr1.X_add_number >= 0x8000 - 4)
 	    as_bad (_("PIC code offset overflow (max 16 signed bits)"));
 	  load_got_offset (AT, &offset_expr);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 
@@ -6750,7 +6590,7 @@ macro (struct mips_cl_insn *ip)
 		       AT, AT, mips_gp_register);
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 		       AT, BFD_RELOC_MIPS_GOT_LO16, AT);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 	  /* Itbl support may require additional care here.  */
@@ -6774,7 +6614,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "nop", "");
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 	  /* Itbl support may require additional care here.  */
@@ -6792,37 +6632,6 @@ macro (struct mips_cl_insn *ip)
 	  mips_optimize = hold_mips_optimize;
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* If there is no base register, we use
-	       <op>	$treg,<sym>($gp)	(BFD_RELOC_GPREL16)
-	       <op>	$treg+1,<sym>+4($gp)	(BFD_RELOC_GPREL16)
-	     If we have a base register, we use
-	       addu	$at,$breg,$gp
-	       <op>	$treg,<sym>($at)	(BFD_RELOC_GPREL16)
-	       <op>	$treg+1,<sym>+4($at)	(BFD_RELOC_GPREL16)
-	     */
-	  if (breg == 0)
-	    {
-	      tempreg = mips_gp_register;
-	      used_at = 0;
-	    }
-	  else
-	    {
-	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
-			   AT, breg, mips_gp_register);
-	      tempreg = AT;
-	      used_at = 1;
-	    }
-
-	  /* Itbl support may require additional care here.  */
-	  macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
-		       BFD_RELOC_GPREL16, tempreg);
-	  offset_expr.X_add_number += 4;
-	  /* Itbl support may require additional care here.  */
-	  macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
-		       BFD_RELOC_GPREL16, tempreg);
-	}
       else
 	abort ();
 
@@ -7553,8 +7362,7 @@ macro2 (struct mips_cl_insn *ip)
       if (treg == tempreg)
         return;
       /* Protect second load's delay slot.  */
-      if (!gpr_interlocks)
-	macro_build (NULL, "nop", "");
+      load_delay_nop ();
       move_register (treg, tempreg);
       break;
 
@@ -8862,13 +8670,6 @@ do_msbd:
 		    The .lit4 and .lit8 sections are only used if
 		    permitted by the -G argument.
 
-		    When generating embedded PIC code, we use the
-		    .lit8 section but not the .lit4 section (we can do
-		    .lit4 inline easily; we need to put .lit8
-		    somewhere in the data segment, and using .lit8
-		    permits the linker to eventually combine identical
-		    .lit8 entries).
-
 		    The code below needs to know whether the target register
 		    is 32 or 64 bits wide.  It relies on the fact 'f' and
 		    'F' are used with GPR-based instructions and 'l' and
@@ -8894,9 +8695,7 @@ do_msbd:
 
 		if (*args == 'f'
 		    || (*args == 'l'
-			&& (! USE_GLOBAL_POINTER_OPT
-			    || mips_pic == EMBEDDED_PIC
-			    || g_switch_value < 4
+			&& (g_switch_value < 4
 			    || (temp[0] == 0 && temp[1] == 0)
 			    || (temp[2] == 0 && temp[3] == 0))))
 		  {
@@ -8983,19 +8782,14 @@ do_msbd:
 		      default: /* unused default case avoids warnings.  */
 		      case 'L':
 			newname = RDATA_SECTION_NAME;
-			if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
-			    || mips_pic == EMBEDDED_PIC)
+			if (g_switch_value >= 8)
 			  newname = ".lit8";
 			break;
 		      case 'F':
-			if (mips_pic == EMBEDDED_PIC)
-			  newname = ".lit8";
-			else
-			  newname = RDATA_SECTION_NAME;
+			newname = RDATA_SECTION_NAME;
 			break;
 		      case 'l':
-			assert (!USE_GLOBAL_POINTER_OPT
-				|| g_switch_value >= 4);
+			assert (g_switch_value >= 4);
 			newname = ".lit4";
 			break;
 		      }
@@ -10254,45 +10048,43 @@ struct option md_longopts[] =
 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
   {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
   {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
-#define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
-#define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
-  {"mfix-vr4122-bugs",    no_argument, NULL, OPTION_FIX_VR4122},
-  {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
+#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
+#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
+  {"mfix-vr4120",    no_argument, NULL, OPTION_FIX_VR4120},
+  {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
 
   /* Miscellaneous options.  */
 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
-#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
-  {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
-#define OPTION_TRAP (OPTION_MISC_BASE + 1)
+#define OPTION_TRAP (OPTION_MISC_BASE + 0)
   {"trap", no_argument, NULL, OPTION_TRAP},
   {"no-break", no_argument, NULL, OPTION_TRAP},
-#define OPTION_BREAK (OPTION_MISC_BASE + 2)
+#define OPTION_BREAK (OPTION_MISC_BASE + 1)
   {"break", no_argument, NULL, OPTION_BREAK},
   {"no-trap", no_argument, NULL, OPTION_BREAK},
-#define OPTION_EB (OPTION_MISC_BASE + 3)
+#define OPTION_EB (OPTION_MISC_BASE + 2)
   {"EB", no_argument, NULL, OPTION_EB},
-#define OPTION_EL (OPTION_MISC_BASE + 4)
+#define OPTION_EL (OPTION_MISC_BASE + 3)
   {"EL", no_argument, NULL, OPTION_EL},
-#define OPTION_FP32 (OPTION_MISC_BASE + 5)
+#define OPTION_FP32 (OPTION_MISC_BASE + 4)
   {"mfp32", no_argument, NULL, OPTION_FP32},
-#define OPTION_GP32 (OPTION_MISC_BASE + 6)
+#define OPTION_GP32 (OPTION_MISC_BASE + 5)
   {"mgp32", no_argument, NULL, OPTION_GP32},
-#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
+#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
   {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
-#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
+#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
   {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
-#define OPTION_FP64 (OPTION_MISC_BASE + 9)
+#define OPTION_FP64 (OPTION_MISC_BASE + 8)
   {"mfp64", no_argument, NULL, OPTION_FP64},
-#define OPTION_GP64 (OPTION_MISC_BASE + 10)
+#define OPTION_GP64 (OPTION_MISC_BASE + 9)
   {"mgp64", no_argument, NULL, OPTION_GP64},
-#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
-#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
+#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
+#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
   {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
   {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
 
   /* ELF-specific options.  */
 #ifdef OBJ_ELF
-#define OPTION_ELF_BASE    (OPTION_MISC_BASE + 13)
+#define OPTION_ELF_BASE    (OPTION_MISC_BASE + 12)
 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
   {"KPIC",        no_argument, NULL, OPTION_CALL_SHARED},
   {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
@@ -10489,22 +10281,12 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mips3d = 0;
       break;
 
-    case OPTION_MEMBEDDED_PIC:
-      mips_pic = EMBEDDED_PIC;
-      if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
-	{
-	  as_bad (_("-G may not be used with embedded PIC code"));
-	  return 0;
-	}
-      g_switch_value = 0x7fffffff;
+    case OPTION_FIX_VR4120:
+      mips_fix_vr4120 = 1;
       break;
 
-    case OPTION_FIX_VR4122:
-      mips_fix_4122_bugs = 1;
-      break;
-
-    case OPTION_NO_FIX_VR4122:
-      mips_fix_4122_bugs = 0;
+    case OPTION_NO_FIX_VR4120:
+      mips_fix_vr4120 = 0;
       break;
 
     case OPTION_RELAX_BRANCH:
@@ -10554,14 +10336,9 @@ md_parse_option (int c, char *arg)
 #endif /* OBJ_ELF */
 
     case 'G':
-      if (! USE_GLOBAL_POINTER_OPT)
-	{
-	  as_bad (_("-G is not supported for this configuration"));
-	  return 0;
-	}
-      else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
+      if (mips_pic == SVR4_PIC)
 	{
-	  as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
+	  as_bad (_("-G may not be used with SVR4 PIC code"));
 	  return 0;
 	}
       else
@@ -10962,24 +10739,7 @@ mips_frob_file (void)
     }
 }
 
-/* When generating embedded PIC code we need to use a special
-   relocation to represent the difference of two symbols in the .text
-   section (switch tables use a difference of this sort).  See
-   include/coff/mips.h for details.  This macro checks whether this
-   fixup requires the special reloc.  */
-#define SWITCH_TABLE(fixp) \
-  ((fixp)->fx_r_type == BFD_RELOC_32 \
-   && OUTPUT_FLAVOR != bfd_target_elf_flavour \
-   && (fixp)->fx_addsy != NULL \
-   && (fixp)->fx_subsy != NULL \
-   && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
-   && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
-
-/* When generating embedded PIC code we must keep all PC relative
-   relocations, in case the linker has to relax a call.  We also need
-   to keep relocations for switch table entries.
-
-   We may have combined relocations without symbols in the N32/N64 ABI.
+/* We may have combined relocations without symbols in the N32/N64 ABI.
    We have to prevent gas from dropping them.  */
 
 int
@@ -10995,11 +10755,7 @@ mips_force_relocation (fixS *fixp)
 	  || fixp->fx_r_type == BFD_RELOC_LO16))
     return 1;
 
-  return (mips_pic == EMBEDDED_PIC
-	  && (fixp->fx_pcrel
-	      || SWITCH_TABLE (fixp)
-	      || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
-	      || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
+  return 0;
 }
 
 /* This hook is called before a fix is simplified.  We don't really
@@ -11039,9 +10795,8 @@ mips_validate_fix (struct fix *fixP, asection *seg)
      whole function).  */
 
   if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
-      && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
-	    || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	   && mips_pic != EMBEDDED_PIC)
+      && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
+	   || OUTPUT_FLAVOR == bfd_target_elf_flavour)
 	  || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
       && fixP->fx_addsy)
     {
@@ -11106,7 +10861,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
   buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
 
   /* We are not done if this is a composite relocation to set up gp.  */
-  if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
+  assert (! fixP->fx_pcrel);
+  if (fixP->fx_addsy == NULL
       && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
 	   || (fixP->fx_r_type == BFD_RELOC_64
 	       && (previous_fx_r_type == BFD_RELOC_GPREL32
@@ -11147,9 +10903,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_MIPS_CALL_HI16:
     case BFD_RELOC_MIPS_CALL_LO16:
     case BFD_RELOC_MIPS16_GPREL:
-      if (fixP->fx_pcrel)
-	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("Invalid PC relative reloc"));
+      assert (! fixP->fx_pcrel);
       /* Nothing needed to do. The value comes from the reloc entry */
       break;
 
@@ -11160,44 +10914,10 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       *valP = 0;
       break;
 
-    case BFD_RELOC_PCREL_HI16_S:
-      /* The addend for this is tricky if it is internal, so we just
-	 do everything here rather than in bfd_install_relocation.  */
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
-	break;
-      if (fixP->fx_addsy
-	  && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
-	{
-	  /* For an external symbol adjust by the address to make it
-	     pcrel_offset.  We use the address of the RELLO reloc
-	     which follows this one.  */
-	  *valP += (fixP->fx_next->fx_frag->fr_address
-		    + fixP->fx_next->fx_where);
-	}
-      *valP = ((*valP + 0x8000) >> 16) & 0xffff;
-      if (target_big_endian)
-	buf += 2;
-      md_number_to_chars (buf, *valP, 2);
-      break;
-
-    case BFD_RELOC_PCREL_LO16:
-      /* The addend for this is tricky if it is internal, so we just
-	 do everything here rather than in bfd_install_relocation.  */
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
-	break;
-      if (fixP->fx_addsy
-	  && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
-	*valP += fixP->fx_frag->fr_address + fixP->fx_where;
-      if (target_big_endian)
-	buf += 2;
-      md_number_to_chars (buf, *valP, 2);
-      break;
-
     case BFD_RELOC_64:
       /* This is handled like BFD_RELOC_32, but we output a sign
          extended value if we are only 32 bits.  */
-      if (fixP->fx_done
-	  || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
+      if (fixP->fx_done)
 	{
 	  if (8 <= sizeof (valueT))
 	    md_number_to_chars (buf, *valP, 8);
@@ -11221,11 +10941,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_32:
       /* If we are deleting this reloc entry, we must fill in the
 	 value now.  This can happen if we have a .word which is not
-	 resolved when it appears but is later defined.  We also need
-	 to fill in the value if this is an embedded PIC switch table
-	 entry.  */
-      if (fixP->fx_done
-	  || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
+	 resolved when it appears but is later defined.   */
+      if (fixP->fx_done)
 	md_number_to_chars (buf, *valP, 4);
       break;
 
@@ -11238,6 +10955,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       break;
 
     case BFD_RELOC_LO16:
+      /* FIXME: Now that embedded-PIC is gone, some of this code/comment
+	 may be safe to remove, but if so it's not obvious.  */
       /* When handling an embedded PIC switch statement, we can wind
 	 up deleting a LO16 reloc.  See the 'o' case in mips_ip.  */
       if (fixP->fx_done)
@@ -11508,13 +11227,6 @@ s_change_sec (int sec)
 {
   segT seg;
 
-  /* When generating embedded PIC code, we only use the .text, .lit8,
-     .sdata and .sbss sections.  We change the .data and .rdata
-     pseudo-ops to use .sdata.  */
-  if (mips_pic == EMBEDDED_PIC
-      && (sec == 'd' || sec == 'r'))
-    sec = 's';
-
 #ifdef OBJ_ELF
   /* The ELF backend needs to know that we are changing sections, so
      that .previous works correctly.  We could do something like check
@@ -11540,52 +11252,30 @@ s_change_sec (int sec)
       break;
 
     case 'r':
-      if (USE_GLOBAL_POINTER_OPT)
-	{
-	  seg = subseg_new (RDATA_SECTION_NAME,
-			    (subsegT) get_absolute_expression ());
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    {
-	      bfd_set_section_flags (stdoutput, seg,
-				     (SEC_ALLOC
-				      | SEC_LOAD
-				      | SEC_READONLY
-				      | SEC_RELOC
-				      | SEC_DATA));
-	      if (strcmp (TARGET_OS, "elf") != 0)
-		record_alignment (seg, 4);
-	    }
-	  demand_empty_rest_of_line ();
-	}
-      else
+      seg = subseg_new (RDATA_SECTION_NAME,
+			(subsegT) get_absolute_expression ());
+      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 	{
-	  as_bad (_("No read only data section in this object file format"));
-	  demand_empty_rest_of_line ();
-	  return;
+	  bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
+						  | SEC_READONLY | SEC_RELOC
+						  | SEC_DATA));
+	  if (strcmp (TARGET_OS, "elf") != 0)
+	    record_alignment (seg, 4);
 	}
+      demand_empty_rest_of_line ();
       break;
 
     case 's':
-      if (USE_GLOBAL_POINTER_OPT)
-	{
-	  seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    {
-	      bfd_set_section_flags (stdoutput, seg,
-				     SEC_ALLOC | SEC_LOAD | SEC_RELOC
-				     | SEC_DATA);
-	      if (strcmp (TARGET_OS, "elf") != 0)
-		record_alignment (seg, 4);
-	    }
-	  demand_empty_rest_of_line ();
-	  break;
-	}
-      else
+      seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
+      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 	{
-	  as_bad (_("Global pointers not supported; recompile -G 0"));
-	  demand_empty_rest_of_line ();
-	  return;
+	  bfd_set_section_flags (stdoutput, seg,
+				 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
+	  if (strcmp (TARGET_OS, "elf") != 0)
+	    record_alignment (seg, 4);
 	}
+      demand_empty_rest_of_line ();
+      break;
     }
 
   auto_align = 1;
@@ -11781,7 +11471,7 @@ s_option (int x ATTRIBUTE_UNUSED)
       else
 	as_bad (_(".option pic%d not supported"), i);
 
-      if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
+      if (mips_pic == SVR4_PIC)
 	{
 	  if (g_switch_seen && g_switch_value != 0)
 	    as_warn (_("-G may not be used with SVR4 PIC code"));
@@ -11891,34 +11581,11 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 
       /* Permit the user to change the ISA and architecture on the fly.
 	 Needless to say, misuse can cause serious problems.  */
-      if (strcmp (name, "mips0") == 0)
+      if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
 	{
 	  reset = 1;
 	  mips_opts.isa = file_mips_isa;
-	}
-      else if (strcmp (name, "mips1") == 0)
-	mips_opts.isa = ISA_MIPS1;
-      else if (strcmp (name, "mips2") == 0)
-	mips_opts.isa = ISA_MIPS2;
-      else if (strcmp (name, "mips3") == 0)
-	mips_opts.isa = ISA_MIPS3;
-      else if (strcmp (name, "mips4") == 0)
-	mips_opts.isa = ISA_MIPS4;
-      else if (strcmp (name, "mips5") == 0)
-	mips_opts.isa = ISA_MIPS5;
-      else if (strcmp (name, "mips32") == 0)
-	mips_opts.isa = ISA_MIPS32;
-      else if (strcmp (name, "mips32r2") == 0)
-	mips_opts.isa = ISA_MIPS32R2;
-      else if (strcmp (name, "mips64") == 0)
-	mips_opts.isa = ISA_MIPS64;
-      else if (strcmp (name, "mips64r2") == 0)
-	mips_opts.isa = ISA_MIPS64R2;
-      else if (strcmp (name, "arch=default") == 0)
-	{
-	  reset = 1;
 	  mips_opts.arch = file_mips_arch;
-	  mips_opts.isa = file_mips_isa;
 	}
       else if (strncmp (name, "arch=", 5) == 0)
 	{
@@ -11933,8 +11600,21 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	      mips_opts.isa = p->isa;
 	    }
 	}
+      else if (strncmp (name, "mips", 4) == 0)
+	{
+	  const struct mips_cpu_info *p;
+
+	  p = mips_parse_cpu("internal use", name);
+	  if (!p)
+	    as_bad (_("unknown ISA level %s"), name + 4);
+	  else
+	    {
+	      mips_opts.arch = p->cpu;
+	      mips_opts.isa = p->isa;
+	    }
+	}
       else
-	as_bad (_("unknown ISA level %s"), name + 4);
+	as_bad (_("unknown ISA or architecture %s"), name);
 
       switch (mips_opts.isa)
 	{
@@ -12022,12 +11702,11 @@ s_abicalls (int ignore ATTRIBUTE_UNUSED)
 {
   mips_pic = SVR4_PIC;
   mips_abicalls = TRUE;
-  if (USE_GLOBAL_POINTER_OPT)
-    {
-      if (g_switch_seen && g_switch_value != 0)
-	as_warn (_("-G may not be used with SVR4 PIC code"));
-      g_switch_value = 0;
-    }
+
+  if (g_switch_seen && g_switch_value != 0)
+    as_warn (_("-G may not be used with SVR4 PIC code"));
+  g_switch_value = 0;
+
   bfd_set_gp_size (stdoutput, 0);
   demand_empty_rest_of_line ();
 }
@@ -12584,7 +12263,7 @@ nopic_need_relax (symbolS *sym, int before_relaxing)
   if (sym == 0)
     return 0;
 
-  if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
+  if (g_switch_value > 0)
     {
       const char *symname;
       int change;
@@ -12691,9 +12370,7 @@ pic_need_relax (symbolS *sym, asection *segtype)
 #ifdef OBJ_ELF
 	  /* A global or weak symbol is treated as external.  */
 	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
-	      || (! S_IS_WEAK (sym)
-		  && (! S_IS_EXTERNAL (sym)
-		      || mips_pic == EMBEDDED_PIC)))
+	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
 #endif
 	  );
 }
@@ -13046,60 +12723,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
-  if (mips_pic == EMBEDDED_PIC
-      && SWITCH_TABLE (fixp))
-    {
-      /* For a switch table entry we use a special reloc.  The addend
-	 is actually the difference between the reloc address and the
-	 subtrahend.  */
-      reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
-      if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
-	as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
-      fixp->fx_r_type = BFD_RELOC_GPREL32;
-    }
-  else if (fixp->fx_pcrel)
-    {
-      bfd_vma pcrel_address;
-
-      /* Set PCREL_ADDRESS to this relocation's "PC".  The PC for high
-	 high-part relocs is the address of the low-part reloc.  */
-      if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
-	{
-	  assert (fixp->fx_next != NULL
-		  && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
-	  pcrel_address = (fixp->fx_next->fx_where
-			   + fixp->fx_next->fx_frag->fr_address);
-	}
-      else
-	pcrel_address = reloc->address;
-
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	{
-	  /* At this point, fx_addnumber is "symbol offset - pcrel_address".
-	     Relocations want only the symbol offset.  */
-	  reloc->addend = fixp->fx_addnumber + pcrel_address;
-	}
-      else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
-	       || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
-	{
-	  /* We use a special addend for an internal RELLO or RELHI reloc.  */
-	  if (symbol_section_p (fixp->fx_addsy))
-	    reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
-	  else
-	    reloc->addend = fixp->fx_addnumber + pcrel_address;
-	}
-      else
-	{
-	  if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
-	    /* A gruesome hack which is a result of the gruesome gas reloc
-	       handling.  */
-	    reloc->addend = pcrel_address;
-	  else
-	    reloc->addend = -pcrel_address;
-	}
-    }
-  else
-    reloc->addend = fixp->fx_addnumber;
+  assert (! fixp->fx_pcrel);
+  reloc->addend = fixp->fx_addnumber;
 
   /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
      entry to be used in the relocation's section offset.  */
@@ -13109,49 +12734,16 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
       reloc->addend = 0;
     }
 
-  /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
-     fixup_segment converted a non-PC relative reloc into a PC
-     relative reloc.  In such a case, we need to convert the reloc
-     code.  */
   code = fixp->fx_r_type;
-  if (fixp->fx_pcrel)
-    {
-      switch (code)
-	{
-	case BFD_RELOC_8:
-	  code = BFD_RELOC_8_PCREL;
-	  break;
-	case BFD_RELOC_16:
-	  code = BFD_RELOC_16_PCREL;
-	  break;
-	case BFD_RELOC_32:
-	  code = BFD_RELOC_32_PCREL;
-	  break;
-	case BFD_RELOC_64:
-	  code = BFD_RELOC_64_PCREL;
-	  break;
-	case BFD_RELOC_8_PCREL:
-	case BFD_RELOC_16_PCREL:
-	case BFD_RELOC_32_PCREL:
-	case BFD_RELOC_64_PCREL:
-	case BFD_RELOC_16_PCREL_S2:
-	case BFD_RELOC_PCREL_HI16_S:
-	case BFD_RELOC_PCREL_LO16:
-	  break;
-	default:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("Cannot make %s relocation PC relative"),
-			bfd_get_reloc_code_name (code));
-	}
-    }
 
-  /* To support a PC relative reloc when generating embedded PIC code
-     for ECOFF, we use a Cygnus extension.  We check for that here to
-     make sure that we don't let such a reloc escape normally.  */
+  /* To support a PC relative reloc, we used a Cygnus extension.
+     We check for that here to make sure that we don't let such a
+     reloc escape normally.  (FIXME: This was formerly used by
+     embedded-PIC support, but is now used by branch handling in
+     general.  That probably should be fixed.)  */
   if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
        || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-      && code == BFD_RELOC_16_PCREL_S2
-      && mips_pic != EMBEDDED_PIC)
+      && code == BFD_RELOC_16_PCREL_S2)
     reloc->howto = NULL;
   else
     reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
@@ -14331,7 +13923,6 @@ md_show_usage (FILE *stream)
 
   fprintf (stream, _("\
 MIPS options:\n\
--membedded-pic		generate embedded position independent code\n\
 -EB			generate big endian output\n\
 -EL			generate little endian output\n\
 -g, -g2			do not remove unneeded NOPs or swap branches\n\
@@ -14373,6 +13964,7 @@ MIPS options:\n\
 -mips16			generate mips16 instructions\n\
 -no-mips16		do not generate mips16 instructions\n"));
   fprintf (stream, _("\
+-mfix-vr4120		work around certain VR4120 errata\n\
 -mgp32			use 32-bit GPRs, regardless of the chosen ISA\n\
 -mfp32			use 32-bit FPRs, regardless of the chosen ISA\n\
 -O0			remove unneeded NOPs, do not swap branches\n\
@@ -14425,10 +14017,6 @@ mips_dwarf2_addr_size (void)
 {
   if (mips_abi == N64_ABI)
     return 8;
-  /* GCC for 64-bit targets turns on mlong64 giving
-     us 64-bit addresses.  */
-  else if (mips_abi == EABI_ABI && !file_mips_gp32)
-    return 8;
   else
     return 4;
 }
diff --git a/gas/config/tc-mips.h b/gas/config/tc-mips.h
index 46a765369a1..8d0106a7c1e 100644
--- a/gas/config/tc-mips.h
+++ b/gas/config/tc-mips.h
@@ -58,10 +58,6 @@ extern void mips_handle_align (struct frag *);
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2)
 
-/* We permit PC relative difference expressions when generating
-   embedded PIC code.  */
-#define DIFF_EXPR_OK
-
 /* Tell assembler that we have an itbl_mips.h header file to include.  */
 #define HAVE_ITBL_CPU
 
@@ -79,12 +75,6 @@ enum mips_pic_level
 
   /* Generate PIC code as in the SVR4 MIPS ABI.  */
   SVR4_PIC,
-
-  /* Generate PIC code without using a global offset table: the data
-     segment has a maximum size of 64K, all data references are off
-     the $gp register, and all text references are PC relative.  This
-     is used on some embedded systems.  */
-  EMBEDDED_PIC
 };
 
 extern enum mips_pic_level mips_pic;
@@ -129,14 +119,12 @@ extern int mips_fix_adjustable (struct fix *);
 /* Values passed to md_apply_fix3 don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-/* Global syms must not be resolved, to support ELF shared libraries.
-   When generating embedded code, we don't have shared libs.  */
+/* Global syms must not be resolved, to support ELF shared libraries.  */
 #define EXTERN_FORCE_RELOC			\
-  (OUTPUT_FLAVOR == bfd_target_elf_flavour	\
-   && mips_pic != EMBEDDED_PIC)
+  (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 
-/* When generating embedded PIC code we must keep PC relative
-   relocations.  */
+/* When generating NEWABI code, we may need to have to keep combined
+   relocations which don't have symbols.  */
 #define TC_FORCE_RELOCATION(FIX) mips_force_relocation (FIX)
 extern int mips_force_relocation (struct fix *);
 
@@ -167,10 +155,6 @@ extern void mips_elf_final_processing (void);
 extern void md_mips_end (void);
 #define md_end()	md_mips_end()
 
-#define USE_GLOBAL_POINTER_OPT	(OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
-				 || OUTPUT_FLAVOR == bfd_target_coff_flavour \
-				 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-
 extern void mips_pop_insert (void);
 #define md_pop_insert()		mips_pop_insert()
 
@@ -183,6 +167,7 @@ extern void mips_enable_auto_align (void);
 extern enum dwarf2_format mips_dwarf2_format (void);
 #define DWARF2_FORMAT() mips_dwarf2_format ()
 
+extern int mips_dwarf2_addr_size (void);
 #define DWARF2_ADDR_SIZE(bfd) mips_dwarf2_addr_size ()
 
 #endif /* TC_MIPS */
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 86daea0a369..66366a57d23 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1,6 +1,6 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -183,7 +183,7 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-/* '+' and '-' can be used as postfix predicate predictors for conditional 
+/* '+' and '-' can be used as postfix predicate predictors for conditional
    branches.  So they need to be accepted as symbol characters.  */
 const char ppc_symbol_chars[] = "+-";
 
@@ -1493,8 +1493,10 @@ ppc_elf_suffix (str_p, exp_p)
 {
   struct map_bfd {
     char *string;
-    int length;
-    int reloc;
+    unsigned int length : 8;
+    unsigned int valid32 : 1;
+    unsigned int valid64 : 1;
+    unsigned int reloc;
   };
 
   char ident[20];
@@ -1504,97 +1506,97 @@ ppc_elf_suffix (str_p, exp_p)
   int len;
   const struct map_bfd *ptr;
 
-#define MAP(str,reloc) { str, sizeof (str)-1, reloc }
+#define MAP(str, reloc)   { str, sizeof (str) - 1, 1, 1, reloc }
+#define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
+#define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
 
   static const struct map_bfd mapping[] = {
-    MAP ("l",			(int) BFD_RELOC_LO16),
-    MAP ("h",			(int) BFD_RELOC_HI16),
-    MAP ("ha",			(int) BFD_RELOC_HI16_S),
-    MAP ("brtaken",		(int) BFD_RELOC_PPC_B16_BRTAKEN),
-    MAP ("brntaken",		(int) BFD_RELOC_PPC_B16_BRNTAKEN),
-    MAP ("got",			(int) BFD_RELOC_16_GOTOFF),
-    MAP ("got@l",		(int) BFD_RELOC_LO16_GOTOFF),
-    MAP ("got@h",		(int) BFD_RELOC_HI16_GOTOFF),
-    MAP ("got@ha",		(int) BFD_RELOC_HI16_S_GOTOFF),
-    MAP ("fixup",		(int) BFD_RELOC_CTOR),
-    MAP ("plt",			(int) BFD_RELOC_24_PLT_PCREL),
-    MAP ("pltrel24",		(int) BFD_RELOC_24_PLT_PCREL),
-    MAP ("copy",		(int) BFD_RELOC_PPC_COPY),
-    MAP ("globdat",		(int) BFD_RELOC_PPC_GLOB_DAT),
-    MAP ("local24pc",		(int) BFD_RELOC_PPC_LOCAL24PC),
-    MAP ("local",		(int) BFD_RELOC_PPC_LOCAL24PC),
-    MAP ("pltrel",		(int) BFD_RELOC_32_PLT_PCREL),
-    MAP ("plt@l",		(int) BFD_RELOC_LO16_PLTOFF),
-    MAP ("plt@h",		(int) BFD_RELOC_HI16_PLTOFF),
-    MAP ("plt@ha",		(int) BFD_RELOC_HI16_S_PLTOFF),
-    MAP ("sdarel",		(int) BFD_RELOC_GPREL16),
-    MAP ("sectoff",		(int) BFD_RELOC_16_BASEREL),
-    MAP ("sectoff@l",		(int) BFD_RELOC_LO16_BASEREL),
-    MAP ("sectoff@h",		(int) BFD_RELOC_HI16_BASEREL),
-    MAP ("sectoff@ha",		(int) BFD_RELOC_HI16_S_BASEREL),
-    MAP ("naddr",		(int) BFD_RELOC_PPC_EMB_NADDR32),
-    MAP ("naddr16",		(int) BFD_RELOC_PPC_EMB_NADDR16),
-    MAP ("naddr@l",		(int) BFD_RELOC_PPC_EMB_NADDR16_LO),
-    MAP ("naddr@h",		(int) BFD_RELOC_PPC_EMB_NADDR16_HI),
-    MAP ("naddr@ha",		(int) BFD_RELOC_PPC_EMB_NADDR16_HA),
-    MAP ("sdai16",		(int) BFD_RELOC_PPC_EMB_SDAI16),
-    MAP ("sda2rel",		(int) BFD_RELOC_PPC_EMB_SDA2REL),
-    MAP ("sda2i16",		(int) BFD_RELOC_PPC_EMB_SDA2I16),
-    MAP ("sda21",		(int) BFD_RELOC_PPC_EMB_SDA21),
-    MAP ("mrkref",		(int) BFD_RELOC_PPC_EMB_MRKREF),
-    MAP ("relsect",		(int) BFD_RELOC_PPC_EMB_RELSEC16),
-    MAP ("relsect@l",		(int) BFD_RELOC_PPC_EMB_RELST_LO),
-    MAP ("relsect@h",		(int) BFD_RELOC_PPC_EMB_RELST_HI),
-    MAP ("relsect@ha",		(int) BFD_RELOC_PPC_EMB_RELST_HA),
-    MAP ("bitfld",		(int) BFD_RELOC_PPC_EMB_BIT_FLD),
-    MAP ("relsda",		(int) BFD_RELOC_PPC_EMB_RELSDA),
-    MAP ("xgot",		(int) BFD_RELOC_PPC_TOC16),
-    MAP ("tls",			(int) BFD_RELOC_PPC_TLS),
-    MAP ("dtpmod",		(int) BFD_RELOC_PPC_DTPMOD),
-    MAP ("dtprel",		(int) BFD_RELOC_PPC_DTPREL),
-    MAP ("dtprel@l",		(int) BFD_RELOC_PPC_DTPREL16_LO),
-    MAP ("dtprel@h",		(int) BFD_RELOC_PPC_DTPREL16_HI),
-    MAP ("dtprel@ha",		(int) BFD_RELOC_PPC_DTPREL16_HA),
-    MAP ("tprel",		(int) BFD_RELOC_PPC_TPREL),
-    MAP ("tprel@l",		(int) BFD_RELOC_PPC_TPREL16_LO),
-    MAP ("tprel@h",		(int) BFD_RELOC_PPC_TPREL16_HI),
-    MAP ("tprel@ha",		(int) BFD_RELOC_PPC_TPREL16_HA),
-    MAP ("got@tlsgd",		(int) BFD_RELOC_PPC_GOT_TLSGD16),
-    MAP ("got@tlsgd@l",		(int) BFD_RELOC_PPC_GOT_TLSGD16_LO),
-    MAP ("got@tlsgd@h",		(int) BFD_RELOC_PPC_GOT_TLSGD16_HI),
-    MAP ("got@tlsgd@ha",	(int) BFD_RELOC_PPC_GOT_TLSGD16_HA),
-    MAP ("got@tlsld",		(int) BFD_RELOC_PPC_GOT_TLSLD16),
-    MAP ("got@tlsld@l",		(int) BFD_RELOC_PPC_GOT_TLSLD16_LO),
-    MAP ("got@tlsld@h",		(int) BFD_RELOC_PPC_GOT_TLSLD16_HI),
-    MAP ("got@tlsld@ha",	(int) BFD_RELOC_PPC_GOT_TLSLD16_HA),
-    MAP ("got@dtprel",		(int) BFD_RELOC_PPC_GOT_DTPREL16),
-    MAP ("got@dtprel@l",	(int) BFD_RELOC_PPC_GOT_DTPREL16_LO),
-    MAP ("got@dtprel@h",	(int) BFD_RELOC_PPC_GOT_DTPREL16_HI),
-    MAP ("got@dtprel@ha",	(int) BFD_RELOC_PPC_GOT_DTPREL16_HA),
-    MAP ("got@tprel",		(int) BFD_RELOC_PPC_GOT_TPREL16),
-    MAP ("got@tprel@l",		(int) BFD_RELOC_PPC_GOT_TPREL16_LO),
-    MAP ("got@tprel@h",		(int) BFD_RELOC_PPC_GOT_TPREL16_HI),
-    MAP ("got@tprel@ha",	(int) BFD_RELOC_PPC_GOT_TPREL16_HA),
-    /* The following are only valid for ppc64.  Negative values are
-       used instead of a flag.  */
-    MAP ("higher",		- (int) BFD_RELOC_PPC64_HIGHER),
-    MAP ("highera",		- (int) BFD_RELOC_PPC64_HIGHER_S),
-    MAP ("highest",		- (int) BFD_RELOC_PPC64_HIGHEST),
-    MAP ("highesta",		- (int) BFD_RELOC_PPC64_HIGHEST_S),
-    MAP ("tocbase",		- (int) BFD_RELOC_PPC64_TOC),
-    MAP ("toc",			- (int) BFD_RELOC_PPC_TOC16),
-    MAP ("toc@l",		- (int) BFD_RELOC_PPC64_TOC16_LO),
-    MAP ("toc@h",		- (int) BFD_RELOC_PPC64_TOC16_HI),
-    MAP ("toc@ha",		- (int) BFD_RELOC_PPC64_TOC16_HA),
-    MAP ("dtprel@higher",	- (int) BFD_RELOC_PPC64_DTPREL16_HIGHER),
-    MAP ("dtprel@highera",	- (int) BFD_RELOC_PPC64_DTPREL16_HIGHERA),
-    MAP ("dtprel@highest",	- (int) BFD_RELOC_PPC64_DTPREL16_HIGHEST),
-    MAP ("dtprel@highesta",	- (int) BFD_RELOC_PPC64_DTPREL16_HIGHESTA),
-    MAP ("tprel@higher",	- (int) BFD_RELOC_PPC64_TPREL16_HIGHER),
-    MAP ("tprel@highera",	- (int) BFD_RELOC_PPC64_TPREL16_HIGHERA),
-    MAP ("tprel@highest",	- (int) BFD_RELOC_PPC64_TPREL16_HIGHEST),
-    MAP ("tprel@highesta",	- (int) BFD_RELOC_PPC64_TPREL16_HIGHESTA),
-    { (char *) 0, 0,		(int) BFD_RELOC_UNUSED }
+    MAP ("l",			BFD_RELOC_LO16),
+    MAP ("h",			BFD_RELOC_HI16),
+    MAP ("ha",			BFD_RELOC_HI16_S),
+    MAP ("brtaken",		BFD_RELOC_PPC_B16_BRTAKEN),
+    MAP ("brntaken",		BFD_RELOC_PPC_B16_BRNTAKEN),
+    MAP ("got",			BFD_RELOC_16_GOTOFF),
+    MAP ("got@l",		BFD_RELOC_LO16_GOTOFF),
+    MAP ("got@h",		BFD_RELOC_HI16_GOTOFF),
+    MAP ("got@ha",		BFD_RELOC_HI16_S_GOTOFF),
+    MAP ("plt@l",		BFD_RELOC_LO16_PLTOFF),
+    MAP ("plt@h",		BFD_RELOC_HI16_PLTOFF),
+    MAP ("plt@ha",		BFD_RELOC_HI16_S_PLTOFF),
+    MAP ("copy",		BFD_RELOC_PPC_COPY),
+    MAP ("globdat",		BFD_RELOC_PPC_GLOB_DAT),
+    MAP ("sectoff",		BFD_RELOC_16_BASEREL),
+    MAP ("sectoff@l",		BFD_RELOC_LO16_BASEREL),
+    MAP ("sectoff@h",		BFD_RELOC_HI16_BASEREL),
+    MAP ("sectoff@ha",		BFD_RELOC_HI16_S_BASEREL),
+    MAP ("tls",			BFD_RELOC_PPC_TLS),
+    MAP ("dtpmod",		BFD_RELOC_PPC_DTPMOD),
+    MAP ("dtprel",		BFD_RELOC_PPC_DTPREL),
+    MAP ("dtprel@l",		BFD_RELOC_PPC_DTPREL16_LO),
+    MAP ("dtprel@h",		BFD_RELOC_PPC_DTPREL16_HI),
+    MAP ("dtprel@ha",		BFD_RELOC_PPC_DTPREL16_HA),
+    MAP ("tprel",		BFD_RELOC_PPC_TPREL),
+    MAP ("tprel@l",		BFD_RELOC_PPC_TPREL16_LO),
+    MAP ("tprel@h",		BFD_RELOC_PPC_TPREL16_HI),
+    MAP ("tprel@ha",		BFD_RELOC_PPC_TPREL16_HA),
+    MAP ("got@tlsgd",		BFD_RELOC_PPC_GOT_TLSGD16),
+    MAP ("got@tlsgd@l",		BFD_RELOC_PPC_GOT_TLSGD16_LO),
+    MAP ("got@tlsgd@h",		BFD_RELOC_PPC_GOT_TLSGD16_HI),
+    MAP ("got@tlsgd@ha",	BFD_RELOC_PPC_GOT_TLSGD16_HA),
+    MAP ("got@tlsld",		BFD_RELOC_PPC_GOT_TLSLD16),
+    MAP ("got@tlsld@l",		BFD_RELOC_PPC_GOT_TLSLD16_LO),
+    MAP ("got@tlsld@h",		BFD_RELOC_PPC_GOT_TLSLD16_HI),
+    MAP ("got@tlsld@ha",	BFD_RELOC_PPC_GOT_TLSLD16_HA),
+    MAP ("got@dtprel",		BFD_RELOC_PPC_GOT_DTPREL16),
+    MAP ("got@dtprel@l",	BFD_RELOC_PPC_GOT_DTPREL16_LO),
+    MAP ("got@dtprel@h",	BFD_RELOC_PPC_GOT_DTPREL16_HI),
+    MAP ("got@dtprel@ha",	BFD_RELOC_PPC_GOT_DTPREL16_HA),
+    MAP ("got@tprel",		BFD_RELOC_PPC_GOT_TPREL16),
+    MAP ("got@tprel@l",		BFD_RELOC_PPC_GOT_TPREL16_LO),
+    MAP ("got@tprel@h",		BFD_RELOC_PPC_GOT_TPREL16_HI),
+    MAP ("got@tprel@ha",	BFD_RELOC_PPC_GOT_TPREL16_HA),
+    MAP32 ("fixup",		BFD_RELOC_CTOR),
+    MAP32 ("plt",		BFD_RELOC_24_PLT_PCREL),
+    MAP32 ("pltrel24",		BFD_RELOC_24_PLT_PCREL),
+    MAP32 ("local24pc",		BFD_RELOC_PPC_LOCAL24PC),
+    MAP32 ("local",		BFD_RELOC_PPC_LOCAL24PC),
+    MAP32 ("pltrel",		BFD_RELOC_32_PLT_PCREL),
+    MAP32 ("sdarel",		BFD_RELOC_GPREL16),
+    MAP32 ("naddr",		BFD_RELOC_PPC_EMB_NADDR32),
+    MAP32 ("naddr16",		BFD_RELOC_PPC_EMB_NADDR16),
+    MAP32 ("naddr@l",		BFD_RELOC_PPC_EMB_NADDR16_LO),
+    MAP32 ("naddr@h",		BFD_RELOC_PPC_EMB_NADDR16_HI),
+    MAP32 ("naddr@ha",		BFD_RELOC_PPC_EMB_NADDR16_HA),
+    MAP32 ("sdai16",		BFD_RELOC_PPC_EMB_SDAI16),
+    MAP32 ("sda2rel",		BFD_RELOC_PPC_EMB_SDA2REL),
+    MAP32 ("sda2i16",		BFD_RELOC_PPC_EMB_SDA2I16),
+    MAP32 ("sda21",		BFD_RELOC_PPC_EMB_SDA21),
+    MAP32 ("mrkref",		BFD_RELOC_PPC_EMB_MRKREF),
+    MAP32 ("relsect",		BFD_RELOC_PPC_EMB_RELSEC16),
+    MAP32 ("relsect@l",		BFD_RELOC_PPC_EMB_RELST_LO),
+    MAP32 ("relsect@h",		BFD_RELOC_PPC_EMB_RELST_HI),
+    MAP32 ("relsect@ha",	BFD_RELOC_PPC_EMB_RELST_HA),
+    MAP32 ("bitfld",		BFD_RELOC_PPC_EMB_BIT_FLD),
+    MAP32 ("relsda",		BFD_RELOC_PPC_EMB_RELSDA),
+    MAP32 ("xgot",		BFD_RELOC_PPC_TOC16),
+    MAP64 ("higher",		BFD_RELOC_PPC64_HIGHER),
+    MAP64 ("highera",		BFD_RELOC_PPC64_HIGHER_S),
+    MAP64 ("highest",		BFD_RELOC_PPC64_HIGHEST),
+    MAP64 ("highesta",		BFD_RELOC_PPC64_HIGHEST_S),
+    MAP64 ("tocbase",		BFD_RELOC_PPC64_TOC),
+    MAP64 ("toc",		BFD_RELOC_PPC_TOC16),
+    MAP64 ("toc@l",		BFD_RELOC_PPC64_TOC16_LO),
+    MAP64 ("toc@h",		BFD_RELOC_PPC64_TOC16_HI),
+    MAP64 ("toc@ha",		BFD_RELOC_PPC64_TOC16_HA),
+    MAP64 ("dtprel@higher",	BFD_RELOC_PPC64_DTPREL16_HIGHER),
+    MAP64 ("dtprel@highera",	BFD_RELOC_PPC64_DTPREL16_HIGHERA),
+    MAP64 ("dtprel@highest",	BFD_RELOC_PPC64_DTPREL16_HIGHEST),
+    MAP64 ("dtprel@highesta",	BFD_RELOC_PPC64_DTPREL16_HIGHESTA),
+    MAP64 ("tprel@higher",	BFD_RELOC_PPC64_TPREL16_HIGHER),
+    MAP64 ("tprel@highera",	BFD_RELOC_PPC64_TPREL16_HIGHERA),
+    MAP64 ("tprel@highest",	BFD_RELOC_PPC64_TPREL16_HIGHEST),
+    MAP64 ("tprel@highesta",	BFD_RELOC_PPC64_TPREL16_HIGHESTA),
+    { (char *) 0, 0, 0, 0,	BFD_RELOC_UNUSED }
   };
 
   if (*str++ != '@')
@@ -1615,17 +1617,11 @@ ppc_elf_suffix (str_p, exp_p)
   for (ptr = &mapping[0]; ptr->length > 0; ptr++)
     if (ch == ptr->string[0]
 	&& len == ptr->length
-	&& memcmp (ident, ptr->string, ptr->length) == 0)
+	&& memcmp (ident, ptr->string, ptr->length) == 0
+	&& (ppc_obj64 ? ptr->valid64 : ptr->valid32))
       {
 	int reloc = ptr->reloc;
 
-	if (reloc < 0)
-	  {
-	    if (!ppc_obj64)
-	      return BFD_RELOC_UNUSED;
-	    reloc = -reloc;
-	  }
-
 	if (!ppc_obj64)
 	  if (exp_p->X_add_number != 0
 	      && (reloc == (int) BFD_RELOC_16_GOTOFF
@@ -5901,7 +5897,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  if (fixP->fx_pcrel)
 	    {
 	      /* This can occur if there is a bug in the input assembler, eg:
-	         ".byte <undefined_symbol> - ."  */
+		 ".byte <undefined_symbol> - ."  */
 	      if (fixP->fx_addsy)
 		as_bad (_("Unable to handle reference to symbol %s"),
 			S_GET_NAME (fixP->fx_addsy));
@@ -6052,15 +6048,15 @@ tc_ppc_regname_to_dw2regnum (const char *regname)
       if (p == q || *q || regnum >= 32)
 	return -1;
       if (regname[0] == 'f')
-        regnum += 32;
+	regnum += 32;
       else if (regname[0] == 'v')
-        regnum += 77;
+	regnum += 77;
     }
   else if (regname[0] == 'c' && regname[1] == 'r')
     {
       p = regname + 2 + (regname[2] == '.');
       if (p[0] < '0' || p[0] > '7' || p[1])
-        return -1;
+	return -1;
       regnum = p[0] - '0' + 68;
     }
   return regnum;
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index ef51bca4e56..c450eaeea75 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -1614,9 +1614,15 @@ s390_insn (ignore)
   expression (&exp);
   if (exp.X_op == O_constant)
     {
-      if (   (opformat->oplen == 6 && exp.X_op > 0 && exp.X_op < (1ULL << 48))
-	  || (opformat->oplen == 4 && exp.X_op > 0 && exp.X_op < (1ULL << 32))
-	  || (opformat->oplen == 2 && exp.X_op > 0 && exp.X_op < (1ULL << 16)))
+      if (   (   opformat->oplen == 6
+	      && exp.X_add_number >= 0
+	      && (addressT) exp.X_add_number < (1ULL << 48))
+	  || (   opformat->oplen == 4
+	      && exp.X_add_number >= 0
+	      && (addressT) exp.X_add_number < (1ULL << 32))
+	  || (   opformat->oplen == 2
+	      && exp.X_add_number >= 0
+	      && (addressT) exp.X_add_number < (1ULL << 16)))
 	md_number_to_chars (insn, exp.X_add_number, opformat->oplen);
       else
 	as_bad (_("Invalid .insn format\n"));
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index 45698d53cc2..04f06ff7e1f 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -1,6 +1,6 @@
 /* tc-sh.c -- Assemble code for the Renesas / SuperH SH
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+   2003, 2004  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -132,6 +132,10 @@ int sh_relax;		/* set if -relax seen */
 
 int sh_small;
 
+/* Flag to generate relocations against symbol values for local symbols.  */
+
+static int dont_adjust_reloc_32;
+
 /* preset architecture set, if given; zero otherwise.  */
 
 static int preset_target_arch;
@@ -1632,7 +1636,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1640,7 +1644,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1648,7 +1652,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1656,7 +1660,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1664,7 +1668,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1672,7 +1676,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1680,7 +1684,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1689,7 +1693,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1698,7 +1702,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1707,7 +1711,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1715,7 +1719,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1723,7 +1727,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_PMOD_N:
 	      if (user->type != AY_PMOD_N)
 		goto fail;
@@ -1740,7 +1744,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AYX_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1749,7 +1753,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AYX_PMOD_N:
 	      if (user->type != AY_PMOD_N)
 		goto fail;
@@ -2143,6 +2147,7 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
 	  switch (i)
 	    {
 	    case REG_N:
+	    case REG_N_D:
 	      nbuf[index] = reg_n;
 	      break;
 	    case REG_M:
@@ -2159,6 +2164,9 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
 	    case REG_B:
 	      nbuf[index] = reg_b | 0x08;
 	      break;
+	    case REG_N_B01:
+	      nbuf[index] = reg_n | 0x01;
+	      break;
 	    case IMM0_4BY4:
 	      insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
 	      break;
@@ -2584,6 +2592,7 @@ md_assemble (char *str)
   sh_operand_info operand[3];
   sh_opcode_info *opcode;
   unsigned int size = 0;
+  char *initial_str = str;
 
 #ifdef HAVE_SH64
   if (sh64_isa_mode == sh64_isa_shmedia)
@@ -2610,7 +2619,45 @@ md_assemble (char *str)
 
   if (opcode == NULL)
     {
-      as_bad (_("unknown opcode"));
+      /* The opcode is not in the hash table.
+	 This means we definately have an assembly failure,
+	 but the instruction may be valid in another CPU variant.
+	 In this case emit something better than 'unknown opcode'.
+	 Search the full table in sh-opc.h to check. */
+
+      char *name = initial_str;
+      int name_length = 0;
+      const sh_opcode_info *op;
+      int found = 0;
+
+      /* identify opcode in string */
+      while (isspace (*name))
+	{
+	  name++;
+	}
+      while (!isspace (name[name_length]))
+	{
+	  name_length++;
+	}
+
+      /* search for opcode in full list */
+      for (op = sh_table; op->name; op++)
+	{
+	  if (strncasecmp (op->name, name, name_length) == 0)
+	    {
+	      found = 1;
+	      break;
+	    }
+	}
+
+      if ( found )
+	{
+	  as_bad (_("opcode not valid for this cpu variant"));
+	}
+      else
+	{
+	  as_bad (_("unknown opcode"));
+	}
       return;
     }
 
@@ -2840,6 +2887,7 @@ struct option md_longopts[] =
 #define OPTION_SMALL (OPTION_LITTLE + 1)
 #define OPTION_DSP (OPTION_SMALL + 1)
 #define OPTION_ISA                    (OPTION_DSP + 1)
+#define OPTION_RENESAS (OPTION_ISA + 1)
 
   {"relax", no_argument, NULL, OPTION_RELAX},
   {"big", no_argument, NULL, OPTION_BIG},
@@ -2847,8 +2895,10 @@ struct option md_longopts[] =
   {"small", no_argument, NULL, OPTION_SMALL},
   {"dsp", no_argument, NULL, OPTION_DSP},
   {"isa",                    required_argument, NULL, OPTION_ISA},
+  {"renesas", no_argument, NULL, OPTION_RENESAS},
+
 #ifdef HAVE_SH64
-#define OPTION_ABI                    (OPTION_ISA + 1)
+#define OPTION_ABI                    (OPTION_RENESAS + 1)
 #define OPTION_NO_MIX                 (OPTION_ABI + 1)
 #define OPTION_SHCOMPACT_CONST_CRANGE (OPTION_NO_MIX + 1)
 #define OPTION_NO_EXPAND              (OPTION_SHCOMPACT_CONST_CRANGE + 1)
@@ -2889,9 +2939,17 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
       preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
       break;
 
+    case OPTION_RENESAS:
+      dont_adjust_reloc_32 = 1;
+      break;
+
     case OPTION_ISA:
       if (strcasecmp (arg, "sh4") == 0)
 	preset_target_arch = arch_sh4;
+      else if (strcasecmp (arg, "sh4-nofpu") == 0)
+	preset_target_arch = arch_sh4_nofpu;
+      else if (strcasecmp (arg, "sh4-nommu-nofpu") == 0)
+	preset_target_arch = arch_sh4_nommu_nofpu;
       else if (strcasecmp (arg, "sh4a") == 0)
 	preset_target_arch = arch_sh4a;
       else if (strcasecmp (arg, "dsp") == 0)
@@ -2972,18 +3030,23 @@ SH options:\n\
 -little			generate little endian code\n\
 -big			generate big endian code\n\
 -relax			alter jump instructions for long displacements\n\
+-renesas		disable optimization with section symbol for\n\
+			compatibility with Renesas assembler.\n\
 -small			align sections to 4 byte boundaries, not 16\n\
--dsp			enable sh-dsp insns, and disable floating-point ISAs.\n"));
-#ifdef HAVE_SH64
-  fprintf (stream, _("\
+-dsp			enable sh-dsp insns, and disable floating-point ISAs.\n\
 -isa=[sh4\n\
+    | sh4-nofpu		sh4 with fpu disabled\n\
+    | sh4-nommu-nofpu   sh4 with no MMU or FPU\n\
     | sh4a\n\
-    | dsp		same as '-dsp'\n\
+    | dsp               same as '-dsp'\n\
     | fp\n\
-    | shmedia		set as the default instruction set for SH64\n\
+    | any]		use most appropriate isa\n"));
+#ifdef HAVE_SH64
+  fprintf (stream, _("\
+-isa=[shmedia		set as the default instruction set for SH64\n\
     | SHmedia\n\
     | shcompact\n\
-    | SHcompact\n"));
+    | SHcompact]\n"));
   fprintf (stream, _("\
 -abi=[32|64]		set size of expanded SHmedia operands and object\n\
 			file type\n\
@@ -2994,13 +3057,6 @@ SH options:\n\
 -no-expand		do not expand MOVI, PT, PTA or PTB instructions\n\
 -expand-pt32		with -abi=64, expand PT, PTA and PTB instructions\n\
 			to 32 bits only\n"));
-#else
-  fprintf (stream, _("\
--isa=[sh4\n\
-    | sh4a\n\
-    | dsp		same as '-dsp'\n\
-    | fp\n\
-    | any]\n"));
 #endif /* HAVE_SH64 */
 }
 
@@ -3521,6 +3577,7 @@ sh_fix_adjustable (fixS *fixP)
   if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
       || fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
       || fixP->fx_r_type == BFD_RELOC_SH_GOTPC
+      || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
       || fixP->fx_r_type == BFD_RELOC_RVA)
     return 0;
 
@@ -3560,6 +3617,8 @@ sh_elf_final_processing (void)
     val = EF_SH3_DSP;
   else if (valid_arch & arch_sh3e)
     val = EF_SH3E;
+  else if (valid_arch & arch_sh4_nommu_nofpu)
+    val = EF_SH4_NOMMU_NOFPU;
   else if (valid_arch & arch_sh4_nofpu)
     val = EF_SH4_NOFPU;
   else if (valid_arch & arch_sh4)
@@ -4188,10 +4247,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
     rel->addend = 0;
 
   rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
-#ifdef OBJ_ELF
-  if (rel->howto->type == R_SH_IND12W)
-      rel->addend += fixp->fx_offset - 4;
-#endif
+
   if (rel->howto == NULL)
     {
       as_bad_where (fixp->fx_file, fixp->fx_line,
@@ -4201,6 +4257,10 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
       rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
       assert (rel->howto != NULL);
     }
+#ifdef OBJ_ELF
+  else if (rel->howto->type == R_SH_IND12W)
+    rel->addend += fixp->fx_offset - 4;
+#endif
 
   return rel;
 }
diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index 8f101dbccc1..5d5ccea5dac 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -3721,7 +3721,7 @@ xg_assemble_literal (insn)
   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
 
   assert (insn->insn_type == ITYPE_LITERAL);
-  assert (insn->ntok = 1);	/* must be only one token here */
+  assert (insn->ntok == 1);	/* must be only one token here */
 
   xtensa_switch_to_literal_fragment (&state);
 
@@ -7888,10 +7888,9 @@ xtensa_post_relax_hook ()
   xtensa_create_property_segments (get_frag_is_insn,
 				   XTENSA_INSN_SEC_NAME,
 				   xt_insn_sec);
-  if (use_literal_section)
-    xtensa_create_property_segments (get_frag_is_literal,
-				     XTENSA_LIT_SEC_NAME,
-				     xt_literal_sec);
+  xtensa_create_property_segments (get_frag_is_literal,
+				   XTENSA_LIT_SEC_NAME,
+				   xt_literal_sec);
 }