PR gas/14260

	* config/tc-arm.c (encode_arm_addr_mode_common): Generate an error
	message if literal pool addressing is used.

	* gas/arm/ldr-t-bad.s: Add test of bogus use of literal pool
	addressing.
	* gas/arm/ldr-t-bad.l: Update expected assembler error message
	output.

5 files changed, 33 insertions, 13 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0d833a9e5fc..111a211ba15 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
 2012-06-28  Nick Clifton  <nickc@redhat.com>
 
+	PR gas/14260
+	* config/tc-arm.c (encode_arm_addr_mode_common): Generate an error
+	message if literal pool addressing is used.
+
+2012-06-28  Nick Clifton  <nickc@redhat.com>
+
 	* dwarf2dbg.c (DWARF2_USE_FIXED_ADVANCE_PC): Enable when using
 	linker relaxation.
 	(dwarf2_gen_line_info): Generate real, local, labels for line
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2257d4e59b8..43e20d1ed3b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7042,7 +7042,11 @@ encode_arm_shifter_operand (int i)
 static void
 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
 {
-  gas_assert (inst.operands[i].isreg);
+  /* PR 14260:
+     Generate an error if the operand is not a register.  */
+  constraint (!inst.operands[i].isreg,
+	      _("Instruction does not support =N addresses"));
+
   inst.instruction |= inst.operands[i].reg << 16;
 
   if (inst.operands[i].preind)
@@ -21269,8 +21273,8 @@ md_apply_fix (fixS *	fixP,
     thumb_bl_common:
 
 #ifdef OBJ_ELF
-       if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
-	   fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
+       if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
+	   && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
 	 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
 #endif
 
@@ -21281,15 +21285,15 @@ md_apply_fix (fixS *	fixP,
 	   1 of the base address.  */
 	value = (value + 1) & ~ 1;
 
-       if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
-	 {
-	   if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
-	     as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
-	   else if ((value & ~0x1ffffff)
-		    && ((value & ~0x1ffffff) != ~0x1ffffff))
-	     as_bad_where (fixP->fx_file, fixP->fx_line,
-			   _("Thumb2 branch out of range"));
-	 }
+      if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
+	{
+	  if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
+	    as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
+	  else if ((value & ~0x1ffffff)
+		   && ((value & ~0x1ffffff) != ~0x1ffffff))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("Thumb2 branch out of range"));
+	}
 
       if (fixP->fx_done || !seg->use_rela_p)
 	encode_thumb2_b_bl_offset (buf, value);
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d76f013451b..6e41589a3cc 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,13 @@
 2012-06-28  Nick Clifton  <nickc@redhat.com>
 
+	PR gas/14260
+	* gas/arm/ldr-t-bad.s: Add test of bogus use of literal pool
+	addressing.
+	* gas/arm/ldr-t-bad.l: Update expected assembler error message
+	output.
+
+2012-06-28  Nick Clifton  <nickc@redhat.com>
+
 	* gas/lns/lns.exp: Use alternate lns-common test for targets
 	enabling linker relaxation.
 	* gas/lns/lns-big-delta.d: Allow for output from architectures
diff --git a/gas/testsuite/gas/arm/ldr-t-bad.l b/gas/testsuite/gas/arm/ldr-t-bad.l
index bda9eefa65d..95f420aad8f 100644
--- a/gas/testsuite/gas/arm/ldr-t-bad.l
+++ b/gas/testsuite/gas/arm/ldr-t-bad.l
@@ -13,4 +13,4 @@
 [^:]*:56: Error: r15 not allowed here -- `str r15,\[r1,r2\]'
 [^:]*:57: Error: r13 not allowed here -- `str r1,\[r2,r13\]'
 [^:]*:58: Error: r15 not allowed here -- `str r1,\[r2,r15\]'
-
+[^:]*:61: Error: Instruction does not support =N addresses -- `ldrt r0,=0x0'
diff --git a/gas/testsuite/gas/arm/ldr-t-bad.s b/gas/testsuite/gas/arm/ldr-t-bad.s
index ee76a3e3be2..81c17a54ebd 100644
--- a/gas/testsuite/gas/arm/ldr-t-bad.s
+++ b/gas/testsuite/gas/arm/ldr-t-bad.s
@@ -57,3 +57,5 @@
 	str r1, [r2, r13]
 	str r1, [r2, r15]
 
+	@ PR 14260
+	ldrt r0, =0x0