diff options
| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 19:40:51 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 19:55:21 +0000 |
| commit | 5284e471d53ccb7c7a1d140bd83098607ccf4b8a (patch) | |
| tree | b0c7d481500be41b59a1f8ab540dd25e9e20c599 /include/opcode | |
| parent | bdd152861ce75c36828904cf3d10f8ce14da6cf5 (diff) | |
| download | binutils-gdb-5284e471d53ccb7c7a1d140bd83098607ccf4b8a.tar.gz | |
MIPS16: Add ASMACRO instruction support
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/mips.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index e00f682c964..eb80dfebee3 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1809,12 +1809,18 @@ extern int bfd_mips_num_opcodes; "R" return address register ($ra or $31) "X" 5 bit MIPS register (MIPS16OP_*_REGR32) "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) + "0" 5-bit ASMACRO p0 immediate + "1" 3-bit ASMACRO p1 immediate + "2" 3-bit ASMACRO p2 immediate + "3" 5-bit ASMACRO p3 immediate + "4" 3-bit ASMACRO p4 immediate "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) "a" 26 bit jump address "i" likewise, but flips bit 0 "e" 11 bit extension value "l" register list for entry instruction "L" register list for exit instruction + "s" 3-bit ASMACRO select immediate "I" an immediate value used for macros @@ -1844,10 +1850,10 @@ extern int bfd_mips_num_opcodes; "M" 7 bit register list for restore instruction (18 bit extended) Characters used so far, for quick reference when adding more: - " 56 8 " + "0123456 8 " ".[]<" "ABCDEF HI KLM P RS UVWXYZ" - "a e ijklm pq vwxyz" + "a e ijklm pq s vwxyz" */ /* Save/restore encoding for the args field when all 4 registers are |