This commit was manufactured by cvs2svn to create branch 'binutils-

2_23-branch'.

Cherrypick from master 2012-08-14 11:59:05 UTC Nick Clifton <nickc@redhat.com> 'Updated Ukranian translations.':
    bfd/cpu-aarch64.c
    bfd/elf64-aarch64.c
    gas/config/tc-aarch64.c
    gas/config/tc-aarch64.h
    gas/doc/c-aarch64.texi
    gas/testsuite/gas/aarch64/aarch64.exp
    gas/testsuite/gas/aarch64/addsub.d
    gas/testsuite/gas/aarch64/addsub.s
    gas/testsuite/gas/aarch64/advsimd-across.d
    gas/testsuite/gas/aarch64/advsimd-across.s
    gas/testsuite/gas/aarch64/advsimd-misc.d
    gas/testsuite/gas/aarch64/advsimd-misc.s
    gas/testsuite/gas/aarch64/advsisd-copy.d
    gas/testsuite/gas/aarch64/advsisd-copy.s
    gas/testsuite/gas/aarch64/advsisd-misc.d
    gas/testsuite/gas/aarch64/advsisd-misc.s
    gas/testsuite/gas/aarch64/alias.d
    gas/testsuite/gas/aarch64/alias.s
    gas/testsuite/gas/aarch64/bitfield-alias.d
    gas/testsuite/gas/aarch64/bitfield-alias.s
    gas/testsuite/gas/aarch64/bitfield-bfm.d
    gas/testsuite/gas/aarch64/bitfield-bfm.s
    gas/testsuite/gas/aarch64/bitfield-dump
    gas/testsuite/gas/aarch64/bitfield-no-aliases.d
    gas/testsuite/gas/aarch64/crypto.d
    gas/testsuite/gas/aarch64/crypto.s
    gas/testsuite/gas/aarch64/diagnostic.d
    gas/testsuite/gas/aarch64/diagnostic.l
    gas/testsuite/gas/aarch64/diagnostic.s
    gas/testsuite/gas/aarch64/floatdp2.d
    gas/testsuite/gas/aarch64/floatdp2.s
    gas/testsuite/gas/aarch64/fp_cvt_int.d
    gas/testsuite/gas/aarch64/fp_cvt_int.s
    gas/testsuite/gas/aarch64/illegal-2.d
    gas/testsuite/gas/aarch64/illegal-2.l
    gas/testsuite/gas/aarch64/illegal-2.s
    gas/testsuite/gas/aarch64/illegal.d
    gas/testsuite/gas/aarch64/illegal.l
    gas/testsuite/gas/aarch64/illegal.s
    gas/testsuite/gas/aarch64/inst-directive.d
    gas/testsuite/gas/aarch64/inst-directive.s
    gas/testsuite/gas/aarch64/int-insns.d
    gas/testsuite/gas/aarch64/int-insns.s
    gas/testsuite/gas/aarch64/ldst-exclusive.d
    gas/testsuite/gas/aarch64/ldst-exclusive.s
    gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d
    gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s
    gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d
    gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s
    gas/testsuite/gas/aarch64/ldst-reg-pair.d
    gas/testsuite/gas/aarch64/ldst-reg-pair.s
    gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d
    gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s
    gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d
    gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s
    gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d
    gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s
    gas/testsuite/gas/aarch64/legacy_reg_names.d
    gas/testsuite/gas/aarch64/legacy_reg_names.l
    gas/testsuite/gas/aarch64/legacy_reg_names.s
    gas/testsuite/gas/aarch64/mapmisc.d
    gas/testsuite/gas/aarch64/mapmisc.dat
    gas/testsuite/gas/aarch64/mapmisc.s
    gas/testsuite/gas/aarch64/mapping.d
    gas/testsuite/gas/aarch64/mapping.s
    gas/testsuite/gas/aarch64/mapping2.d
    gas/testsuite/gas/aarch64/mapping2.s
    gas/testsuite/gas/aarch64/mapping3.d
    gas/testsuite/gas/aarch64/mapping3.s
    gas/testsuite/gas/aarch64/mapping4.d
    gas/testsuite/gas/aarch64/mapping4.s
    gas/testsuite/gas/aarch64/mov-no-aliases.d
    gas/testsuite/gas/aarch64/mov.d
    gas/testsuite/gas/aarch64/mov.s
    gas/testsuite/gas/aarch64/movi.d
    gas/testsuite/gas/aarch64/movi.s
    gas/testsuite/gas/aarch64/msr.d
    gas/testsuite/gas/aarch64/msr.s
    gas/testsuite/gas/aarch64/neon-fp-cvt-int.d
    gas/testsuite/gas/aarch64/neon-fp-cvt-int.s
    gas/testsuite/gas/aarch64/neon-frint.d
    gas/testsuite/gas/aarch64/neon-frint.s
    gas/testsuite/gas/aarch64/neon-ins.d
    gas/testsuite/gas/aarch64/neon-ins.s
    gas/testsuite/gas/aarch64/neon-not.d
    gas/testsuite/gas/aarch64/neon-not.s
    gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
    gas/testsuite/gas/aarch64/neon-vfp-reglist-post.s
    gas/testsuite/gas/aarch64/neon-vfp-reglist.d
    gas/testsuite/gas/aarch64/neon-vfp-reglist.s
    gas/testsuite/gas/aarch64/no-aliases.d
    gas/testsuite/gas/aarch64/optional.d
    gas/testsuite/gas/aarch64/optional.s
    gas/testsuite/gas/aarch64/programmer-friendly.d
    gas/testsuite/gas/aarch64/programmer-friendly.s
    gas/testsuite/gas/aarch64/reloc-data.d
    gas/testsuite/gas/aarch64/reloc-data.s
    gas/testsuite/gas/aarch64/reloc-insn.d
    gas/testsuite/gas/aarch64/reloc-insn.s
    gas/testsuite/gas/aarch64/shifted.d
    gas/testsuite/gas/aarch64/shifted.s
    gas/testsuite/gas/aarch64/symbol.d
    gas/testsuite/gas/aarch64/symbol.s
    gas/testsuite/gas/aarch64/sysreg-1.d
    gas/testsuite/gas/aarch64/sysreg-1.s
    gas/testsuite/gas/aarch64/sysreg.d
    gas/testsuite/gas/aarch64/sysreg.s
    gas/testsuite/gas/aarch64/system.d
    gas/testsuite/gas/aarch64/system.s
    gas/testsuite/gas/aarch64/tlbi_op.d
    gas/testsuite/gas/aarch64/tlbi_op.s
    gas/testsuite/gas/aarch64/tls.d
    gas/testsuite/gas/aarch64/tls.s
    gas/testsuite/gas/aarch64/verbose-error.d
    gas/testsuite/gas/aarch64/verbose-error.l
    gas/testsuite/gas/aarch64/verbose-error.s
    gas/testsuite/gas/i386/arch-10-bdver2.d
    gas/testsuite/gas/i386/x86-64-arch-2-bdver2.d
    gas/testsuite/gas/mips/branch-swap-2.l
    gas/testsuite/gas/mips/branch-swap-2.s
    gas/testsuite/gas/mmix/err-fb-2.s
    include/elf/aarch64.h
    include/opcode/aarch64.h
    ld/emulparams/aarch64elf.sh
    ld/emulparams/aarch64elfb.sh
    ld/emulparams/aarch64linux.sh
    ld/emulparams/aarch64linuxb.sh
    ld/emultempl/aarch64elf.em
    ld/po/uk.po
    ld/testsuite/ld-aarch64/aarch64-elf.exp
    ld/testsuite/ld-aarch64/aarch64.ld
    ld/testsuite/ld-aarch64/eh-frame-bar.s
    ld/testsuite/ld-aarch64/eh-frame-foo.s
    ld/testsuite/ld-aarch64/eh-frame.d
    ld/testsuite/ld-aarch64/emit-relocs-257-be.d
    ld/testsuite/ld-aarch64/emit-relocs-257.d
    ld/testsuite/ld-aarch64/emit-relocs-257.s
    ld/testsuite/ld-aarch64/emit-relocs-260-be.d
    ld/testsuite/ld-aarch64/emit-relocs-260.d
    ld/testsuite/ld-aarch64/emit-relocs-260.s
    ld/testsuite/ld-aarch64/emit-relocs-262.d
    ld/testsuite/ld-aarch64/emit-relocs-262.s
    ld/testsuite/ld-aarch64/emit-relocs-263.d
    ld/testsuite/ld-aarch64/emit-relocs-263.s
    ld/testsuite/ld-aarch64/emit-relocs-264.d
    ld/testsuite/ld-aarch64/emit-relocs-264.s
    ld/testsuite/ld-aarch64/emit-relocs-265.d
    ld/testsuite/ld-aarch64/emit-relocs-265.s
    ld/testsuite/ld-aarch64/emit-relocs-266.d
    ld/testsuite/ld-aarch64/emit-relocs-266.s
    ld/testsuite/ld-aarch64/emit-relocs-267.d
    ld/testsuite/ld-aarch64/emit-relocs-267.s
    ld/testsuite/ld-aarch64/emit-relocs-268.d
    ld/testsuite/ld-aarch64/emit-relocs-268.s
    ld/testsuite/ld-aarch64/emit-relocs-269.d
    ld/testsuite/ld-aarch64/emit-relocs-269.s
    ld/testsuite/ld-aarch64/emit-relocs-270-bad.d
    ld/testsuite/ld-aarch64/emit-relocs-270.d
    ld/testsuite/ld-aarch64/emit-relocs-270.s
    ld/testsuite/ld-aarch64/emit-relocs-271.d
    ld/testsuite/ld-aarch64/emit-relocs-271.s
    ld/testsuite/ld-aarch64/emit-relocs-272.d
    ld/testsuite/ld-aarch64/emit-relocs-272.s
    ld/testsuite/ld-aarch64/emit-relocs-273.d
    ld/testsuite/ld-aarch64/emit-relocs-273.s
    ld/testsuite/ld-aarch64/emit-relocs-274.d
    ld/testsuite/ld-aarch64/emit-relocs-274.s
    ld/testsuite/ld-aarch64/emit-relocs-275.d
    ld/testsuite/ld-aarch64/emit-relocs-275.s
    ld/testsuite/ld-aarch64/emit-relocs-276.d
    ld/testsuite/ld-aarch64/emit-relocs-276.s
    ld/testsuite/ld-aarch64/emit-relocs-277.d
    ld/testsuite/ld-aarch64/emit-relocs-277.s
    ld/testsuite/ld-aarch64/emit-relocs-278.d
    ld/testsuite/ld-aarch64/emit-relocs-278.s
    ld/testsuite/ld-aarch64/emit-relocs-279-bad.d
    ld/testsuite/ld-aarch64/emit-relocs-279.d
    ld/testsuite/ld-aarch64/emit-relocs-279.s
    ld/testsuite/ld-aarch64/emit-relocs-280.d
    ld/testsuite/ld-aarch64/emit-relocs-280.s
    ld/testsuite/ld-aarch64/emit-relocs-282.d
    ld/testsuite/ld-aarch64/emit-relocs-282.s
    ld/testsuite/ld-aarch64/emit-relocs-283.d
    ld/testsuite/ld-aarch64/emit-relocs-283.s
    ld/testsuite/ld-aarch64/emit-relocs-284.d
    ld/testsuite/ld-aarch64/emit-relocs-284.s
    ld/testsuite/ld-aarch64/emit-relocs-285.d
    ld/testsuite/ld-aarch64/emit-relocs-285.s
    ld/testsuite/ld-aarch64/emit-relocs-286-bad.d
    ld/testsuite/ld-aarch64/emit-relocs-286.d
    ld/testsuite/ld-aarch64/emit-relocs-286.s
    ld/testsuite/ld-aarch64/emit-relocs-287.d
    ld/testsuite/ld-aarch64/emit-relocs-287.s
    ld/testsuite/ld-aarch64/emit-relocs-299.d
    ld/testsuite/ld-aarch64/emit-relocs-299.s
    ld/testsuite/ld-aarch64/emit-relocs-311.d
    ld/testsuite/ld-aarch64/emit-relocs-311.s
    ld/testsuite/ld-aarch64/emit-relocs-312.d
    ld/testsuite/ld-aarch64/emit-relocs-312.s
    ld/testsuite/ld-aarch64/emit-relocs1.s
    ld/testsuite/ld-aarch64/farcall-b-none-function.d
    ld/testsuite/ld-aarch64/farcall-b-none-function.s
    ld/testsuite/ld-aarch64/farcall-b.d
    ld/testsuite/ld-aarch64/farcall-b.s
    ld/testsuite/ld-aarch64/farcall-back.d
    ld/testsuite/ld-aarch64/farcall-back.s
    ld/testsuite/ld-aarch64/farcall-bl-none-function.d
    ld/testsuite/ld-aarch64/farcall-bl-none-function.s
    ld/testsuite/ld-aarch64/farcall-bl.d
    ld/testsuite/ld-aarch64/farcall-bl.s
    ld/testsuite/ld-aarch64/farcall-section.d
    ld/testsuite/ld-aarch64/farcall-section.s
    ld/testsuite/ld-aarch64/limit-b.d
    ld/testsuite/ld-aarch64/limit-b.s
    ld/testsuite/ld-aarch64/limit-bl.d
    ld/testsuite/ld-aarch64/limit-bl.s
    ld/testsuite/ld-aarch64/relocs.ld
    ld/testsuite/ld-aarch64/tls-desc-ie.d
    ld/testsuite/ld-aarch64/tls-desc-ie.s
    ld/testsuite/ld-aarch64/tls-relax-all.d
    ld/testsuite/ld-aarch64/tls-relax-all.s
    ld/testsuite/ld-aarch64/tls-relax-gd-ie.d
    ld/testsuite/ld-aarch64/tls-relax-gd-ie.s
    ld/testsuite/ld-aarch64/tls-relax-gd-le.d
    ld/testsuite/ld-aarch64/tls-relax-gd-le.s
    ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d
    ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.s
    ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d
    ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
    ld/testsuite/ld-aarch64/tls-relax-gdesc-le-2.d
    ld/testsuite/ld-aarch64/tls-relax-gdesc-le-2.s
    ld/testsuite/ld-aarch64/tls-relax-gdesc-le.d
    ld/testsuite/ld-aarch64/tls-relax-gdesc-le.s
    ld/testsuite/ld-aarch64/tls-relax-ie-le-2.d
    ld/testsuite/ld-aarch64/tls-relax-ie-le-2.s
    ld/testsuite/ld-aarch64/tls-relax-ie-le-3.d
    ld/testsuite/ld-aarch64/tls-relax-ie-le-3.s
    ld/testsuite/ld-aarch64/tls-relax-ie-le.d
    ld/testsuite/ld-aarch64/tls-relax-ie-le.s
    ld/testsuite/ld-aarch64/weak-undefined.d
    ld/testsuite/ld-aarch64/weak-undefined.s
    ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d
    ld/testsuite/ld-mips-elf/export-class-call16-def.s
    ld/testsuite/ld-mips-elf/export-class-call16-n32.dd
    ld/testsuite/ld-mips-elf/export-class-call16-n32.gd
    ld/testsuite/ld-mips-elf/export-class-call16-n32.s
    ld/testsuite/ld-mips-elf/export-class-call16-n64.dd
    ld/testsuite/ld-mips-elf/export-class-call16-n64.gd
    ld/testsuite/ld-mips-elf/export-class-call16-n64.s
    ld/testsuite/ld-mips-elf/export-class-call16-o32-irix.dd
    ld/testsuite/ld-mips-elf/export-class-call16-o32.dd
    ld/testsuite/ld-mips-elf/export-class-call16-o32.gd
    ld/testsuite/ld-mips-elf/export-class-call16-o32.s
    ld/testsuite/ld-mips-elf/export-class-call16.ld
    ld/testsuite/ld-mips-elf/gp-hidden-64.rd
    ld/testsuite/ld-mips-elf/gp-hidden-lib-64.rd
    ld/testsuite/ld-mips-elf/gp-hidden-lib.rd
    ld/testsuite/ld-mips-elf/gp-hidden-lib.s
    ld/testsuite/ld-mips-elf/gp-hidden-ver-64.rd
    ld/testsuite/ld-mips-elf/gp-hidden-ver.rd
    ld/testsuite/ld-mips-elf/gp-hidden-ver.s
    ld/testsuite/ld-mips-elf/gp-hidden-ver.ver
    ld/testsuite/ld-mips-elf/gp-hidden.rd
    ld/testsuite/ld-mips-elf/gp-hidden.s
    ld/testsuite/ld-mips-elf/gp-hidden.sd
    opcodes/aarch64-asm-2.c
    opcodes/aarch64-asm.c
    opcodes/aarch64-asm.h
    opcodes/aarch64-dis-2.c
    opcodes/aarch64-dis.c
    opcodes/aarch64-dis.h
    opcodes/aarch64-gen.c
    opcodes/aarch64-opc-2.c
    opcodes/aarch64-opc.c
    opcodes/aarch64-opc.h
    opcodes/aarch64-tbl.h

1 files changed, 195 insertions, 0 deletions

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
new file mode 100644
index 00000000000..68681f6a1cf
--- /dev/null
+++ b/opcodes/aarch64-opc-2.c
@@ -0,0 +1,195 @@
+/* This file is automatically generated by aarch64-gen.  Do not edit!  */
+/* Copyright 2012  Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+#include "sysdep.h"
+#include "aarch64-opc.h"
+
+
+const struct aarch64_operand aarch64_operands[] =
+{
+  {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
+  {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
+  {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
+  {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"},
+  {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
+  {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
+  {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
+  {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
+  {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
+  {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
+  {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"},
+  {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
+  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
+  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
+  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
+  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
+  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
+  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
+  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
+  {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+  {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit unsigned immediate with optional shift"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit floating-point constant"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
+  {AARCH64_OPND_CLASS_NIL, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
+  {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"},
+  {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instructin cache maintenance operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
+  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an prefetch operation specifier"},
+  {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
+};
+
+/* Indexed by an enum aarch64_op enumerator, the value is the offset of
+   the corresponding aarch64_opcode entry in the aarch64_opcode_table.  */
+
+static const unsigned op_enum_table [] =
+{
+  0,
+  648,
+  649,
+  650,
+  653,
+  654,
+  655,
+  656,
+  657,
+  651,
+  652,
+  658,
+  659,
+  681,
+  682,
+  685,
+  691,
+  692,
+  695,
+  697,
+  698,
+  687,
+  688,
+  701,
+  703,
+  741,
+  742,
+  743,
+  744,
+  12,
+  506,
+  507,
+  764,
+  766,
+  768,
+  748,
+  767,
+  765,
+  259,
+  495,
+  505,
+  504,
+  746,
+  501,
+  498,
+  491,
+  490,
+  497,
+  500,
+  502,
+  503,
+  756,
+  125,
+  522,
+  525,
+  528,
+  523,
+  526,
+  614,
+  160,
+  161,
+  162,
+  163,
+  416,
+  583,
+};
+
+/* Given the opcode enumerator OP, return the pointer to the corresponding
+   opcode entry.  */
+
+const aarch64_opcode *
+aarch64_get_opcode (enum aarch64_op op)
+{
+  return aarch64_opcode_table + op_enum_table[op];
+}