Initial creation of sourceware repositorygdb-4_18-branchpoint

25 files changed, 27150 insertions, 0 deletions

diff --git a/sim/fr30/ChangeLog b/sim/fr30/ChangeLog
new file mode 100644
index 00000000000..dd399aafb59
--- /dev/null
+++ b/sim/fr30/ChangeLog
@@ -0,0 +1,287 @@
+1999-02-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_DEPS): Add fr30-desc.h, delete cpu-opc.h.
+	* configure.in (sim_link_files,sim_link_links): Delete.
+	* configure: Rebuild.
+	* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+	* fr30.c (fr30bf_model_fr30_1_u_cti): CGEN_INSN_ATTR renamed to
+	CGEN_INSN_ATTR_VALUE.
+	* mloop.in (extract-pbb): Ditto. Use idesc->length to get insn length.
+	* sim-if.c (sim_open): fr30_cgen_cpu_open renamed from
+	fr30_cgen_opcode_open.  Set disassembler.
+	(sim_close): fr30_cgen_cpu_open renamed from fr30_cgen_opcode_open.
+	* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
+	fr30-desc.h,fr30-opc.h,fr30-sim.h.
+
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
+1999-01-15  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.h,model.c: Regenerate.
+	* fr30.c (fr30bf_model_insn_before): Clear load_regs_pending.
+	(fr30bf_model_insn_after): Copy load_regs_pending to load_regs.
+	(fr30bf_model_fr30_1_u_exec): Check for load stalls.
+	(fr30bf_model_fr30_1_u_{cti,load,store}): Ditto.
+
+1999-01-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* arch.c,arch.h,cpuall.h: Regenerate.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+	* devices.c (device_io_write_buffer): Remove some m32r cruft.
+	* fr30-sim.h (FR30_MISC_PROFILE): Delete, plus supporting macros.
+	(EIT_*,MSPR_*,MLCR_*,MPMR_*): Delete, m32r cruft.
+	* fr30.c (fr30bf_model_insn_after): Update cycle counts.
+	(check_load_stall): New function.
+	(fr30bf_model_fr30_1_u_exec): Update argument list.
+	(fr30bf_model_fr30_1_u_{cti,load,store,ldm,stm}): New functions.
+	* sim-if.c (sim_open): Comment out memory mapped device allocation.
+	Delete FR30_MISC_PROFILE handling.
+	(print_fr30_misc_cpu): Delete.
+	* sim-main.h (_sim_cpu): Delete member fr30_misc_profile.
+	* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
+
+1999-01-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (fr30-clean): rm eng.h.
+
+	* sim-main.h: Delete inclusion of ansidecl.h.
+	Include sim-basics.h before cgen-types.h.
+	Delete inclusion of cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
+	* cpu.h,sem-switch.c,sem.c: Regenerate.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
+	(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
+	(sim-if.o,arch.o,devices.o): Use SIM_MAIN_DEPS.
+	(FR30BF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
+	(mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
+	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* fr30-sim.h (fr30bf_h_sbit_[gs]et_handler): Declare.
+	([GS]ET_H_SBIT): Define.
+	(fr30bf_h_ccr_[gs]et_handler): Declare.
+	([GS]ET_H_CCR): Define.
+	(fr30bf_h_scr_[gs]et_handler): Declare.
+	([GS]ET_H_SCR): Define.
+	(fr30bf_h_ilm_[gs]et_handler): Declare.
+	([GS]ET_H_ILM): Define.
+	(fr30bf_h_ps_[gs]et_handler): Declare.
+	([GS]ET_H_PS): Define.
+	(fr30bf_h_dr_[gs]et_handler): Declare.
+	([GS]ET_H_DR): Define.
+	* fr30.c (all register access fns): Rename to ..._handler.
+	(fr30bf_h_*_get_handler,fr30bf_h_*_set_handler): Rewrite to use
+	CPU or GET_H_FOO/SET_H_FOO access macros as appropriate.
+	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
+
+Fri Dec 18 17:09:34 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30.c (fr30bf_store_register): Call a_fr30_h_dr_set for
+	dedicated registers.
+
+Thu Dec 17 17:17:48 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* sem-switch.c,sem.c: Regenerate.
+
+Tue Dec 15 17:39:59 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (setup_int): Correct calls to SETMEMSI.
+	(fr30_int): Must calculate new pc after saving old one.
+	* fr30.c (fr30bf_h_sbit_get): New function.
+	(fr30bf_h_sbit_set): New function.
+	(fr30bf_h_ccr_set): Use fr30bf_h_sbit_set and move stack switching
+	logic to that function.
+	* cpu.[ch],decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* configure.in: --enable-cgen-maint moved to common/aclocal.m4.
+	* configure: Regenerate.
+
+	* sem-switch.c,sem.c: Regenerate.
+
+	* traps.c (setup_int): Use enums for register numbers.
+	(fr30_int): Ditto.
+
+1998-12-14  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.[ch],model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Dec 10 18:43:13 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.[ch],cpu.[ch],decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* fr30.c (fr30bf_h_scr_get): Implement as separate bits.
+	(fr30bf_h_scr_set): Implement as separate bits.
+
+Wed Dec  9 13:25:37 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+
+Tue Dec  8 13:15:23 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+Mon Dec  7 14:35:23 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (fr30_inte): New function.
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-12-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,cpuall.h,decode.c,sem-switch.c,sem.c: Regenerate.
+	* mloop.in (extract): Make static inline.  Rewrite.
+	(execute): Check ARGBUF_PROFILE_P before profiling.
+	Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
+
+Fri Dec  4 16:18:25 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* sem.c,sem-switch.c: Regenerate.
+	* cpu.h,decode.c: Regenerate.
+
+Fri Dec  4 17:09:27 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+
+Fri Dec  4 00:22:43 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Dec  3 17:33:16 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30.c (fr30bf_h_ccr_get): New function.
+	(fr30bf_h_ccr_set): New function.
+	(fr30bf_h_ps_get): Use ccr access function.
+	(fr30bf_h_ps_set): Use ccr access function.
+	(fr30bf_h_scr_get): New function.
+	(fr30bf_h_scr_set): New function.
+	(fr30bf_h_ilm_get): New function.
+	(fr30bf_h_ilm_set): New function
+	(fr30bf_h_ps_get): Implement src and ilm.
+	(fr30bf_h_ps_set): Implement src and ilm.
+
+	* arch.c,arch.h,cpu.h,decode.c,decode.h,model.c,
+	sem-switch.c,sem.c: Regenerate.
+
+Thu Dec  3 00:15:11 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-11-30  Doug Evans  <devans@casey.cygnus.com>
+
+	* mloop.in (extract-pbb): Add delay slot support.
+	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Nov 26 11:28:30 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerated.
+
+Mon Nov 23 18:30:36 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerated.
+
+1998-11-20  Doug Evans  <devans@tobor.to.cygnus.com>
+
+	* fr30-sim.h (*-REGNUM): Sync up with gdb.
+	* fr30.c (decode_gdb_dr_regnum): New function.
+	(fr30bf_fetch_register): Implement.
+	(fr30bf_store_register): Ditto.
+	(fr30bf_h_ps_get,fr30bf_h_ps_set): Ditto.
+	(fr30bf_h_dr_get,fr30bf_h_dr_set): New functions.
+	* sem-switch.c,sem.c: Rebuild.
+	* traps.c (setup_int): New function
+	(fr30_int): Handle all int insn processing here.
+	Don't save ps,pc if breakpoint trap.
+	* cpu.c,cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Nov 19 16:05:09 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (fr30_int): Correct register usage.
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Wed Nov 18 21:39:37 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30-sim.h (TRAP_SYSCALL, TRAP_BREAKPOINT): Redefine for fr30.
+	* fr30.c (fr30bf_h_ps_get): New function.
+	(fr30bf_h_ps_set): New function.
+	* mloop.in: Set up fast-pbb model for fr30.
+	* traps.c (fr30_int): New function.
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+1998-11-18  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (FR30_OBJS): Delete extract.o.
+	(FR30BF_INCLUDE_DEPS): Add cgen-engine.h.
+	(extract.o): Delete rule for.
+	* mloop.in: Rewrite.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+
+Wed Nov 18 11:31:21 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Mon Nov 16 19:23:44 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Thu Nov 12 19:27:50 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+	* fr30.c: Get rid of unused functions.
+
+Mon Nov  9 18:25:47 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+	* fr30.c: Get rid of m32r stuff. Flesh out fr30 stuff.
+
+Thu Nov  5 15:26:22 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h: Regenerated.
+
+Tue Oct 27 15:39:48 1996  Dave Brolley  <brolley@cygnus.com>
+
+	* Directory created.
diff --git a/sim/fr30/Makefile.in b/sim/fr30/Makefile.in
new file mode 100644
index 00000000000..427312e70bc
--- /dev/null
+++ b/sim/fr30/Makefile.in
@@ -0,0 +1,90 @@
+# Makefile template for Configure for the fr30 simulator
+# Copyright (C) 1998 Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+FR30_OBJS = fr30.o cpu.o decode.o sem.o model.o mloop.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+	$(SIM_NEW_COMMON_OBJS) \
+	sim-cpu.o \
+	sim-hload.o \
+	sim-hrw.o \
+	sim-model.o \
+	sim-reg.o \
+	cgen-utils.o cgen-trace.o cgen-scache.o \
+	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+	sim-if.o arch.o \
+	$(FR30_OBJS) \
+	traps.o devices.o \
+	$(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+	$(CGEN_INCLUDE_DEPS) \
+	arch.h cpuall.h fr30-sim.h $(srcdir)/../../opcodes/fr30-desc.h
+
+SIM_EXTRA_CFLAGS =
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = fr30-clean
+
+# This selects the fr30 newlib/libgloss syscall definitions.
+NL_TARGET = -DNL_TARGET_fr30
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = fr30
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# FR30 objs
+
+FR30BF_INCLUDE_DEPS = \
+	$(CGEN_MAIN_CPU_DEPS) \
+	cpu.h decode.h eng.h
+
+fr30.o: fr30.c $(FR30BF_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop.c eng.h: stamp-mloop
+stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+	$(SHELL) $(srccom)/genmloop.sh \
+		-mono -fast -pbb -switch sem-switch.c \
+		-cpu fr30bf -infile $(srcdir)/mloop.in
+	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
+	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
+	touch stamp-mloop
+mloop.o: mloop.c sem-switch.c $(FR30BF_INCLUDE_DEPS)
+
+cpu.o: cpu.c $(FR30BF_INCLUDE_DEPS)
+decode.o: decode.c $(FR30BF_INCLUDE_DEPS)
+sem.o: sem.c $(FR30BF_INCLUDE_DEPS)
+model.o: model.c $(FR30BF_INCLUDE_DEPS)
+
+fr30-clean:
+	rm -f mloop.c eng.h stamp-mloop
+	rm -f tmp-*
+
diff --git a/sim/fr30/README b/sim/fr30/README
new file mode 100644
index 00000000000..47bf314943e
--- /dev/null
+++ b/sim/fr30/README
@@ -0,0 +1,14 @@
+This is the fr30 simulator directory.
+
+It is still work-in-progress.  The current sources are reasonably
+well tested and lots of features are in.  However, there's lots
+more yet to come.
+
+There are lots of machine generated files in the source directory!
+They are only generated if you configure with --enable-cgen-maint,
+similar in behaviour to Makefile.in, configure under automake/autoconf.
+
+For details on the generator, see ../../cgen.
+
+devo/cgen isn't part of the comp-tools module yet.
+You'll need to check it out manually (also akin to automake/autoconf).
diff --git a/sim/fr30/TODO b/sim/fr30/TODO
new file mode 100644
index 00000000000..ae4c76078f2
--- /dev/null
+++ b/sim/fr30/TODO
@@ -0,0 +1,14 @@
+m32r-inherited stuff?
+----------------------
+- header file dependencies revisit
+- hooks cleanup
+- testsuites
+- FIXME's
+
+
+m32r stuff?
+----------------------
+- memory accesses still test if profiling is on even in fast mode
+- have semantic code use G/SET_H_FOO if not default [incl fun-access]
+- have G/SET_H_FOO macros call function if fun-access
+- --> can always use G/S_H_FOO macros
diff --git a/sim/fr30/arch.c b/sim/fr30/arch.c
new file mode 100644
index 00000000000..db6e23e1a02
--- /dev/null
+++ b/sim/fr30/arch.c
@@ -0,0 +1,695 @@
+/* Simulator support for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_FR30BF
+  & fr30_mach,
+#endif
+  0
+};
+
+/* Get the value of h-pc.  */
+
+USI
+a_fr30_h_pc_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_pc_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-pc.  */
+
+void
+a_fr30_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_pc_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-gr.  */
+
+SI
+a_fr30_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_gr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-gr.  */
+
+void
+a_fr30_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-cr.  */
+
+SI
+a_fr30_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_cr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-cr.  */
+
+void
+a_fr30_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_cr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-dr.  */
+
+SI
+a_fr30_h_dr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_dr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-dr.  */
+
+void
+a_fr30_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_dr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ps.  */
+
+USI
+a_fr30_h_ps_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ps_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ps.  */
+
+void
+a_fr30_h_ps_set (SIM_CPU *current_cpu, USI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ps_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r13.  */
+
+SI
+a_fr30_h_r13_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r13_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r13.  */
+
+void
+a_fr30_h_r13_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r13_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r14.  */
+
+SI
+a_fr30_h_r14_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r14_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r14.  */
+
+void
+a_fr30_h_r14_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r14_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r15.  */
+
+SI
+a_fr30_h_r15_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r15_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r15.  */
+
+void
+a_fr30_h_r15_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r15_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-nbit.  */
+
+BI
+a_fr30_h_nbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_nbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-nbit.  */
+
+void
+a_fr30_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_nbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-zbit.  */
+
+BI
+a_fr30_h_zbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_zbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-zbit.  */
+
+void
+a_fr30_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_zbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-vbit.  */
+
+BI
+a_fr30_h_vbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_vbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-vbit.  */
+
+void
+a_fr30_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_vbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-cbit.  */
+
+BI
+a_fr30_h_cbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_cbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-cbit.  */
+
+void
+a_fr30_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_cbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ibit.  */
+
+BI
+a_fr30_h_ibit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ibit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ibit.  */
+
+void
+a_fr30_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ibit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-sbit.  */
+
+BI
+a_fr30_h_sbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_sbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-sbit.  */
+
+void
+a_fr30_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_sbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-tbit.  */
+
+BI
+a_fr30_h_tbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_tbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-tbit.  */
+
+void
+a_fr30_h_tbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_tbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-d0bit.  */
+
+BI
+a_fr30_h_d0bit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_d0bit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-d0bit.  */
+
+void
+a_fr30_h_d0bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_d0bit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-d1bit.  */
+
+BI
+a_fr30_h_d1bit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_d1bit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-d1bit.  */
+
+void
+a_fr30_h_d1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_d1bit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ccr.  */
+
+UQI
+a_fr30_h_ccr_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ccr_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ccr.  */
+
+void
+a_fr30_h_ccr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ccr_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-scr.  */
+
+UQI
+a_fr30_h_scr_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_scr_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-scr.  */
+
+void
+a_fr30_h_scr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_scr_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ilm.  */
+
+UQI
+a_fr30_h_ilm_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ilm_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ilm.  */
+
+void
+a_fr30_h_ilm_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ilm_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
diff --git a/sim/fr30/arch.h b/sim/fr30/arch.h
new file mode 100644
index 00000000000..7bde11d66da
--- /dev/null
+++ b/sim/fr30/arch.h
@@ -0,0 +1,87 @@
+/* Simulator header for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30_ARCH_H
+#define FR30_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Cover fns for register access.  */
+USI a_fr30_h_pc_get (SIM_CPU *);
+void a_fr30_h_pc_set (SIM_CPU *, USI);
+SI a_fr30_h_gr_get (SIM_CPU *, UINT);
+void a_fr30_h_gr_set (SIM_CPU *, UINT, SI);
+SI a_fr30_h_cr_get (SIM_CPU *, UINT);
+void a_fr30_h_cr_set (SIM_CPU *, UINT, SI);
+SI a_fr30_h_dr_get (SIM_CPU *, UINT);
+void a_fr30_h_dr_set (SIM_CPU *, UINT, SI);
+USI a_fr30_h_ps_get (SIM_CPU *);
+void a_fr30_h_ps_set (SIM_CPU *, USI);
+SI a_fr30_h_r13_get (SIM_CPU *);
+void a_fr30_h_r13_set (SIM_CPU *, SI);
+SI a_fr30_h_r14_get (SIM_CPU *);
+void a_fr30_h_r14_set (SIM_CPU *, SI);
+SI a_fr30_h_r15_get (SIM_CPU *);
+void a_fr30_h_r15_set (SIM_CPU *, SI);
+BI a_fr30_h_nbit_get (SIM_CPU *);
+void a_fr30_h_nbit_set (SIM_CPU *, BI);
+BI a_fr30_h_zbit_get (SIM_CPU *);
+void a_fr30_h_zbit_set (SIM_CPU *, BI);
+BI a_fr30_h_vbit_get (SIM_CPU *);
+void a_fr30_h_vbit_set (SIM_CPU *, BI);
+BI a_fr30_h_cbit_get (SIM_CPU *);
+void a_fr30_h_cbit_set (SIM_CPU *, BI);
+BI a_fr30_h_ibit_get (SIM_CPU *);
+void a_fr30_h_ibit_set (SIM_CPU *, BI);
+BI a_fr30_h_sbit_get (SIM_CPU *);
+void a_fr30_h_sbit_set (SIM_CPU *, BI);
+BI a_fr30_h_tbit_get (SIM_CPU *);
+void a_fr30_h_tbit_set (SIM_CPU *, BI);
+BI a_fr30_h_d0bit_get (SIM_CPU *);
+void a_fr30_h_d0bit_set (SIM_CPU *, BI);
+BI a_fr30_h_d1bit_get (SIM_CPU *);
+void a_fr30_h_d1bit_set (SIM_CPU *, BI);
+UQI a_fr30_h_ccr_get (SIM_CPU *);
+void a_fr30_h_ccr_set (SIM_CPU *, UQI);
+UQI a_fr30_h_scr_get (SIM_CPU *);
+void a_fr30_h_scr_set (SIM_CPU *, UQI);
+UQI a_fr30_h_ilm_get (SIM_CPU *);
+void a_fr30_h_ilm_set (SIM_CPU *, UQI);
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_FR30_1, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_FR30_1_U_STM, UNIT_FR30_1_U_LDM, UNIT_FR30_1_U_STORE
+ , UNIT_FR30_1_U_LOAD, UNIT_FR30_1_U_CTI, UNIT_FR30_1_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (3)
+
+#endif /* FR30_ARCH_H */
diff --git a/sim/fr30/config.in b/sim/fr30/config.in
new file mode 100644
index 00000000000..9723b8662c9
--- /dev/null
+++ b/sim/fr30/config.in
@@ -0,0 +1,162 @@
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Define if using alloca.c.  */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work.  */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro.  */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call.  */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define.  */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work.  */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void).  */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define.  */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files.  */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function.  */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function.  */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function.  */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function.  */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function.  */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function.  */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function.  */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function.  */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function.  */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function.  */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function.  */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function.  */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function.  */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function.  */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function.  */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function.  */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file.  */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <fcntl.h> header file.  */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file.  */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file.  */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file.  */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file.  */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file.  */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file.  */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file.  */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/time.h> header file.  */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file.  */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file.  */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file.  */
+#undef HAVE_VALUES_H
diff --git a/sim/fr30/configure b/sim/fr30/configure
new file mode 100644
index 00000000000..43063ad23bb
--- /dev/null
+++ b/sim/fr30/configure
@@ -0,0 +1,4222 @@
+#! /bin/sh
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# This file is derived from `gettext.m4'.  The difference is that the
+# included macros assume Cygnus-style source and build trees.
+
+# Macro to add for using GNU gettext.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 3
+
+
+
+
+
+# Search path for a program which passes the given test.
+# Ulrich Drepper <drepper@cygnus.com>, 1996.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check whether LC_MESSAGES is available in <locale.h>.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check to see if we're running under Cygwin32, without using
+# AC_CANONICAL_*.  If so, set output variable CYGWIN32 to "yes".
+# Otherwise set it to "no".
+
+
+
+# Check to see if we're running under Win32, without using
+# AC_CANONICAL_*.  If so, set output variable EXEEXT to ".exe".
+# Otherwise set it to "".
+
+
+
+
+
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.13 
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+ac_help="$ac_help
+  --disable-nls           do not use Native Language Support"
+ac_help="$ac_help
+  --with-included-gettext use the GNU gettext library included here"
+ac_help="$ac_help
+  --enable-maintainer-mode		Enable developer functionality."
+ac_help="$ac_help
+  --enable-sim-bswap			Use Host specific BSWAP instruction."
+ac_help="$ac_help
+  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator"
+ac_help="$ac_help
+  --enable-sim-debug=opts		Enable debugging flags"
+ac_help="$ac_help
+  --enable-sim-stdio			Specify whether to use stdio for console input/output."
+ac_help="$ac_help
+  --enable-sim-trace=opts		Enable tracing flags"
+ac_help="$ac_help
+  --enable-sim-profile=opts		Enable profiling flags"
+ac_help="$ac_help
+  --enable-sim-endian=endian		Specify target byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses."
+ac_help="$ac_help
+  --enable-sim-hostendian=end		Specify host byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-scache=size		Specify simulator execution cache size."
+ac_help="$ac_help
+  --enable-sim-default-model=model	Specify default model to simulate."
+ac_help="$ac_help
+  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment."
+ac_help="$ac_help
+  --enable-cgen-maint[=DIR]    build cgen generated files"
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+# Initialize some other variables.
+subdirs=
+MFLAGS= MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+# Maximum number of lines to put in a shell here document.
+ac_max_here_lines=12
+
+ac_prev=
+for ac_option
+do
+
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval "$ac_prev=\$ac_option"
+    ac_prev=
+    continue
+  fi
+
+  case "$ac_option" in
+  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
+  *) ac_optarg= ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case "$ac_option" in
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir="$ac_optarg" ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build="$ac_optarg" ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file="$ac_optarg" ;;
+
+  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+  | --da=*)
+    datadir="$ac_optarg" ;;
+
+  -disable-* | --disable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    eval "enable_${ac_feature}=no" ;;
+
+  -enable-* | --enable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "enable_${ac_feature}='$ac_optarg'" ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix="$ac_optarg" ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he)
+    # Omit some internal or obsolete options to make the list less imposing.
+    # This message is too long to be a string in the A/UX 3.1 sh.
+    cat << EOF
+Usage: configure [options] [host]
+Options: [defaults in brackets after descriptions]
+Configuration:
+  --cache-file=FILE       cache test results in FILE
+  --help                  print this message
+  --no-create             do not create output files
+  --quiet, --silent       do not print \`checking...' messages
+  --version               print the version of autoconf that created configure
+Directory and file names:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [same as prefix]
+  --bindir=DIR            user executables in DIR [EPREFIX/bin]
+  --sbindir=DIR           system admin executables in DIR [EPREFIX/sbin]
+  --libexecdir=DIR        program executables in DIR [EPREFIX/libexec]
+  --datadir=DIR           read-only architecture-independent data in DIR
+                          [PREFIX/share]
+  --sysconfdir=DIR        read-only single-machine data in DIR [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data in DIR
+                          [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data in DIR [PREFIX/var]
+  --libdir=DIR            object code libraries in DIR [EPREFIX/lib]
+  --includedir=DIR        C header files in DIR [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc in DIR [/usr/include]
+  --infodir=DIR           info documentation in DIR [PREFIX/info]
+  --mandir=DIR            man documentation in DIR [PREFIX/man]
+  --srcdir=DIR            find the sources in DIR [configure dir or ..]
+  --program-prefix=PREFIX prepend PREFIX to installed program names
+  --program-suffix=SUFFIX append SUFFIX to installed program names
+  --program-transform-name=PROGRAM
+                          run sed PROGRAM on installed program names
+EOF
+    cat << EOF
+Host type:
+  --build=BUILD           configure for building on BUILD [BUILD=HOST]
+  --host=HOST             configure for HOST [guessed]
+  --target=TARGET         configure for TARGET [TARGET=HOST]
+Features and packages:
+  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+  --x-includes=DIR        X include files are in DIR
+  --x-libraries=DIR       X library files are in DIR
+EOF
+    if test -n "$ac_help"; then
+      echo "--enable and --with options recognized:$ac_help"
+    fi
+    exit 0 ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host="$ac_optarg" ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir="$ac_optarg" ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir="$ac_optarg" ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir="$ac_optarg" ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir="$ac_optarg" ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst \
+  | --locals | --local | --loca | --loc | --lo)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+    localstatedir="$ac_optarg" ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir="$ac_optarg" ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir="$ac_optarg" ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix="$ac_optarg" ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix="$ac_optarg" ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix="$ac_optarg" ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name="$ac_optarg" ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir="$ac_optarg" ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir="$ac_optarg" ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site="$ac_optarg" ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir="$ac_optarg" ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir="$ac_optarg" ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target="$ac_optarg" ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers)
+    echo "configure generated by autoconf version 2.13"
+    exit 0 ;;
+
+  -with-* | --with-*)
+    ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "with_${ac_package}='$ac_optarg'" ;;
+
+  -without-* | --without-*)
+    ac_package=`echo $ac_option|sed -e 's/-*without-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    eval "with_${ac_package}=no" ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes="$ac_optarg" ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries="$ac_optarg" ;;
+
+  -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
+    ;;
+
+  *)
+    if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
+      echo "configure: warning: $ac_option: invalid host type" 1>&2
+    fi
+    if test "x$nonopt" != xNONE; then
+      { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
+    fi
+    nonopt="$ac_option"
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
+fi
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+# File descriptor usage:
+# 0 standard input
+# 1 file creation
+# 2 errors and warnings
+# 3 some systems may open it to /dev/tty
+# 4 used on the Kubota Titan
+# 6 checking for... messages and results
+# 5 compiler messages saved in config.log
+if test "$silent" = yes; then
+  exec 6>/dev/null
+else
+  exec 6>&1
+fi
+exec 5>./config.log
+
+echo "\
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+" 1>&5
+
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Also quote any args containing shell metacharacters.
+ac_configure_args=
+for ac_arg
+do
+  case "$ac_arg" in
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c) ;;
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
+  *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
+  ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+  *) ac_configure_args="$ac_configure_args $ac_arg" ;;
+  esac
+done
+
+# NLS nuisances.
+# Only set these to C if already set.  These must not be set unconditionally
+# because not all systems understand e.g. LANG=C (notably SCO).
+# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
+# Non-C LC_CTYPE values break the ctype check.
+if test "${LANG+set}"   = set; then LANG=C;   export LANG;   fi
+if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
+if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
+if test "${LC_CTYPE+set}"    = set; then LC_CTYPE=C;    export LC_CTYPE;    fi
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo > confdefs.h
+
+# A filename unique to this package, relative to the directory that
+# configure is in, which we can look for to find out if srcdir is correct.
+ac_unique_file=Makefile.in
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then its parent.
+  ac_prog=$0
+  ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+  test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+  srcdir=$ac_confdir
+  if test ! -r $srcdir/$ac_unique_file; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+  if test "$ac_srcdir_defaulted" = yes; then
+    { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+  else
+    { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+  fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+  if test "x$prefix" != xNONE; then
+    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+  else
+    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+  fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+  if test -r "$ac_site_file"; then
+    echo "loading site script $ac_site_file"
+    . "$ac_site_file"
+  fi
+done
+
+if test -r "$cache_file"; then
+  echo "loading cache $cache_file"
+  . $cache_file
+else
+  echo "creating cache $cache_file"
+  > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+ac_exeext=
+ac_objext=o
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+  # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+  if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+    ac_n= ac_c='
+' ac_t='	'
+  else
+    ac_n=-n ac_c= ac_t=
+  fi
+else
+  ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:693: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    # This must be in double quotes, not single quotes, because CPP may get
+  # substituted into the Makefile and "${CC-cc}" will confuse make.
+  CPP="${CC-cc} -E"
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp.
+  cat > conftest.$ac_ext <<EOF
+#line 708 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:714: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -E -traditional-cpp"
+  cat > conftest.$ac_ext <<EOF
+#line 725 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:731: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -nologo -E"
+  cat > conftest.$ac_ext <<EOF
+#line 742 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:748: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+  ac_cv_prog_CPP="$CPP"
+fi
+  CPP="$ac_cv_prog_CPP"
+else
+  ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
+echo "configure:773: checking whether ${MAKE-make} sets \${MAKE}" >&5
+set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftestmake <<\EOF
+all:
+	@echo 'ac_maketemp="${MAKE}"'
+EOF
+# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`
+if test -n "$ac_maketemp"; then
+  eval ac_cv_prog_make_${ac_make}_set=yes
+else
+  eval ac_cv_prog_make_${ac_make}_set=no
+fi
+rm -f conftestmake
+fi
+if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  SET_MAKE=
+else
+  echo "$ac_t""no" 1>&6
+  SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
+echo "configure:800: checking for POSIXized ISC" >&5
+if test -d /etc/conf/kconfig.d &&
+  grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1
+then
+  echo "$ac_t""yes" 1>&6
+  ISC=yes # If later tests want to check for ISC.
+  cat >> confdefs.h <<\EOF
+#define _POSIX_SOURCE 1
+EOF
+
+  if test "$GCC" = yes; then
+    CC="$CC -posix"
+  else
+    CC="$CC -Xp"
+  fi
+else
+  echo "$ac_t""no" 1>&6
+  ISC=
+fi
+
+echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
+echo "configure:821: checking for ANSI C header files" >&5
+if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 826 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:834: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  ac_cv_header_stdc=yes
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 851 "configure"
+#include "confdefs.h"
+#include <string.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "memchr" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 869 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "free" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+if test "$cross_compiling" = yes; then
+  :
+else
+  cat > conftest.$ac_ext <<EOF
+#line 890 "configure"
+#include "confdefs.h"
+#include <ctype.h>
+#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int main () { int i; for (i = 0; i < 256; i++)
+if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
+exit (0); }
+
+EOF
+if { (eval echo configure:901: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  :
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_header_stdc=no
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_header_stdc" 1>&6
+if test $ac_cv_header_stdc = yes; then
+  cat >> confdefs.h <<\EOF
+#define STDC_HEADERS 1
+EOF
+
+fi
+
+echo $ac_n "checking for working const""... $ac_c" 1>&6
+echo "configure:925: checking for working const" >&5
+if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 930 "configure"
+#include "confdefs.h"
+
+int main() {
+
+/* Ultrix mips cc rejects this.  */
+typedef int charset[2]; const charset x;
+/* SunOS 4.1.1 cc rejects this.  */
+char const *const *ccp;
+char **p;
+/* NEC SVR4.0.2 mips cc rejects this.  */
+struct point {int x, y;};
+static struct point const zero = {0,0};
+/* AIX XL C 1.02.0.0 rejects this.
+   It does not let you subtract one const X* pointer from another in an arm
+   of an if-expression whose if-part is not a constant expression */
+const char *g = "string";
+ccp = &g + (g ? g-g : 0);
+/* HPUX 7.0 cc rejects these. */
+++ccp;
+p = (char**) ccp;
+ccp = (char const *const *) p;
+{ /* SCO 3.2v4 cc rejects this.  */
+  char *t;
+  char const *s = 0 ? (char *) 0 : (char const *) 0;
+
+  *t++ = 0;
+}
+{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
+  int x[] = {25, 17};
+  const int *foo = &x[0];
+  ++foo;
+}
+{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
+  typedef const int *iptr;
+  iptr p = 0;
+  ++p;
+}
+{ /* AIX XL C 1.02.0.0 rejects this saying
+     "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
+  struct s { int j; const int *ap[3]; };
+  struct s *b; b->j = 5;
+}
+{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
+  const int foo = 10;
+}
+
+; return 0; }
+EOF
+if { (eval echo configure:979: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_const=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_const=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_c_const" 1>&6
+if test $ac_cv_c_const = no; then
+  cat >> confdefs.h <<\EOF
+#define const 
+EOF
+
+fi
+
+echo $ac_n "checking for inline""... $ac_c" 1>&6
+echo "configure:1000: checking for inline" >&5
+if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_inline=no
+for ac_kw in inline __inline__ __inline; do
+  cat > conftest.$ac_ext <<EOF
+#line 1007 "configure"
+#include "confdefs.h"
+
+int main() {
+} $ac_kw foo() {
+; return 0; }
+EOF
+if { (eval echo configure:1014: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_inline=$ac_kw; break
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+done
+
+fi
+
+echo "$ac_t""$ac_cv_c_inline" 1>&6
+case "$ac_cv_c_inline" in
+  inline | yes) ;;
+  no) cat >> confdefs.h <<\EOF
+#define inline 
+EOF
+ ;;
+  *)  cat >> confdefs.h <<EOF
+#define inline $ac_cv_c_inline
+EOF
+ ;;
+esac
+
+echo $ac_n "checking for off_t""... $ac_c" 1>&6
+echo "configure:1040: checking for off_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1045 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_off_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_off_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_off_t" 1>&6
+if test $ac_cv_type_off_t = no; then
+  cat >> confdefs.h <<\EOF
+#define off_t long
+EOF
+
+fi
+
+echo $ac_n "checking for size_t""... $ac_c" 1>&6
+echo "configure:1073: checking for size_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1078 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_size_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_size_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_size_t" 1>&6
+if test $ac_cv_type_size_t = no; then
+  cat >> confdefs.h <<\EOF
+#define size_t unsigned
+EOF
+
+fi
+
+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
+# for constant arguments.  Useless!
+echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
+echo "configure:1108: checking for working alloca.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1113 "configure"
+#include "confdefs.h"
+#include <alloca.h>
+int main() {
+char *p = alloca(2 * sizeof(int));
+; return 0; }
+EOF
+if { (eval echo configure:1120: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_header_alloca_h=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_alloca_h=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
+if test $ac_cv_header_alloca_h = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA_H 1
+EOF
+
+fi
+
+echo $ac_n "checking for alloca""... $ac_c" 1>&6
+echo "configure:1141: checking for alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1146 "configure"
+#include "confdefs.h"
+
+#ifdef __GNUC__
+# define alloca __builtin_alloca
+#else
+# ifdef _MSC_VER
+#  include <malloc.h>
+#  define alloca _alloca
+# else
+#  if HAVE_ALLOCA_H
+#   include <alloca.h>
+#  else
+#   ifdef _AIX
+ #pragma alloca
+#   else
+#    ifndef alloca /* predefined by HP cc +Olibcalls */
+char *alloca ();
+#    endif
+#   endif
+#  endif
+# endif
+#endif
+
+int main() {
+char *p = (char *) alloca(1);
+; return 0; }
+EOF
+if { (eval echo configure:1174: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_func_alloca_works=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_func_alloca_works=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
+if test $ac_cv_func_alloca_works = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA 1
+EOF
+
+fi
+
+if test $ac_cv_func_alloca_works = no; then
+  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
+  # that cause trouble.  Some versions do not even contain alloca or
+  # contain a buggy version.  If you still want to use their alloca,
+  # use ar to extract alloca.o from them instead of compiling alloca.c.
+  ALLOCA=alloca.${ac_objext}
+  cat >> confdefs.h <<\EOF
+#define C_ALLOCA 1
+EOF
+
+
+echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
+echo "configure:1206: checking whether alloca needs Cray hooks" >&5
+if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1211 "configure"
+#include "confdefs.h"
+#if defined(CRAY) && ! defined(CRAY2)
+webecray
+#else
+wenotbecray
+#endif
+
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "webecray" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_os_cray=yes
+else
+  rm -rf conftest*
+  ac_cv_os_cray=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_os_cray" 1>&6
+if test $ac_cv_os_cray = yes; then
+for ac_func in _getb67 GETB67 getb67; do
+  echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1236: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1241 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1264: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  cat >> confdefs.h <<EOF
+#define CRAY_STACKSEG_END $ac_func
+EOF
+
+  break
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+done
+fi
+
+echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
+echo "configure:1291: checking stack direction for C alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_c_stack_direction=0
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1299 "configure"
+#include "confdefs.h"
+find_stack_direction ()
+{
+  static char *addr = 0;
+  auto char dummy;
+  if (addr == 0)
+    {
+      addr = &dummy;
+      return find_stack_direction ();
+    }
+  else
+    return (&dummy > addr) ? 1 : -1;
+}
+main ()
+{
+  exit (find_stack_direction() < 0);
+}
+EOF
+if { (eval echo configure:1318: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_stack_direction=1
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_stack_direction=-1
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
+cat >> confdefs.h <<EOF
+#define STACK_DIRECTION $ac_cv_c_stack_direction
+EOF
+
+fi
+
+for ac_hdr in unistd.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1343: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1348 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1353: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getpagesize
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1382: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1387 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1410: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+echo $ac_n "checking for working mmap""... $ac_c" 1>&6
+echo "configure:1435: checking for working mmap" >&5
+if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_func_mmap_fixed_mapped=no
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1443 "configure"
+#include "confdefs.h"
+
+/* Thanks to Mike Haertel and Jim Avera for this test.
+   Here is a matrix of mmap possibilities:
+	mmap private not fixed
+	mmap private fixed at somewhere currently unmapped
+	mmap private fixed at somewhere already mapped
+	mmap shared not fixed
+	mmap shared fixed at somewhere currently unmapped
+	mmap shared fixed at somewhere already mapped
+   For private mappings, we should verify that changes cannot be read()
+   back from the file, nor mmap's back from the file at a different
+   address.  (There have been systems where private was not correctly
+   implemented like the infamous i386 svr4.0, and systems where the
+   VM page cache was not coherent with the filesystem buffer cache
+   like early versions of FreeBSD and possibly contemporary NetBSD.)
+   For shared mappings, we should conversely verify that changes get
+   propogated back to all the places they're supposed to be.
+
+   Grep wants private fixed already mapped.
+   The main things grep needs to know about mmap are:
+   * does it exist and is it safe to write into the mmap'd area
+   * how to use it (BSD variants)  */
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+/* This mess was copied from the GNU getpagesize.h.  */
+#ifndef HAVE_GETPAGESIZE
+# ifdef HAVE_UNISTD_H
+#  include <unistd.h>
+# endif
+
+/* Assume that all systems that can run configure have sys/param.h.  */
+# ifndef HAVE_SYS_PARAM_H
+#  define HAVE_SYS_PARAM_H 1
+# endif
+
+# ifdef _SC_PAGESIZE
+#  define getpagesize() sysconf(_SC_PAGESIZE)
+# else /* no _SC_PAGESIZE */
+#  ifdef HAVE_SYS_PARAM_H
+#   include <sys/param.h>
+#   ifdef EXEC_PAGESIZE
+#    define getpagesize() EXEC_PAGESIZE
+#   else /* no EXEC_PAGESIZE */
+#    ifdef NBPG
+#     define getpagesize() NBPG * CLSIZE
+#     ifndef CLSIZE
+#      define CLSIZE 1
+#     endif /* no CLSIZE */
+#    else /* no NBPG */
+#     ifdef NBPC
+#      define getpagesize() NBPC
+#     else /* no NBPC */
+#      ifdef PAGESIZE
+#       define getpagesize() PAGESIZE
+#      endif /* PAGESIZE */
+#     endif /* no NBPC */
+#    endif /* no NBPG */
+#   endif /* no EXEC_PAGESIZE */
+#  else /* no HAVE_SYS_PARAM_H */
+#   define getpagesize() 8192	/* punt totally */
+#  endif /* no HAVE_SYS_PARAM_H */
+# endif /* no _SC_PAGESIZE */
+
+#endif /* no HAVE_GETPAGESIZE */
+
+#ifdef __cplusplus
+extern "C" { void *malloc(unsigned); }
+#else
+char *malloc();
+#endif
+
+int
+main()
+{
+	char *data, *data2, *data3;
+	int i, pagesize;
+	int fd;
+
+	pagesize = getpagesize();
+
+	/*
+	 * First, make a file with some known garbage in it.
+	 */
+	data = malloc(pagesize);
+	if (!data)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		*(data + i) = rand();
+	umask(0);
+	fd = creat("conftestmmap", 0600);
+	if (fd < 0)
+		exit(1);
+	if (write(fd, data, pagesize) != pagesize)
+		exit(1);
+	close(fd);
+
+	/*
+	 * Next, try to mmap the file at a fixed address which
+	 * already has something else allocated at it.  If we can,
+	 * also make sure that we see the same garbage.
+	 */
+	fd = open("conftestmmap", O_RDWR);
+	if (fd < 0)
+		exit(1);
+	data2 = malloc(2 * pagesize);
+	if (!data2)
+		exit(1);
+	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
+	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
+	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data2 + i))
+			exit(1);
+
+	/*
+	 * Finally, make sure that changes to the mapped area
+	 * do not percolate back to the file as seen by read().
+	 * (This is a bug on some variants of i386 svr4.0.)
+	 */
+	for (i = 0; i < pagesize; ++i)
+		*(data2 + i) = *(data2 + i) + 1;
+	data3 = malloc(pagesize);
+	if (!data3)
+		exit(1);
+	if (read(fd, data3, pagesize) != pagesize)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data3 + i))
+			exit(1);
+	close(fd);
+	unlink("conftestmmap");
+	exit(0);
+}
+
+EOF
+if { (eval echo configure:1583: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_func_mmap_fixed_mapped=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_func_mmap_fixed_mapped=no
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
+if test $ac_cv_func_mmap_fixed_mapped = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_MMAP 1
+EOF
+
+fi
+
+
+# autoconf.info says this should be called right after AC_INIT.
+
+
+ac_aux_dir=
+for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do
+  if test -f $ac_dir/install-sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f $ac_dir/install.sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  fi
+done
+if test -z "$ac_aux_dir"; then
+  { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; }
+fi
+ac_config_guess=$ac_aux_dir/config.guess
+ac_config_sub=$ac_aux_dir/config.sub
+ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
+
+
+# Do some error checking and defaulting for the host and target type.
+# The inputs are:
+#    configure --host=HOST --target=TARGET --build=BUILD NONOPT
+#
+# The rules are:
+# 1. You are not allowed to specify --host, --target, and nonopt at the
+#    same time.
+# 2. Host defaults to nonopt.
+# 3. If nonopt is not specified, then host defaults to the current host,
+#    as determined by config.guess.
+# 4. Target and build default to nonopt.
+# 5. If nonopt is not specified, then target and build default to host.
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+case $host---$target---$nonopt in
+NONE---*---* | *---NONE---* | *---*---NONE) ;;
+*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
+esac
+
+
+# Make sure we can run config.sub.
+if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
+else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking host system type""... $ac_c" 1>&6
+echo "configure:1656: checking host system type" >&5
+
+host_alias=$host
+case "$host_alias" in
+NONE)
+  case $nonopt in
+  NONE)
+    if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
+    else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
+    fi ;;
+  *) host_alias=$nonopt ;;
+  esac ;;
+esac
+
+host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
+host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$host" 1>&6
+
+echo $ac_n "checking target system type""... $ac_c" 1>&6
+echo "configure:1677: checking target system type" >&5
+
+target_alias=$target
+case "$target_alias" in
+NONE)
+  case $nonopt in
+  NONE) target_alias=$host_alias ;;
+  *) target_alias=$nonopt ;;
+  esac ;;
+esac
+
+target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
+target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$target" 1>&6
+
+echo $ac_n "checking build system type""... $ac_c" 1>&6
+echo "configure:1695: checking build system type" >&5
+
+build_alias=$build
+case "$build_alias" in
+NONE)
+  case $nonopt in
+  NONE) build_alias=$host_alias ;;
+  *) build_alias=$nonopt ;;
+  esac ;;
+esac
+
+build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
+build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$build" 1>&6
+
+test "$host_alias" != "$target_alias" &&
+  test "$program_prefix$program_suffix$program_transform_name" = \
+    NONENONEs,x,x, &&
+  program_prefix=${target_alias}-
+
+if test "$program_transform_name" = s,x,x,; then
+  program_transform_name=
+else
+  # Double any \ or $.  echo might interpret backslashes.
+  cat <<\EOF_SED > conftestsed
+s,\\,\\\\,g; s,\$,$$,g
+EOF_SED
+  program_transform_name="`echo $program_transform_name|sed -f conftestsed`"
+  rm -f conftestsed
+fi
+test "$program_prefix" != NONE &&
+  program_transform_name="s,^,${program_prefix},; $program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+  program_transform_name="s,\$\$,${program_suffix},; $program_transform_name"
+
+# sed with no file args requires a program.
+test "$program_transform_name" = "" && program_transform_name="s,x,x,"
+
+# Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1739: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="gcc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1769: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_prog_rejected=no
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+        ac_prog_rejected=yes
+	continue
+      fi
+      ac_cv_prog_CC="cc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# -gt 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    set dummy "$ac_dir/$ac_word" "$@"
+    shift
+    ac_cv_prog_CC="$@"
+  fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+  if test -z "$CC"; then
+    case "`uname -s`" in
+    *win32* | *WIN32*)
+      # Extract the first word of "cl", so it can be a program name with args.
+set dummy cl; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1820: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="cl"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+ ;;
+    esac
+  fi
+  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:1852: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext << EOF
+
+#line 1863 "configure"
+#include "confdefs.h"
+
+main(){return(0);}
+EOF
+if { (eval echo configure:1868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  ac_cv_prog_cc_works=yes
+  # If we can't run a trivial program, we are probably using a cross compiler.
+  if (./conftest; exit) 2>/dev/null; then
+    ac_cv_prog_cc_cross=no
+  else
+    ac_cv_prog_cc_cross=yes
+  fi
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:1894: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:1899: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.c <<EOF
+#ifdef __GNUC__
+  yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1908: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+  ac_cv_prog_gcc=yes
+else
+  ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+
+ac_test_CFLAGS="${CFLAGS+set}"
+ac_save_CFLAGS="$CFLAGS"
+CFLAGS=
+echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:1927: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+  ac_cv_prog_cc_g=yes
+else
+  ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS="$ac_save_CFLAGS"
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+
+# Find a good install program.  We prefer a C program (faster),
+# so one script is as good as another.  But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# ./install, which can be erroneously created by make from ./install.sh.
+echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
+echo "configure:1970: checking for a BSD compatible install" >&5
+if test -z "$INSTALL"; then
+if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    IFS="${IFS= 	}"; ac_save_IFS="$IFS"; IFS=":"
+  for ac_dir in $PATH; do
+    # Account for people who put trailing slashes in PATH elements.
+    case "$ac_dir/" in
+    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
+    *)
+      # OSF1 and SCO ODT 3.0 have their own names for install.
+      # Don't use installbsd from OSF since it installs stuff as root
+      # by default.
+      for ac_prog in ginstall scoinst install; do
+        if test -f $ac_dir/$ac_prog; then
+	  if test $ac_prog = install &&
+            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
+	    # AIX install.  It has an incompatible calling convention.
+	    :
+	  else
+	    ac_cv_path_install="$ac_dir/$ac_prog -c"
+	    break 2
+	  fi
+	fi
+      done
+      ;;
+    esac
+  done
+  IFS="$ac_save_IFS"
+
+fi
+  if test "${ac_cv_path_install+set}" = set; then
+    INSTALL="$ac_cv_path_install"
+  else
+    # As a last resort, use the slow shell script.  We don't cache a
+    # path for INSTALL within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the path is relative.
+    INSTALL="$ac_install_sh"
+  fi
+fi
+echo "$ac_t""$INSTALL" 1>&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+  CC_FOR_BUILD='$(CC)'
+else
+  CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+# Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2038: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+ALL_LINGUAS=
+                              
+   for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
+unistd.h values.h sys/param.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2073: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2078 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2083: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
+__argz_count __argz_stringify __argz_next
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2113: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2118 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2141: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+   if test "${ac_cv_func_stpcpy+set}" != "set"; then
+     for ac_func in stpcpy
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2170: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2175 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2198: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   fi
+   if test "${ac_cv_func_stpcpy}" = "yes"; then
+     cat >> confdefs.h <<\EOF
+#define HAVE_STPCPY 1
+EOF
+
+   fi
+
+   if test $ac_cv_header_locale_h = yes; then
+    echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
+echo "configure:2232: checking for LC_MESSAGES" >&5
+if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2237 "configure"
+#include "confdefs.h"
+#include <locale.h>
+int main() {
+return LC_MESSAGES
+; return 0; }
+EOF
+if { (eval echo configure:2244: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
+    if test $am_cv_val_LC_MESSAGES = yes; then
+      cat >> confdefs.h <<\EOF
+#define HAVE_LC_MESSAGES 1
+EOF
+
+    fi
+  fi
+   echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
+echo "configure:2265: checking whether NLS is requested" >&5
+        # Check whether --enable-nls or --disable-nls was given.
+if test "${enable_nls+set}" = set; then
+  enableval="$enable_nls"
+  USE_NLS=$enableval
+else
+  USE_NLS=yes
+fi
+
+    echo "$ac_t""$USE_NLS" 1>&6
+    
+
+    USE_INCLUDED_LIBINTL=no
+
+        if test "$USE_NLS" = "yes"; then
+      cat >> confdefs.h <<\EOF
+#define ENABLE_NLS 1
+EOF
+
+      echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
+echo "configure:2285: checking whether included gettext is requested" >&5
+      # Check whether --with-included-gettext or --without-included-gettext was given.
+if test "${with_included_gettext+set}" = set; then
+  withval="$with_included_gettext"
+  nls_cv_force_use_gnu_gettext=$withval
+else
+  nls_cv_force_use_gnu_gettext=no
+fi
+
+      echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
+
+      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
+      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
+                        		nls_cv_header_intl=
+	nls_cv_header_libgt=
+	CATOBJEXT=NONE
+
+	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
+echo "configure:2304: checking for libintl.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2309 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2314: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
+echo "configure:2331: checking for gettext in libc" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2336 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2343: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
+
+	   if test "$gt_cv_func_gettext_libc" != "yes"; then
+	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
+echo "configure:2359: checking for bindtextdomain in -lintl" >&5
+ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lintl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 2367 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bindtextdomain();
+
+int main() {
+bindtextdomain()
+; return 0; }
+EOF
+if { (eval echo configure:2378: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
+echo "configure:2394: checking for gettext in libintl" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2399 "configure"
+#include "confdefs.h"
+
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2406: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+	   fi
+
+	   if test "$gt_cv_func_gettext_libc" = "yes" \
+	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
+	      cat >> confdefs.h <<\EOF
+#define HAVE_GETTEXT 1
+EOF
+
+	      # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2434: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+	      if test "$MSGFMT" != "no"; then
+		for ac_func in dcgettext
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2468: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2473 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2496: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+		# Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2523: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		# Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2559: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		cat > conftest.$ac_ext <<EOF
+#line 2591 "configure"
+#include "confdefs.h"
+
+int main() {
+extern int _nl_msg_cat_cntr;
+			       return _nl_msg_cat_cntr
+; return 0; }
+EOF
+if { (eval echo configure:2599: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  CATOBJEXT=.gmo
+		   DATADIRNAME=share
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CATOBJEXT=.mo
+		   DATADIRNAME=lib
+fi
+rm -f conftest*
+		INSTOBJEXT=.mo
+	      fi
+	    fi
+	
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+	        
+        if test "$CATOBJEXT" = "NONE"; then
+	  	  	  nls_cv_use_gnu_gettext=yes
+        fi
+      fi
+
+      if test "$nls_cv_use_gnu_gettext" = "yes"; then
+                INTLOBJS="\$(GETTOBJS)"
+        # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2631: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2665: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2701: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        
+	USE_INCLUDED_LIBINTL=yes
+        CATOBJEXT=.gmo
+        INSTOBJEXT=.mo
+        DATADIRNAME=share
+	INTLDEPS='$(top_builddir)/../intl/libintl.a'
+	INTLLIBS=$INTLDEPS
+	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
+        nls_cv_header_intl=libintl.h
+        nls_cv_header_libgt=libgettext.h
+      fi
+
+            if test "$XGETTEXT" != ":"; then
+			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
+	  : ;
+	else
+	  echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
+	  XGETTEXT=":"
+	fi
+      fi
+
+      # We need to process the po/ directory.
+      POSUB=po
+    else
+      DATADIRNAME=share
+      nls_cv_header_intl=libintl.h
+      nls_cv_header_libgt=libgettext.h
+    fi
+
+    # If this is used in GNU gettext we have to set USE_NLS to `yes'
+    # because some of the sources are only built for this goal.
+    if test "$PACKAGE" = gettext; then
+      USE_NLS=yes
+      USE_INCLUDED_LIBINTL=yes
+    fi
+
+                for lang in $ALL_LINGUAS; do
+      GMOFILES="$GMOFILES $lang.gmo"
+      POFILES="$POFILES $lang.po"
+    done
+
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
+   if test "x$CATOBJEXT" != "x"; then
+     if test "x$ALL_LINGUAS" = "x"; then
+       LINGUAS=
+     else
+       echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
+echo "configure:2791: checking for catalogs to be installed" >&5
+       NEW_LINGUAS=
+       for lang in ${LINGUAS=$ALL_LINGUAS}; do
+         case "$ALL_LINGUAS" in
+          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
+         esac
+       done
+       LINGUAS=$NEW_LINGUAS
+       echo "$ac_t""$LINGUAS" 1>&6
+     fi
+
+          if test -n "$LINGUAS"; then
+       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
+     fi
+   fi
+
+            if test $ac_cv_header_locale_h = yes; then
+     INCLUDE_LOCALE_H="#include <locale.h>"
+   else
+     INCLUDE_LOCALE_H="\
+/* The system does not provide the header <locale.h>.  Take care yourself.  */"
+   fi
+   
+
+            if test -f $srcdir/po2tbl.sed.in; then
+      if test "$CATOBJEXT" = ".cat"; then
+	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
+echo "configure:2819: checking for linux/version.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2824 "configure"
+#include "confdefs.h"
+#include <linux/version.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2829: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  msgformat=linux
+else
+  echo "$ac_t""no" 1>&6
+msgformat=xopen
+fi
+
+
+	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
+      fi
+            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
+	 $srcdir/po2tbl.sed.in > po2tbl.sed
+   fi
+
+            if test "$PACKAGE" = "gettext"; then
+     GT_NO="#NO#"
+     GT_YES=
+   else
+     GT_NO=
+     GT_YES="#YES#"
+   fi
+   
+   
+
+   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
+   
+
+      l=
+   
+
+            if test -d $srcdir/po; then
+      test -d po || mkdir po
+      if test "x$srcdir" != "x."; then
+	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
+	    posrcprefix="$srcdir/"
+	 else
+	    posrcprefix="../$srcdir/"
+	 fi
+      else
+	 posrcprefix="../"
+      fi
+      rm -f po/POTFILES
+      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
+	 < $srcdir/po/POTFILES.in > po/POTFILES
+   fi
+  
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2898: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2903 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2908: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in sys/time.h sys/resource.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2938: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2943 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2948: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in fcntl.h fpu_control.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2978: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2983 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2988: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in dlfcn.h errno.h sys/stat.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3018: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3023 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3028: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:3057: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3062 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:3085: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+# Check for socket libraries
+echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
+echo "configure:3112: checking for bind in -lsocket" >&5
+ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lsocket  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3120 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bind();
+
+int main() {
+bind()
+; return 0; }
+EOF
+if { (eval echo configure:3131: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lsocket $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
+echo "configure:3159: checking for gethostbyname in -lnsl" >&5
+ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lnsl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3167 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char gethostbyname();
+
+int main() {
+gethostbyname()
+; return 0; }
+EOF
+if { (eval echo configure:3178: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lnsl $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+  enableval="$enable_maintainer_mode"
+  case "${enableval}" in
+  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
+  no)	MAINT="#" ;;
+  *)	{ echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+  echo "Setting maintainer mode" 6>&1
+fi
+else
+  MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+  enableval="$enable_sim_bswap"
+  case "${enableval}" in
+  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+  no)	sim_bswap="-DWITH_BSWAP=0";;
+  *)	{ echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+  echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+  sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+  enableval="$enable_sim_cflags"
+  case "${enableval}" in
+  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
+  trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";;
+  no)	 sim_cflags="";;
+  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+  echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+  sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+  enableval="$enable_sim_debug"
+  case "${enableval}" in
+  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+  echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+  sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+  enableval="$enable_sim_stdio"
+  case "${enableval}" in
+  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+  *)	{ echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+  echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+  sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+  enableval="$enable_sim_trace"
+  case "${enableval}" in
+  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+  [-0-9]*)
+	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+  [a-z]*)
+	sim_trace=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_trace" = x; then
+	    sim_trace="-DWITH_TRACE='(TRACE_$x"
+	  else
+	    sim_trace="${sim_trace}|TRACE_$x"
+	  fi
+	done
+	sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+  echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+  sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+  enableval="$enable_sim_profile"
+  case "${enableval}" in
+  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+  [-0-9]*)
+	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+  [a-z]*)
+	sim_profile=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_profile" = x; then
+	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+	  else
+	    sim_profile="${sim_profile}|PROFILE_$x"
+	  fi
+	done
+	sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+  echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+  sim_profile=""
+fi
+
+
+
+echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
+echo "configure:3354: checking return type of signal handlers" >&5
+if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3359 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+#undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int main() {
+int i;
+; return 0; }
+EOF
+if { (eval echo configure:3376: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_type_signal=void
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_type_signal=int
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_type_signal" 1>&6
+cat >> confdefs.h <<EOF
+#define RETSIGTYPE $ac_cv_type_signal
+EOF
+
+
+
+echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
+echo "configure:3396: checking for executable suffix" >&5
+if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$CYGWIN32" = yes; then
+am_cv_exeext=.exe
+else
+cat > am_c_test.c << 'EOF'
+int main() {
+/* Nothing needed here */
+}
+EOF
+${CC-cc} -o am_c_test $CFLAGS $CPPFLAGS $LDFLAGS am_c_test.c $LIBS 1>&5
+am_cv_exeext=`ls am_c_test.* | grep -v am_c_test.c | sed -e s/am_c_test//`
+rm -f am_c_test*
+fi
+
+test x"${am_cv_exeext}" = x && am_cv_exeext=no
+fi
+EXEEXT=""
+test x"${am_cv_exeext}" != xno && EXEEXT=${am_cv_exeext}
+echo "$ac_t""${am_cv_exeext}" 1>&6
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+  sim_link_files=tconfig.in
+else
+  sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+
+wire_endian="BIG_ENDIAN"
+default_endian=""
+# Check whether --enable-sim-endian or --disable-sim-endian was given.
+if test "${enable_sim_endian+set}" = set; then
+  enableval="$enable_sim_endian"
+  case "${enableval}" in
+  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
+  yes)	 if test x"$wire_endian" != x; then
+	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+	 else
+           if test x"$default_endian" != x; then
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
+	   else
+	     echo "No hard-wired endian for target $target" 1>&6
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  no)	 if test x"$default_endian" != x; then
+	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+	 else
+	   if test x"$wire_endian" != x; then
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
+	   else
+	     echo "No default endian for target $target" 1>&6
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
+  echo "Setting endian flags = $sim_endian" 6>&1
+fi
+else
+  if test x"$default_endian" != x; then
+  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+else
+  if test x"$wire_endian" != x; then
+    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+  else
+    sim_endian=
+  fi
+fi
+fi
+
+wire_alignment="NONSTRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+  enableval="$enable_sim_alignment"
+  case "${enableval}" in
+  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+  yes) if test x"$wire_alignment" != x; then
+	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+       else
+         if test x"$default_alignment" != x; then
+           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+         else
+	   echo "No hard-wired alignment for target $target" 1>&6
+	   sim_alignment="-DWITH_ALIGNMENT=0"
+         fi
+       fi;;
+  no)  if test x"$default_alignment" != x; then
+	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+       else
+         if test x"$wire_alignment" != x; then
+	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+         else
+           echo "No default alignment for target $target" 1>&6
+           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+         fi
+       fi;;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+  echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+  if test x"$default_alignment" != x; then
+  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+  if test x"$wire_alignment" != x; then
+    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+  else
+    sim_alignment=
+  fi
+fi
+fi
+
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+  enableval="$enable_sim_hostendian"
+  case "${enableval}" in
+  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+  echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+  
+if test "x$cross_compiling" = "xno"; then
+  echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
+echo "configure:3550: checking whether byte ordering is bigendian" >&5
+if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_bigendian=unknown
+# See if sys/param.h defines the BYTE_ORDER macro.
+cat > conftest.$ac_ext <<EOF
+#line 3557 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3568: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  # It does; now see whether it defined to BIG_ENDIAN or not.
+cat > conftest.$ac_ext <<EOF
+#line 3572 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3583: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_bigendian=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_bigendian=no
+fi
+rm -f conftest*
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+if test $ac_cv_c_bigendian = unknown; then
+if test "$cross_compiling" = yes; then
+    { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3603 "configure"
+#include "confdefs.h"
+main () {
+  /* Are we little or big endian?  From Harbison&Steele.  */
+  union
+  {
+    long l;
+    char c[sizeof (long)];
+  } u;
+  u.l = 1;
+  exit (u.c[sizeof (long) - 1] == 1);
+}
+EOF
+if { (eval echo configure:3616: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_bigendian=no
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_bigendian=yes
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_c_bigendian" 1>&6
+if test $ac_cv_c_bigendian = yes; then
+  cat >> confdefs.h <<\EOF
+#define WORDS_BIGENDIAN 1
+EOF
+
+fi
+
+  if test $ac_cv_c_bigendian = yes; then
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+  else
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+  fi
+else
+  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi
+
+
+default_sim_scache="16384"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+  enableval="$enable_sim_scache"
+  case "${enableval}" in
+  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+  no)	sim_scache="-DWITH_SCACHE=0" ;;
+  [0-9]*) sim_cache=${enableval};;
+  *)	{ echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; };
+	sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+  echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+  sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi
+
+
+
+default_sim_default_model="fr30-1"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+  enableval="$enable_sim_default_model"
+  case "${enableval}" in
+  yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };;
+  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+  echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi
+
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+  enableval="$enable_sim_environment"
+  case "${enableval}" in
+  all | ALL)             sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+  user | USER)           sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+  virtual | VIRTUAL)     sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+  operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; };
+       sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+  echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+  sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi
+
+
+cgen_maint=no
+cgen=../../cgen/cgen
+cgendir='$(srcdir)/../../cgen'
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+  enableval="$enable_cgen_maint"
+  case "${enableval}" in
+  yes)	cgen_maint=yes ;;
+  no)	cgen_maint=no ;;
+  *)
+	# argument is cgen install directory (not implemented yet).
+	# Having a `share' directory might be more appropriate for the .scm,
+	# .cpu, etc. files.
+	cgendir=${cgen_maint}/lib/cgen
+	cgen=${cgendir}/bin/cgen
+	;;
+esac
+fi
+if test x${cgen_maint} != xno ; then
+  CGEN_MAINT=''
+else
+  CGEN_MAINT='#'
+fi
+
+
+
+
+
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs.  It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already.  You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+  case `(ac_space=' '; set | grep ac_space) 2>&1` in
+  *ac_space=\ *)
+    # `set' does not quote correctly, so add quotes (double-quote substitution
+    # turns \\\\ into \\, and sed turns \\ into \).
+    sed -n \
+      -e "s/'/'\\\\''/g" \
+      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+    ;;
+  *)
+    # `set' quotes correctly as required by POSIX, so do not add quotes.
+    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+    ;;
+  esac >> confcache
+if cmp -s $cache_file confcache; then
+  :
+else
+  if test -w $cache_file; then
+    echo "updating cache $cache_file"
+    cat confcache > $cache_file
+  else
+    echo "not updating unwritable cache $cache_file"
+  fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+DEFS=-DHAVE_CONFIG_H
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+  case "\$ac_option" in
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+    echo "$CONFIG_STATUS generated by autoconf version 2.13"
+    exit 0 ;;
+  -help | --help | --hel | --he | --h)
+    echo "\$ac_cs_usage"; exit 0 ;;
+  *) echo "\$ac_cs_usage"; exit 1 ;;
+  esac
+done
+
+ac_given_srcdir=$srcdir
+ac_given_INSTALL="$INSTALL"
+
+trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@sim_environment@%$sim_environment%g
+s%@sim_alignment@%$sim_alignment%g
+s%@sim_assert@%$sim_assert%g
+s%@sim_bitsize@%$sim_bitsize%g
+s%@sim_endian@%$sim_endian%g
+s%@sim_hostendian@%$sim_hostendian%g
+s%@sim_float@%$sim_float%g
+s%@sim_scache@%$sim_scache%g
+s%@sim_default_model@%$sim_default_model%g
+s%@sim_hw_cflags@%$sim_hw_cflags%g
+s%@sim_hw_objs@%$sim_hw_objs%g
+s%@sim_hw@%$sim_hw%g
+s%@sim_inline@%$sim_inline%g
+s%@sim_packages@%$sim_packages%g
+s%@sim_regparm@%$sim_regparm%g
+s%@sim_reserved_bits@%$sim_reserved_bits%g
+s%@sim_smp@%$sim_smp%g
+s%@sim_stdcall@%$sim_stdcall%g
+s%@sim_xor_endian@%$sim_xor_endian%g
+s%@build_warnings@%$build_warnings%g
+s%@SHELL@%$SHELL%g
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@FFLAGS@%$FFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@host@%$host%g
+s%@host_alias@%$host_alias%g
+s%@host_cpu@%$host_cpu%g
+s%@host_vendor@%$host_vendor%g
+s%@host_os@%$host_os%g
+s%@target@%$target%g
+s%@target_alias@%$target_alias%g
+s%@target_cpu@%$target_cpu%g
+s%@target_vendor@%$target_vendor%g
+s%@target_os@%$target_os%g
+s%@build@%$build%g
+s%@build_alias@%$build_alias%g
+s%@build_cpu@%$build_cpu%g
+s%@build_vendor@%$build_vendor%g
+s%@build_os@%$build_os%g
+s%@CC@%$CC%g
+s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
+s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
+s%@INSTALL_DATA@%$INSTALL_DATA%g
+s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
+s%@HDEFINES@%$HDEFINES%g
+s%@AR@%$AR%g
+s%@RANLIB@%$RANLIB%g
+s%@SET_MAKE@%$SET_MAKE%g
+s%@CPP@%$CPP%g
+s%@ALLOCA@%$ALLOCA%g
+s%@USE_NLS@%$USE_NLS%g
+s%@MSGFMT@%$MSGFMT%g
+s%@GMSGFMT@%$GMSGFMT%g
+s%@XGETTEXT@%$XGETTEXT%g
+s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g
+s%@CATALOGS@%$CATALOGS%g
+s%@CATOBJEXT@%$CATOBJEXT%g
+s%@DATADIRNAME@%$DATADIRNAME%g
+s%@GMOFILES@%$GMOFILES%g
+s%@INSTOBJEXT@%$INSTOBJEXT%g
+s%@INTLDEPS@%$INTLDEPS%g
+s%@INTLLIBS@%$INTLLIBS%g
+s%@INTLOBJS@%$INTLOBJS%g
+s%@POFILES@%$POFILES%g
+s%@POSUB@%$POSUB%g
+s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g
+s%@GT_NO@%$GT_NO%g
+s%@GT_YES@%$GT_YES%g
+s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
+s%@l@%$l%g
+s%@MAINT@%$MAINT%g
+s%@sim_bswap@%$sim_bswap%g
+s%@sim_cflags@%$sim_cflags%g
+s%@sim_debug@%$sim_debug%g
+s%@sim_stdio@%$sim_stdio%g
+s%@sim_trace@%$sim_trace%g
+s%@sim_profile@%$sim_profile%g
+s%@EXEEXT@%$EXEEXT%g
+s%@CGEN_MAINT@%$CGEN_MAINT%g
+s%@cgendir@%$cgendir%g
+s%@cgen@%$cgen%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+  if test $ac_beg -gt 1; then
+    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+  else
+    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+  fi
+  if test ! -s conftest.s$ac_file; then
+    ac_more_lines=false
+    rm -f conftest.s$ac_file
+  else
+    if test -z "$ac_sed_cmds"; then
+      ac_sed_cmds="sed -f conftest.s$ac_file"
+    else
+      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+    fi
+    ac_file=`expr $ac_file + 1`
+    ac_beg=$ac_end
+    ac_end=`expr $ac_end + $ac_max_sed_cmds`
+  fi
+done
+if test -z "$ac_sed_cmds"; then
+  ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+    # The file is in a subdirectory.
+    test ! -d "$ac_dir" && mkdir "$ac_dir"
+    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dir_suffix.
+    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dir_suffix= ac_dots=
+  fi
+
+  case "$ac_given_srcdir" in
+  .)  srcdir=.
+      if test -z "$ac_dots"; then top_srcdir=.
+      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+  *) # Relative path.
+    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+    top_srcdir="$ac_dots$ac_given_srcdir" ;;
+  esac
+
+  case "$ac_given_INSTALL" in
+  [/$]*) INSTALL="$ac_given_INSTALL" ;;
+  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+  esac
+
+  echo creating "$ac_file"
+  rm -f "$ac_file"
+  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+  case "$ac_file" in
+  *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+  *) ac_comsub= ;;
+  esac
+
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ 	]*\)#\([ 	]*define[ 	][ 	]*\)'
+ac_dB='\([ 	][ 	]*\)[^ 	]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_uB='\([ 	]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+EOF
+cat >> $CONFIG_STATUS <<EOF
+  CONFIG_HEADERS="config.h:config.in"
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  echo creating $ac_file
+
+  rm -f conftest.frag conftest.in conftest.out
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  cat $ac_file_inputs > conftest.in
+
+EOF
+
+# Transform confdefs.h into a sed script conftest.vals that substitutes
+# the proper values into config.h.in to produce config.h.  And first:
+# Protect against being on the right side of a sed subst in config.status.
+# Protect against being in an unquoted here document in config.status.
+rm -f conftest.vals
+cat > conftest.hdr <<\EOF
+s/[\\&%]/\\&/g
+s%[\\$`]%\\&%g
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
+s%ac_d%ac_u%gp
+s%ac_u%ac_e%gp
+EOF
+sed -n -f conftest.hdr confdefs.h > conftest.vals
+rm -f conftest.hdr
+
+# This sed command replaces #undef with comments.  This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >> conftest.vals <<\EOF
+s%^[ 	]*#[ 	]*undef[ 	][ 	]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+EOF
+
+# Break up conftest.vals because some shells have a limit on
+# the size of here documents, and old seds have small limits too.
+
+rm -f conftest.tail
+while :
+do
+  ac_lines=`grep -c . conftest.vals`
+  # grep -c gives empty output for an empty file on some AIX systems.
+  if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
+  # Write a limited-size here document to conftest.frag.
+  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
+  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
+  echo 'CEOF
+  sed -f conftest.frag conftest.in > conftest.out
+  rm -f conftest.in
+  mv conftest.out conftest.in
+' >> $CONFIG_STATUS
+  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
+  rm -f conftest.vals
+  mv conftest.tail conftest.vals
+done
+rm -f conftest.vals
+
+cat >> $CONFIG_STATUS <<\EOF
+  rm -f conftest.frag conftest.h
+  echo "/* $ac_file.  Generated automatically by configure.  */" > conftest.h
+  cat conftest.in >> conftest.h
+  rm -f conftest.in
+  if cmp -s $ac_file conftest.h 2>/dev/null; then
+    echo "$ac_file is unchanged"
+    rm -f conftest.h
+  else
+    # Remove last slash and all that follows it.  Not all systems have dirname.
+      ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+      if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+      # The file is in a subdirectory.
+      test ! -d "$ac_dir" && mkdir "$ac_dir"
+    fi
+    rm -f $ac_file
+    mv conftest.h $ac_file
+  fi
+fi; done
+
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+srcdir=$ac_given_srcdir
+while test -n "$ac_sources"; do
+  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+  set $ac_sources; ac_source=$1; shift; ac_sources=$*
+
+  echo "linking $srcdir/$ac_source to $ac_dest"
+
+  if test ! -r $srcdir/$ac_source; then
+    { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; }
+  fi
+  rm -f $ac_dest
+
+  # Make relative symlinks.
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then
+    # The dest file is in a subdirectory.
+    test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
+    ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dest_dir_suffix.
+    ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dest_dir_suffix= ac_dots=
+  fi
+
+  case "$srcdir" in
+  [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
+  *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
+  esac
+
+  # Make a symlink if possible; otherwise try a hard link.
+  if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+    ln $srcdir/$ac_source $ac_dest; then :
+  else
+    { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
+  fi
+done
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+case "x$CONFIG_FILES" in
+ xMakefile*)
+   echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+   rm -f Makesim1.tmp Makesim2.tmp Makefile
+   sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+   sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+   sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
+	<Makefile.sim >Makefile
+   rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+   ;;
+ esac
+ case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
+
diff --git a/sim/fr30/configure.in b/sim/fr30/configure.in
new file mode 100644
index 00000000000..fc25dfc54b6
--- /dev/null
+++ b/sim/fr30/configure.in
@@ -0,0 +1,16 @@
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(fr30-1)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
diff --git a/sim/fr30/cpu.c b/sim/fr30/cpu.c
new file mode 100644
index 00000000000..c339a93dc1c
--- /dev/null
+++ b/sim/fr30/cpu.c
@@ -0,0 +1,356 @@
+/* Misc. support for CPU family fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU fr30bf
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+
+/* Get the value of h-pc.  */
+
+USI
+fr30bf_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+fr30bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+fr30bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr.  */
+
+void
+fr30bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cr.  */
+
+SI
+fr30bf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_cr[regno]);
+}
+
+/* Set a value for h-cr.  */
+
+void
+fr30bf_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_cr[regno]) = newval;
+}
+
+/* Get the value of h-dr.  */
+
+SI
+fr30bf_h_dr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_DR (regno);
+}
+
+/* Set a value for h-dr.  */
+
+void
+fr30bf_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  SET_H_DR (regno, newval);
+}
+
+/* Get the value of h-ps.  */
+
+USI
+fr30bf_h_ps_get (SIM_CPU *current_cpu)
+{
+  return GET_H_PS ();
+}
+
+/* Set a value for h-ps.  */
+
+void
+fr30bf_h_ps_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_PS (newval);
+}
+
+/* Get the value of h-r13.  */
+
+SI
+fr30bf_h_r13_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r13);
+}
+
+/* Set a value for h-r13.  */
+
+void
+fr30bf_h_r13_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r13) = newval;
+}
+
+/* Get the value of h-r14.  */
+
+SI
+fr30bf_h_r14_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r14);
+}
+
+/* Set a value for h-r14.  */
+
+void
+fr30bf_h_r14_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r14) = newval;
+}
+
+/* Get the value of h-r15.  */
+
+SI
+fr30bf_h_r15_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r15);
+}
+
+/* Set a value for h-r15.  */
+
+void
+fr30bf_h_r15_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r15) = newval;
+}
+
+/* Get the value of h-nbit.  */
+
+BI
+fr30bf_h_nbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit.  */
+
+void
+fr30bf_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-zbit.  */
+
+BI
+fr30bf_h_zbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit.  */
+
+void
+fr30bf_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-vbit.  */
+
+BI
+fr30bf_h_vbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit.  */
+
+void
+fr30bf_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-cbit.  */
+
+BI
+fr30bf_h_cbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit.  */
+
+void
+fr30bf_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-ibit.  */
+
+BI
+fr30bf_h_ibit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_ibit);
+}
+
+/* Set a value for h-ibit.  */
+
+void
+fr30bf_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_ibit) = newval;
+}
+
+/* Get the value of h-sbit.  */
+
+BI
+fr30bf_h_sbit_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SBIT ();
+}
+
+/* Set a value for h-sbit.  */
+
+void
+fr30bf_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  SET_H_SBIT (newval);
+}
+
+/* Get the value of h-tbit.  */
+
+BI
+fr30bf_h_tbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tbit);
+}
+
+/* Set a value for h-tbit.  */
+
+void
+fr30bf_h_tbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_tbit) = newval;
+}
+
+/* Get the value of h-d0bit.  */
+
+BI
+fr30bf_h_d0bit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_d0bit);
+}
+
+/* Set a value for h-d0bit.  */
+
+void
+fr30bf_h_d0bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_d0bit) = newval;
+}
+
+/* Get the value of h-d1bit.  */
+
+BI
+fr30bf_h_d1bit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_d1bit);
+}
+
+/* Set a value for h-d1bit.  */
+
+void
+fr30bf_h_d1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_d1bit) = newval;
+}
+
+/* Get the value of h-ccr.  */
+
+UQI
+fr30bf_h_ccr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_CCR ();
+}
+
+/* Set a value for h-ccr.  */
+
+void
+fr30bf_h_ccr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_CCR (newval);
+}
+
+/* Get the value of h-scr.  */
+
+UQI
+fr30bf_h_scr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SCR ();
+}
+
+/* Set a value for h-scr.  */
+
+void
+fr30bf_h_scr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_SCR (newval);
+}
+
+/* Get the value of h-ilm.  */
+
+UQI
+fr30bf_h_ilm_get (SIM_CPU *current_cpu)
+{
+  return GET_H_ILM ();
+}
+
+/* Set a value for h-ilm.  */
+
+void
+fr30bf_h_ilm_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_ILM (newval);
+}
+
+/* Record trace results for INSN.  */
+
+void
+fr30bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/fr30/cpu.h b/sim/fr30/cpu.h
new file mode 100644
index 00000000000..9a028632130
--- /dev/null
+++ b/sim/fr30/cpu.h
@@ -0,0 +1,1244 @@
+/* CPU family header for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_FR30BF_H
+#define CPU_FR30BF_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* general registers */
+  SI h_gr[16];
+#define GET_H_GR(a1) CPU (h_gr)[a1]
+#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
+  /* coprocessor registers */
+  SI h_cr[16];
+#define GET_H_CR(a1) CPU (h_cr)[a1]
+#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
+  /* dedicated registers */
+  SI h_dr[6];
+/* GET_H_DR macro user-written */
+/* SET_H_DR macro user-written */
+  /* program status */
+  USI h_ps;
+/* GET_H_PS macro user-written */
+/* SET_H_PS macro user-written */
+  /* General Register 13 explicitely required */
+  SI h_r13;
+#define GET_H_R13() CPU (h_r13)
+#define SET_H_R13(x) (CPU (h_r13) = (x))
+  /* General Register 14 explicitely required */
+  SI h_r14;
+#define GET_H_R14() CPU (h_r14)
+#define SET_H_R14(x) (CPU (h_r14) = (x))
+  /* General Register 15 explicitely required */
+  SI h_r15;
+#define GET_H_R15() CPU (h_r15)
+#define SET_H_R15(x) (CPU (h_r15) = (x))
+  /* negative         bit */
+  BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+  /* zero             bit */
+  BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+  /* overflow         bit */
+  BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+  /* carry            bit */
+  BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+  /* interrupt enable bit */
+  BI h_ibit;
+#define GET_H_IBIT() CPU (h_ibit)
+#define SET_H_IBIT(x) (CPU (h_ibit) = (x))
+  /* stack            bit */
+  BI h_sbit;
+/* GET_H_SBIT macro user-written */
+/* SET_H_SBIT macro user-written */
+  /* trace trap       bit */
+  BI h_tbit;
+#define GET_H_TBIT() CPU (h_tbit)
+#define SET_H_TBIT(x) (CPU (h_tbit) = (x))
+  /* division 0       bit */
+  BI h_d0bit;
+#define GET_H_D0BIT() CPU (h_d0bit)
+#define SET_H_D0BIT(x) (CPU (h_d0bit) = (x))
+  /* division 1       bit */
+  BI h_d1bit;
+#define GET_H_D1BIT() CPU (h_d1bit)
+#define SET_H_D1BIT(x) (CPU (h_d1bit) = (x))
+  /* condition code   bits */
+  UQI h_ccr;
+/* GET_H_CCR macro user-written */
+/* SET_H_CCR macro user-written */
+  /* system condition bits */
+  UQI h_scr;
+/* GET_H_SCR macro user-written */
+/* SET_H_SCR macro user-written */
+  /* interrupt level  mask */
+  UQI h_ilm;
+/* GET_H_ILM macro user-written */
+/* SET_H_ILM macro user-written */
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} FR30BF_CPU_DATA;
+
+/* Cover fns for register access.  */
+USI fr30bf_h_pc_get (SIM_CPU *);
+void fr30bf_h_pc_set (SIM_CPU *, USI);
+SI fr30bf_h_gr_get (SIM_CPU *, UINT);
+void fr30bf_h_gr_set (SIM_CPU *, UINT, SI);
+SI fr30bf_h_cr_get (SIM_CPU *, UINT);
+void fr30bf_h_cr_set (SIM_CPU *, UINT, SI);
+SI fr30bf_h_dr_get (SIM_CPU *, UINT);
+void fr30bf_h_dr_set (SIM_CPU *, UINT, SI);
+USI fr30bf_h_ps_get (SIM_CPU *);
+void fr30bf_h_ps_set (SIM_CPU *, USI);
+SI fr30bf_h_r13_get (SIM_CPU *);
+void fr30bf_h_r13_set (SIM_CPU *, SI);
+SI fr30bf_h_r14_get (SIM_CPU *);
+void fr30bf_h_r14_set (SIM_CPU *, SI);
+SI fr30bf_h_r15_get (SIM_CPU *);
+void fr30bf_h_r15_set (SIM_CPU *, SI);
+BI fr30bf_h_nbit_get (SIM_CPU *);
+void fr30bf_h_nbit_set (SIM_CPU *, BI);
+BI fr30bf_h_zbit_get (SIM_CPU *);
+void fr30bf_h_zbit_set (SIM_CPU *, BI);
+BI fr30bf_h_vbit_get (SIM_CPU *);
+void fr30bf_h_vbit_set (SIM_CPU *, BI);
+BI fr30bf_h_cbit_get (SIM_CPU *);
+void fr30bf_h_cbit_set (SIM_CPU *, BI);
+BI fr30bf_h_ibit_get (SIM_CPU *);
+void fr30bf_h_ibit_set (SIM_CPU *, BI);
+BI fr30bf_h_sbit_get (SIM_CPU *);
+void fr30bf_h_sbit_set (SIM_CPU *, BI);
+BI fr30bf_h_tbit_get (SIM_CPU *);
+void fr30bf_h_tbit_set (SIM_CPU *, BI);
+BI fr30bf_h_d0bit_get (SIM_CPU *);
+void fr30bf_h_d0bit_set (SIM_CPU *, BI);
+BI fr30bf_h_d1bit_get (SIM_CPU *);
+void fr30bf_h_d1bit_set (SIM_CPU *, BI);
+UQI fr30bf_h_ccr_get (SIM_CPU *);
+void fr30bf_h_ccr_set (SIM_CPU *, UQI);
+UQI fr30bf_h_scr_get (SIM_CPU *);
+void fr30bf_h_scr_set (SIM_CPU *, UQI);
+UQI fr30bf_h_ilm_get (SIM_CPU *);
+void fr30bf_h_ilm_set (SIM_CPU *, UQI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN fr30bf_fetch_register;
+extern CPUREG_STORE_FN fr30bf_store_register;
+
+typedef struct {
+  UINT load_regs;
+  UINT load_regs_pending;
+} MODEL_FR30_1_DATA;
+
+union sem_fields {
+    struct { /* empty sformat for unspecified field list */
+      int empty;
+    } fmt_empty;
+    struct { /* e.g. add $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_add;
+    struct { /* e.g. add $u4,$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_addi;
+    struct { /* e.g. add2 $m4,$Ri */
+      SI f_m4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_add2;
+    struct { /* e.g. addc $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_addc;
+    struct { /* e.g. addn $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_addn;
+    struct { /* e.g. addn $u4,$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_addni;
+    struct { /* e.g. addn2 $m4,$Ri */
+      SI f_m4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_addn2;
+    struct { /* e.g. cmp $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_cmp;
+    struct { /* e.g. cmp $u4,$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_cmpi;
+    struct { /* e.g. cmp2 $m4,$Ri */
+      SI f_m4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_cmp2;
+    struct { /* e.g. and $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_and;
+    struct { /* e.g. and $Rj,@$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_andm;
+    struct { /* e.g. andh $Rj,@$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_andh;
+    struct { /* e.g. andb $Rj,@$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_andb;
+    struct { /* e.g. bandl $u4,@$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_bandl;
+    struct { /* e.g. btstl $u4,@$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_btstl;
+    struct { /* e.g. mul $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_mul;
+    struct { /* e.g. mulu $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_mulu;
+    struct { /* e.g. mulh $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_mulh;
+    struct { /* e.g. div0s $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_div0s;
+    struct { /* e.g. div0u $Ri */
+      int empty;
+    } fmt_div0u;
+    struct { /* e.g. div1 $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_div1;
+    struct { /* e.g. div2 $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_div2;
+    struct { /* e.g. div3 */
+      int empty;
+    } fmt_div3;
+    struct { /* e.g. div4s */
+      int empty;
+    } fmt_div4s;
+    struct { /* e.g. lsl $Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_lsl;
+    struct { /* e.g. lsl $u4,$Ri */
+      UINT f_u4;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_lsli;
+    struct { /* e.g. ldi:8 $i8,$Ri */
+      UINT f_i8;
+      SI * i_Ri;
+      unsigned char out_Ri;
+    } fmt_ldi8;
+    struct { /* e.g. ldi:20 $i20,$Ri */
+      UINT f_i20;
+      SI * i_Ri;
+      unsigned char out_Ri;
+    } fmt_ldi20;
+    struct { /* e.g. ldi:32 $i32,$Ri */
+      UINT f_i32;
+      SI * i_Ri;
+      unsigned char out_Ri;
+    } fmt_ldi32;
+    struct { /* e.g. ld @$Rj,$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_ld;
+    struct { /* e.g. lduh @$Rj,$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_lduh;
+    struct { /* e.g. ldub @$Rj,$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_ldub;
+    struct { /* e.g. ld @($R13,$Rj),$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+      unsigned char out_Ri;
+    } fmt_ldr13;
+    struct { /* e.g. lduh @($R13,$Rj),$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+      unsigned char out_Ri;
+    } fmt_ldr13uh;
+    struct { /* e.g. ldub @($R13,$Rj),$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+      unsigned char out_Ri;
+    } fmt_ldr13ub;
+    struct { /* e.g. ld @($R14,$disp10),$Ri */
+      SI f_disp10;
+      SI * i_Ri;
+      unsigned char in_h_gr_14;
+      unsigned char out_Ri;
+    } fmt_ldr14;
+    struct { /* e.g. lduh @($R14,$disp9),$Ri */
+      SI f_disp9;
+      SI * i_Ri;
+      unsigned char in_h_gr_14;
+      unsigned char out_Ri;
+    } fmt_ldr14uh;
+    struct { /* e.g. ldub @($R14,$disp8),$Ri */
+      INT f_disp8;
+      SI * i_Ri;
+      unsigned char in_h_gr_14;
+      unsigned char out_Ri;
+    } fmt_ldr14ub;
+    struct { /* e.g. ld @($R15,$udisp6),$Ri */
+      USI f_udisp6;
+      SI * i_Ri;
+      unsigned char in_h_gr_15;
+      unsigned char out_Ri;
+    } fmt_ldr15;
+    struct { /* e.g. ld @$R15+,$Ri */
+      UINT f_Ri;
+      SI * i_Ri;
+      unsigned char in_h_gr_15;
+      unsigned char out_Ri;
+      unsigned char out_h_gr_15;
+    } fmt_ldr15gr;
+    struct { /* e.g. ld @$R15+,$Rs2 */
+      UINT f_Rs2;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_ldr15dr;
+    struct { /* e.g. ld @$R15+,$ps */
+      int empty;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_ldr15ps;
+    struct { /* e.g. st $Ri,@$Rj */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_st;
+    struct { /* e.g. sth $Ri,@$Rj */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_sth;
+    struct { /* e.g. stb $Ri,@$Rj */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+    } fmt_stb;
+    struct { /* e.g. st $Ri,@($R13,$Rj) */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+    } fmt_str13;
+    struct { /* e.g. sth $Ri,@($R13,$Rj) */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+    } fmt_str13h;
+    struct { /* e.g. stb $Ri,@($R13,$Rj) */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char in_h_gr_13;
+    } fmt_str13b;
+    struct { /* e.g. st $Ri,@($R14,$disp10) */
+      SI f_disp10;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char in_h_gr_14;
+    } fmt_str14;
+    struct { /* e.g. sth $Ri,@($R14,$disp9) */
+      SI f_disp9;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char in_h_gr_14;
+    } fmt_str14h;
+    struct { /* e.g. stb $Ri,@($R14,$disp8) */
+      INT f_disp8;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char in_h_gr_14;
+    } fmt_str14b;
+    struct { /* e.g. st $Ri,@($R15,$udisp6) */
+      USI f_udisp6;
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char in_h_gr_15;
+    } fmt_str15;
+    struct { /* e.g. st $Ri,@-$R15 */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_str15gr;
+    struct { /* e.g. st $Rs2,@-$R15 */
+      UINT f_Rs2;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_str15dr;
+    struct { /* e.g. st $ps,@-$R15 */
+      int empty;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_str15ps;
+    struct { /* e.g. mov $Rj,$Ri */
+      SI * i_Rj;
+      SI * i_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_mov;
+    struct { /* e.g. mov $Rs1,$Ri */
+      UINT f_Rs1;
+      SI * i_Ri;
+      unsigned char out_Ri;
+    } fmt_movdr;
+    struct { /* e.g. mov $ps,$Ri */
+      SI * i_Ri;
+      unsigned char out_Ri;
+    } fmt_movps;
+    struct { /* e.g. mov $Ri,$Rs1 */
+      UINT f_Rs1;
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_mov2dr;
+    struct { /* e.g. mov $Ri,$ps */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_mov2ps;
+    struct { /* e.g. bno:d $label9 */
+      int empty;
+    } fmt_bnod;
+    struct { /* e.g. dmov $R13,@$dir10 */
+      USI f_dir10;
+      unsigned char in_h_gr_13;
+    } fmt_dmovr13;
+    struct { /* e.g. dmovh $R13,@$dir9 */
+      USI f_dir9;
+      unsigned char in_h_gr_13;
+    } fmt_dmovr13h;
+    struct { /* e.g. dmovb $R13,@$dir8 */
+      UINT f_dir8;
+      unsigned char in_h_gr_13;
+    } fmt_dmovr13b;
+    struct { /* e.g. dmov @$R13+,@$dir10 */
+      USI f_dir10;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmovr13pi;
+    struct { /* e.g. dmovh @$R13+,@$dir9 */
+      USI f_dir9;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmovr13pih;
+    struct { /* e.g. dmovb @$R13+,@$dir8 */
+      UINT f_dir8;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmovr13pib;
+    struct { /* e.g. dmov @$R15+,@$dir10 */
+      USI f_dir10;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_dmovr15pi;
+    struct { /* e.g. dmov @$dir10,$R13 */
+      USI f_dir10;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13;
+    struct { /* e.g. dmovh @$dir9,$R13 */
+      USI f_dir9;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13h;
+    struct { /* e.g. dmovb @$dir8,$R13 */
+      UINT f_dir8;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13b;
+    struct { /* e.g. dmov @$dir10,@$R13+ */
+      USI f_dir10;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13pi;
+    struct { /* e.g. dmovh @$dir9,@$R13+ */
+      USI f_dir9;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13pih;
+    struct { /* e.g. dmovb @$dir8,@$R13+ */
+      UINT f_dir8;
+      unsigned char in_h_gr_13;
+      unsigned char out_h_gr_13;
+    } fmt_dmov2r13pib;
+    struct { /* e.g. dmov @$dir10,@-$R15 */
+      USI f_dir10;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_dmov2r15pd;
+    struct { /* e.g. ldres @$Ri+,$u4 */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_ldres;
+    struct { /* e.g. copop $u4c,$ccc,$CRj,$CRi */
+      int empty;
+    } fmt_copop;
+    struct { /* e.g. copld $u4c,$ccc,$Rjc,$CRi */
+      int empty;
+    } fmt_copld;
+    struct { /* e.g. copst $u4c,$ccc,$CRj,$Ric */
+      int empty;
+    } fmt_copst;
+    struct { /* e.g. nop */
+      int empty;
+    } fmt_nop;
+    struct { /* e.g. andccr $u8 */
+      UINT f_u8;
+    } fmt_andccr;
+    struct { /* e.g. stilm $u8 */
+      UINT f_u8;
+    } fmt_stilm;
+    struct { /* e.g. addsp $s10 */
+      SI f_s10;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_15;
+    } fmt_addsp;
+    struct { /* e.g. extsb $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_extsb;
+    struct { /* e.g. extub $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_extub;
+    struct { /* e.g. extsh $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_extsh;
+    struct { /* e.g. extuh $Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+      unsigned char out_Ri;
+    } fmt_extuh;
+    struct { /* e.g. ldm0 ($reglist_low_ld) */
+      UINT f_reglist_low_ld;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_0;
+      unsigned char out_h_gr_1;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_2;
+      unsigned char out_h_gr_3;
+      unsigned char out_h_gr_4;
+      unsigned char out_h_gr_5;
+      unsigned char out_h_gr_6;
+      unsigned char out_h_gr_7;
+    } fmt_ldm0;
+    struct { /* e.g. ldm1 ($reglist_hi_ld) */
+      UINT f_reglist_hi_ld;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_10;
+      unsigned char out_h_gr_11;
+      unsigned char out_h_gr_12;
+      unsigned char out_h_gr_13;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_8;
+      unsigned char out_h_gr_9;
+    } fmt_ldm1;
+    struct { /* e.g. stm0 ($reglist_low_st) */
+      UINT f_reglist_low_st;
+      unsigned char in_h_gr_0;
+      unsigned char in_h_gr_1;
+      unsigned char in_h_gr_15;
+      unsigned char in_h_gr_2;
+      unsigned char in_h_gr_3;
+      unsigned char in_h_gr_4;
+      unsigned char in_h_gr_5;
+      unsigned char in_h_gr_6;
+      unsigned char in_h_gr_7;
+      unsigned char out_h_gr_15;
+    } fmt_stm0;
+    struct { /* e.g. stm1 ($reglist_hi_st) */
+      UINT f_reglist_hi_st;
+      unsigned char in_h_gr_10;
+      unsigned char in_h_gr_11;
+      unsigned char in_h_gr_12;
+      unsigned char in_h_gr_13;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char in_h_gr_8;
+      unsigned char in_h_gr_9;
+      unsigned char out_h_gr_15;
+    } fmt_stm1;
+    struct { /* e.g. enter $u10 */
+      USI f_u10;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+    } fmt_enter;
+    struct { /* e.g. leave */
+      int empty;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+    } fmt_leave;
+    struct { /* e.g. xchb @$Rj,$Ri */
+      SI * i_Ri;
+      SI * i_Rj;
+      unsigned char in_Ri;
+      unsigned char in_Rj;
+      unsigned char out_Ri;
+    } fmt_xchb;
+  /* cti insns, kept separately so addr_cache is in fixed place */
+  struct {
+    union {
+    struct { /* e.g. jmp @$Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_jmp;
+    struct { /* e.g. call @$Ri */
+      SI * i_Ri;
+      unsigned char in_Ri;
+    } fmt_callr;
+    struct { /* e.g. call $label12 */
+      IADDR i_label12;
+    } fmt_call;
+    struct { /* e.g. ret */
+      int empty;
+    } fmt_ret;
+    struct { /* e.g. int $u8 */
+      UINT f_u8;
+    } fmt_int;
+    struct { /* e.g. inte */
+      int empty;
+    } fmt_inte;
+    struct { /* e.g. reti */
+      int empty;
+    } fmt_reti;
+    struct { /* e.g. bra:d $label9 */
+      IADDR i_label9;
+    } fmt_brad;
+    struct { /* e.g. beq:d $label9 */
+      IADDR i_label9;
+    } fmt_beqd;
+    struct { /* e.g. bc:d $label9 */
+      IADDR i_label9;
+    } fmt_bcd;
+    struct { /* e.g. bn:d $label9 */
+      IADDR i_label9;
+    } fmt_bnd;
+    struct { /* e.g. bv:d $label9 */
+      IADDR i_label9;
+    } fmt_bvd;
+    struct { /* e.g. blt:d $label9 */
+      IADDR i_label9;
+    } fmt_bltd;
+    struct { /* e.g. ble:d $label9 */
+      IADDR i_label9;
+    } fmt_bled;
+    struct { /* e.g. bls:d $label9 */
+      IADDR i_label9;
+    } fmt_blsd;
+    } fields;
+#if WITH_SCACHE_PBB
+    SEM_PC addr_cache;
+#endif
+  } cti;
+#if WITH_SCACHE_PBB
+  /* Writeback handler.  */
+  struct {
+    /* Pointer to argbuf entry for insn whose results need writing back.  */
+    const struct argbuf *abuf;
+  } write;
+  /* x-before handler */
+  struct {
+    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+    int first_p;
+  } before;
+  /* x-after handler */
+  struct {
+    int empty;
+  } after;
+  /* This entry is used to terminate each pbb.  */
+  struct {
+    /* Number of insns in pbb.  */
+    int insn_count;
+    /* Next pbb to execute.  */
+    SCACHE *next;
+  } chain;
+#endif
+};
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+  union sem semantic;
+  int written;
+  union sem_fields fields;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  /* Instruction fields.  */ \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_Rj; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_Rj = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_u4; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_u4 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_ADD2_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  SI f_m4; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD2_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_m4 = ((EXTRACT_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_DIV0S_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_DIV0S_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_DIV3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_op4; \
+  unsigned int length;
+#define EXTRACT_IFMT_DIV3_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_op4 = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDI8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_i8; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDI8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_i8 = EXTRACT_UINT (insn, 16, 4, 8); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDI20_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_i20; \
+  UINT f_i20_4; \
+  UINT f_i20_16; \
+  UINT f_op2; \
+  UINT f_Ri; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDI20_CODE \
+  length = 4; \
+  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \
+do {\
+  f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
+} while (0);\
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDI32_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_i32; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_Ri; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDI32_CODE \
+  length = 6; \
+  word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_i32 = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDR14_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  SI f_disp10; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDR14_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_disp10 = ((EXTRACT_INT (insn, 16, 4, 8)) << (2)); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDR14UH_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  SI f_disp9; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDR14UH_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_disp9 = ((EXTRACT_INT (insn, 16, 4, 8)) << (1)); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDR14UB_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  INT f_disp8; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDR14UB_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_disp8 = EXTRACT_INT (insn, 16, 4, 8); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDR15_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  USI f_udisp6; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDR15_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_udisp6 = ((EXTRACT_UINT (insn, 16, 8, 4)) << (2)); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LDR15DR_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_Rs2; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDR15DR_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Rs2 = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_MOVDR_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_Rs1; \
+  UINT f_Ri; \
+  unsigned int length;
+#define EXTRACT_IFMT_MOVDR_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_Rs1 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_CALL_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op5; \
+  SI f_rel12; \
+  unsigned int length;
+#define EXTRACT_IFMT_CALL_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op5 = EXTRACT_UINT (insn, 16, 4, 1); \
+  f_rel12 = ((((EXTRACT_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
+
+#define EXTRACT_IFMT_INT_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_u8; \
+  unsigned int length;
+#define EXTRACT_IFMT_INT_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_u8 = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_BRAD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_cc; \
+  SI f_rel9; \
+  unsigned int length;
+#define EXTRACT_IFMT_BRAD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_cc = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_rel9 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
+
+#define EXTRACT_IFMT_DMOVR13_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  USI f_dir10; \
+  unsigned int length;
+#define EXTRACT_IFMT_DMOVR13_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_dir10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \
+
+#define EXTRACT_IFMT_DMOVR13H_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  USI f_dir9; \
+  unsigned int length;
+#define EXTRACT_IFMT_DMOVR13H_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_dir9 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (1)); \
+
+#define EXTRACT_IFMT_DMOVR13B_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_dir8; \
+  unsigned int length;
+#define EXTRACT_IFMT_DMOVR13B_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_dir8 = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_COPOP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_ccc; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_CRj; \
+  UINT f_u4c; \
+  UINT f_CRi; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_COPOP_CODE \
+  length = 4; \
+  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
+  f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
+
+#define EXTRACT_IFMT_COPLD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_ccc; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_Rjc; \
+  UINT f_u4c; \
+  UINT f_CRi; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_COPLD_CODE \
+  length = 4; \
+  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_Rjc = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
+  f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
+
+#define EXTRACT_IFMT_COPST_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_ccc; \
+  UINT f_op2; \
+  UINT f_op3; \
+  UINT f_CRj; \
+  UINT f_u4c; \
+  UINT f_Ric; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_COPST_CODE \
+  length = 4; \
+  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
+  f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_Ric = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
+
+#define EXTRACT_IFMT_ADDSP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  SI f_s10; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDSP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_s10 = ((EXTRACT_INT (insn, 16, 8, 8)) << (2)); \
+
+#define EXTRACT_IFMT_LDM0_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_reglist_low_ld; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDM0_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_reglist_low_ld = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_LDM1_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_reglist_hi_ld; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDM1_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_reglist_hi_ld = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_STM0_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_reglist_low_st; \
+  unsigned int length;
+#define EXTRACT_IFMT_STM0_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_reglist_low_st = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_STM1_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  UINT f_reglist_hi_st; \
+  unsigned int length;
+#define EXTRACT_IFMT_STM1_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_reglist_hi_st = EXTRACT_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_ENTER_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_op2; \
+  USI f_u10; \
+  unsigned int length;
+#define EXTRACT_IFMT_ENTER_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_u10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_FR30BF_H */
diff --git a/sim/fr30/cpuall.h b/sim/fr30/cpuall.h
new file mode 100644
index 00000000000..dc8ed961395
--- /dev/null
+++ b/sim/fr30/cpuall.h
@@ -0,0 +1,63 @@
+/* Simulator CPU header for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30_CPUALL_H
+#define FR30_CPUALL_H
+
+/* Include files for each cpu family.  */
+
+#ifdef WANT_CPU_FR30BF
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH fr30_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* FR30_CPUALL_H */
diff --git a/sim/fr30/decode.c b/sim/fr30/decode.c
new file mode 100644
index 00000000000..c6d16567f3f
--- /dev/null
+++ b/sim/fr30/decode.c
@@ -0,0 +1,3303 @@
+/* Simulator instruction decoder for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU fr30bf
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* FIXME: Need to review choices for the following.  */
+
+#if WITH_SEM_SWITCH_FULL
+#define FULL(fn)
+#else
+#define FULL(fn) CONCAT3 (fr30bf,_sem_,fn) ,
+#endif
+
+#if WITH_FAST
+#if WITH_SEM_SWITCH_FAST
+#define FAST(fn)
+#else
+#define FAST(fn) CONCAT3 (fr30bf,_semf_,fn) , /* f for fast */
+#endif
+#else
+#define FAST(fn)
+#endif
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC fr30bf_insn_data[FR30BF_INSN_MAX];
+
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
+#define IDX(insn) CONCAT2 (FR30BF_,insn)
+#define TYPE(insn) CONCAT2 (FR30_,insn)
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
+
+static const struct insn_sem fr30bf_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
+  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
+  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
+  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
+  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
+  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
+  { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
+  { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
+  { TYPE (INSN_ADD2), IDX (INSN_ADD2), FULL (add2) FAST (add2) },
+  { TYPE (INSN_ADDC), IDX (INSN_ADDC), FULL (addc) FAST (addc) },
+  { TYPE (INSN_ADDN), IDX (INSN_ADDN), FULL (addn) FAST (addn) },
+  { TYPE (INSN_ADDNI), IDX (INSN_ADDNI), FULL (addni) FAST (addni) },
+  { TYPE (INSN_ADDN2), IDX (INSN_ADDN2), FULL (addn2) FAST (addn2) },
+  { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
+  { TYPE (INSN_SUBC), IDX (INSN_SUBC), FULL (subc) FAST (subc) },
+  { TYPE (INSN_SUBN), IDX (INSN_SUBN), FULL (subn) FAST (subn) },
+  { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
+  { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
+  { TYPE (INSN_CMP2), IDX (INSN_CMP2), FULL (cmp2) FAST (cmp2) },
+  { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
+  { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
+  { TYPE (INSN_EOR), IDX (INSN_EOR), FULL (eor) FAST (eor) },
+  { TYPE (INSN_ANDM), IDX (INSN_ANDM), FULL (andm) FAST (andm) },
+  { TYPE (INSN_ANDH), IDX (INSN_ANDH), FULL (andh) FAST (andh) },
+  { TYPE (INSN_ANDB), IDX (INSN_ANDB), FULL (andb) FAST (andb) },
+  { TYPE (INSN_ORM), IDX (INSN_ORM), FULL (orm) FAST (orm) },
+  { TYPE (INSN_ORH), IDX (INSN_ORH), FULL (orh) FAST (orh) },
+  { TYPE (INSN_ORB), IDX (INSN_ORB), FULL (orb) FAST (orb) },
+  { TYPE (INSN_EORM), IDX (INSN_EORM), FULL (eorm) FAST (eorm) },
+  { TYPE (INSN_EORH), IDX (INSN_EORH), FULL (eorh) FAST (eorh) },
+  { TYPE (INSN_EORB), IDX (INSN_EORB), FULL (eorb) FAST (eorb) },
+  { TYPE (INSN_BANDL), IDX (INSN_BANDL), FULL (bandl) FAST (bandl) },
+  { TYPE (INSN_BORL), IDX (INSN_BORL), FULL (borl) FAST (borl) },
+  { TYPE (INSN_BEORL), IDX (INSN_BEORL), FULL (beorl) FAST (beorl) },
+  { TYPE (INSN_BANDH), IDX (INSN_BANDH), FULL (bandh) FAST (bandh) },
+  { TYPE (INSN_BORH), IDX (INSN_BORH), FULL (borh) FAST (borh) },
+  { TYPE (INSN_BEORH), IDX (INSN_BEORH), FULL (beorh) FAST (beorh) },
+  { TYPE (INSN_BTSTL), IDX (INSN_BTSTL), FULL (btstl) FAST (btstl) },
+  { TYPE (INSN_BTSTH), IDX (INSN_BTSTH), FULL (btsth) FAST (btsth) },
+  { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
+  { TYPE (INSN_MULU), IDX (INSN_MULU), FULL (mulu) FAST (mulu) },
+  { TYPE (INSN_MULH), IDX (INSN_MULH), FULL (mulh) FAST (mulh) },
+  { TYPE (INSN_MULUH), IDX (INSN_MULUH), FULL (muluh) FAST (muluh) },
+  { TYPE (INSN_DIV0S), IDX (INSN_DIV0S), FULL (div0s) FAST (div0s) },
+  { TYPE (INSN_DIV0U), IDX (INSN_DIV0U), FULL (div0u) FAST (div0u) },
+  { TYPE (INSN_DIV1), IDX (INSN_DIV1), FULL (div1) FAST (div1) },
+  { TYPE (INSN_DIV2), IDX (INSN_DIV2), FULL (div2) FAST (div2) },
+  { TYPE (INSN_DIV3), IDX (INSN_DIV3), FULL (div3) FAST (div3) },
+  { TYPE (INSN_DIV4S), IDX (INSN_DIV4S), FULL (div4s) FAST (div4s) },
+  { TYPE (INSN_LSL), IDX (INSN_LSL), FULL (lsl) FAST (lsl) },
+  { TYPE (INSN_LSLI), IDX (INSN_LSLI), FULL (lsli) FAST (lsli) },
+  { TYPE (INSN_LSL2), IDX (INSN_LSL2), FULL (lsl2) FAST (lsl2) },
+  { TYPE (INSN_LSR), IDX (INSN_LSR), FULL (lsr) FAST (lsr) },
+  { TYPE (INSN_LSRI), IDX (INSN_LSRI), FULL (lsri) FAST (lsri) },
+  { TYPE (INSN_LSR2), IDX (INSN_LSR2), FULL (lsr2) FAST (lsr2) },
+  { TYPE (INSN_ASR), IDX (INSN_ASR), FULL (asr) FAST (asr) },
+  { TYPE (INSN_ASRI), IDX (INSN_ASRI), FULL (asri) FAST (asri) },
+  { TYPE (INSN_ASR2), IDX (INSN_ASR2), FULL (asr2) FAST (asr2) },
+  { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
+  { TYPE (INSN_LDI20), IDX (INSN_LDI20), FULL (ldi20) FAST (ldi20) },
+  { TYPE (INSN_LDI32), IDX (INSN_LDI32), FULL (ldi32) FAST (ldi32) },
+  { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
+  { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
+  { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
+  { TYPE (INSN_LDR13), IDX (INSN_LDR13), FULL (ldr13) FAST (ldr13) },
+  { TYPE (INSN_LDR13UH), IDX (INSN_LDR13UH), FULL (ldr13uh) FAST (ldr13uh) },
+  { TYPE (INSN_LDR13UB), IDX (INSN_LDR13UB), FULL (ldr13ub) FAST (ldr13ub) },
+  { TYPE (INSN_LDR14), IDX (INSN_LDR14), FULL (ldr14) FAST (ldr14) },
+  { TYPE (INSN_LDR14UH), IDX (INSN_LDR14UH), FULL (ldr14uh) FAST (ldr14uh) },
+  { TYPE (INSN_LDR14UB), IDX (INSN_LDR14UB), FULL (ldr14ub) FAST (ldr14ub) },
+  { TYPE (INSN_LDR15), IDX (INSN_LDR15), FULL (ldr15) FAST (ldr15) },
+  { TYPE (INSN_LDR15GR), IDX (INSN_LDR15GR), FULL (ldr15gr) FAST (ldr15gr) },
+  { TYPE (INSN_LDR15DR), IDX (INSN_LDR15DR), FULL (ldr15dr) FAST (ldr15dr) },
+  { TYPE (INSN_LDR15PS), IDX (INSN_LDR15PS), FULL (ldr15ps) FAST (ldr15ps) },
+  { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
+  { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
+  { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
+  { TYPE (INSN_STR13), IDX (INSN_STR13), FULL (str13) FAST (str13) },
+  { TYPE (INSN_STR13H), IDX (INSN_STR13H), FULL (str13h) FAST (str13h) },
+  { TYPE (INSN_STR13B), IDX (INSN_STR13B), FULL (str13b) FAST (str13b) },
+  { TYPE (INSN_STR14), IDX (INSN_STR14), FULL (str14) FAST (str14) },
+  { TYPE (INSN_STR14H), IDX (INSN_STR14H), FULL (str14h) FAST (str14h) },
+  { TYPE (INSN_STR14B), IDX (INSN_STR14B), FULL (str14b) FAST (str14b) },
+  { TYPE (INSN_STR15), IDX (INSN_STR15), FULL (str15) FAST (str15) },
+  { TYPE (INSN_STR15GR), IDX (INSN_STR15GR), FULL (str15gr) FAST (str15gr) },
+  { TYPE (INSN_STR15DR), IDX (INSN_STR15DR), FULL (str15dr) FAST (str15dr) },
+  { TYPE (INSN_STR15PS), IDX (INSN_STR15PS), FULL (str15ps) FAST (str15ps) },
+  { TYPE (INSN_MOV), IDX (INSN_MOV), FULL (mov) FAST (mov) },
+  { TYPE (INSN_MOVDR), IDX (INSN_MOVDR), FULL (movdr) FAST (movdr) },
+  { TYPE (INSN_MOVPS), IDX (INSN_MOVPS), FULL (movps) FAST (movps) },
+  { TYPE (INSN_MOV2DR), IDX (INSN_MOV2DR), FULL (mov2dr) FAST (mov2dr) },
+  { TYPE (INSN_MOV2PS), IDX (INSN_MOV2PS), FULL (mov2ps) FAST (mov2ps) },
+  { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
+  { TYPE (INSN_JMPD), IDX (INSN_JMPD), FULL (jmpd) FAST (jmpd) },
+  { TYPE (INSN_CALLR), IDX (INSN_CALLR), FULL (callr) FAST (callr) },
+  { TYPE (INSN_CALLRD), IDX (INSN_CALLRD), FULL (callrd) FAST (callrd) },
+  { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) },
+  { TYPE (INSN_CALLD), IDX (INSN_CALLD), FULL (calld) FAST (calld) },
+  { TYPE (INSN_RET), IDX (INSN_RET), FULL (ret) FAST (ret) },
+  { TYPE (INSN_RET_D), IDX (INSN_RET_D), FULL (ret_d) FAST (ret_d) },
+  { TYPE (INSN_INT), IDX (INSN_INT), FULL (int) FAST (int) },
+  { TYPE (INSN_INTE), IDX (INSN_INTE), FULL (inte) FAST (inte) },
+  { TYPE (INSN_RETI), IDX (INSN_RETI), FULL (reti) FAST (reti) },
+  { TYPE (INSN_BRAD), IDX (INSN_BRAD), FULL (brad) FAST (brad) },
+  { TYPE (INSN_BRA), IDX (INSN_BRA), FULL (bra) FAST (bra) },
+  { TYPE (INSN_BNOD), IDX (INSN_BNOD), FULL (bnod) FAST (bnod) },
+  { TYPE (INSN_BNO), IDX (INSN_BNO), FULL (bno) FAST (bno) },
+  { TYPE (INSN_BEQD), IDX (INSN_BEQD), FULL (beqd) FAST (beqd) },
+  { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
+  { TYPE (INSN_BNED), IDX (INSN_BNED), FULL (bned) FAST (bned) },
+  { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
+  { TYPE (INSN_BCD), IDX (INSN_BCD), FULL (bcd) FAST (bcd) },
+  { TYPE (INSN_BC), IDX (INSN_BC), FULL (bc) FAST (bc) },
+  { TYPE (INSN_BNCD), IDX (INSN_BNCD), FULL (bncd) FAST (bncd) },
+  { TYPE (INSN_BNC), IDX (INSN_BNC), FULL (bnc) FAST (bnc) },
+  { TYPE (INSN_BND), IDX (INSN_BND), FULL (bnd) FAST (bnd) },
+  { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) },
+  { TYPE (INSN_BPD), IDX (INSN_BPD), FULL (bpd) FAST (bpd) },
+  { TYPE (INSN_BP), IDX (INSN_BP), FULL (bp) FAST (bp) },
+  { TYPE (INSN_BVD), IDX (INSN_BVD), FULL (bvd) FAST (bvd) },
+  { TYPE (INSN_BV), IDX (INSN_BV), FULL (bv) FAST (bv) },
+  { TYPE (INSN_BNVD), IDX (INSN_BNVD), FULL (bnvd) FAST (bnvd) },
+  { TYPE (INSN_BNV), IDX (INSN_BNV), FULL (bnv) FAST (bnv) },
+  { TYPE (INSN_BLTD), IDX (INSN_BLTD), FULL (bltd) FAST (bltd) },
+  { TYPE (INSN_BLT), IDX (INSN_BLT), FULL (blt) FAST (blt) },
+  { TYPE (INSN_BGED), IDX (INSN_BGED), FULL (bged) FAST (bged) },
+  { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) },
+  { TYPE (INSN_BLED), IDX (INSN_BLED), FULL (bled) FAST (bled) },
+  { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) },
+  { TYPE (INSN_BGTD), IDX (INSN_BGTD), FULL (bgtd) FAST (bgtd) },
+  { TYPE (INSN_BGT), IDX (INSN_BGT), FULL (bgt) FAST (bgt) },
+  { TYPE (INSN_BLSD), IDX (INSN_BLSD), FULL (blsd) FAST (blsd) },
+  { TYPE (INSN_BLS), IDX (INSN_BLS), FULL (bls) FAST (bls) },
+  { TYPE (INSN_BHID), IDX (INSN_BHID), FULL (bhid) FAST (bhid) },
+  { TYPE (INSN_BHI), IDX (INSN_BHI), FULL (bhi) FAST (bhi) },
+  { TYPE (INSN_DMOVR13), IDX (INSN_DMOVR13), FULL (dmovr13) FAST (dmovr13) },
+  { TYPE (INSN_DMOVR13H), IDX (INSN_DMOVR13H), FULL (dmovr13h) FAST (dmovr13h) },
+  { TYPE (INSN_DMOVR13B), IDX (INSN_DMOVR13B), FULL (dmovr13b) FAST (dmovr13b) },
+  { TYPE (INSN_DMOVR13PI), IDX (INSN_DMOVR13PI), FULL (dmovr13pi) FAST (dmovr13pi) },
+  { TYPE (INSN_DMOVR13PIH), IDX (INSN_DMOVR13PIH), FULL (dmovr13pih) FAST (dmovr13pih) },
+  { TYPE (INSN_DMOVR13PIB), IDX (INSN_DMOVR13PIB), FULL (dmovr13pib) FAST (dmovr13pib) },
+  { TYPE (INSN_DMOVR15PI), IDX (INSN_DMOVR15PI), FULL (dmovr15pi) FAST (dmovr15pi) },
+  { TYPE (INSN_DMOV2R13), IDX (INSN_DMOV2R13), FULL (dmov2r13) FAST (dmov2r13) },
+  { TYPE (INSN_DMOV2R13H), IDX (INSN_DMOV2R13H), FULL (dmov2r13h) FAST (dmov2r13h) },
+  { TYPE (INSN_DMOV2R13B), IDX (INSN_DMOV2R13B), FULL (dmov2r13b) FAST (dmov2r13b) },
+  { TYPE (INSN_DMOV2R13PI), IDX (INSN_DMOV2R13PI), FULL (dmov2r13pi) FAST (dmov2r13pi) },
+  { TYPE (INSN_DMOV2R13PIH), IDX (INSN_DMOV2R13PIH), FULL (dmov2r13pih) FAST (dmov2r13pih) },
+  { TYPE (INSN_DMOV2R13PIB), IDX (INSN_DMOV2R13PIB), FULL (dmov2r13pib) FAST (dmov2r13pib) },
+  { TYPE (INSN_DMOV2R15PD), IDX (INSN_DMOV2R15PD), FULL (dmov2r15pd) FAST (dmov2r15pd) },
+  { TYPE (INSN_LDRES), IDX (INSN_LDRES), FULL (ldres) FAST (ldres) },
+  { TYPE (INSN_STRES), IDX (INSN_STRES), FULL (stres) FAST (stres) },
+  { TYPE (INSN_COPOP), IDX (INSN_COPOP), FULL (copop) FAST (copop) },
+  { TYPE (INSN_COPLD), IDX (INSN_COPLD), FULL (copld) FAST (copld) },
+  { TYPE (INSN_COPST), IDX (INSN_COPST), FULL (copst) FAST (copst) },
+  { TYPE (INSN_COPSV), IDX (INSN_COPSV), FULL (copsv) FAST (copsv) },
+  { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
+  { TYPE (INSN_ANDCCR), IDX (INSN_ANDCCR), FULL (andccr) FAST (andccr) },
+  { TYPE (INSN_ORCCR), IDX (INSN_ORCCR), FULL (orccr) FAST (orccr) },
+  { TYPE (INSN_STILM), IDX (INSN_STILM), FULL (stilm) FAST (stilm) },
+  { TYPE (INSN_ADDSP), IDX (INSN_ADDSP), FULL (addsp) FAST (addsp) },
+  { TYPE (INSN_EXTSB), IDX (INSN_EXTSB), FULL (extsb) FAST (extsb) },
+  { TYPE (INSN_EXTUB), IDX (INSN_EXTUB), FULL (extub) FAST (extub) },
+  { TYPE (INSN_EXTSH), IDX (INSN_EXTSH), FULL (extsh) FAST (extsh) },
+  { TYPE (INSN_EXTUH), IDX (INSN_EXTUH), FULL (extuh) FAST (extuh) },
+  { TYPE (INSN_LDM0), IDX (INSN_LDM0), FULL (ldm0) FAST (ldm0) },
+  { TYPE (INSN_LDM1), IDX (INSN_LDM1), FULL (ldm1) FAST (ldm1) },
+  { TYPE (INSN_STM0), IDX (INSN_STM0), FULL (stm0) FAST (stm0) },
+  { TYPE (INSN_STM1), IDX (INSN_STM1), FULL (stm1) FAST (stm1) },
+  { TYPE (INSN_ENTER), IDX (INSN_ENTER), FULL (enter) FAST (enter) },
+  { TYPE (INSN_LEAVE), IDX (INSN_LEAVE), FULL (leave) FAST (leave) },
+  { TYPE (INSN_XCHB), IDX (INSN_XCHB), FULL (xchb) FAST (xchb) },
+};
+
+static const struct insn_sem fr30bf_insn_sem_invalid =
+{
+  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
+};
+
+#undef IDX
+#undef TYPE
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+  id->num = t->index;
+  if ((int) t->type <= 0)
+    id->idata = & cgen_virtual_insn_table[- (int) t->type];
+  else
+    id->idata = & insn_table[t->type];
+  id->attrs = CGEN_INSN_ATTRS (id->idata);
+  /* Oh my god, a magic number.  */
+  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+#if ! WITH_SEM_SWITCH_FULL
+  id->sem_full = t->sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  id->sem_fast = t->sem_fast;
+#endif
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+fr30bf_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = FR30BF_INSN_MAX;
+  IDESC *table = fr30bf_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & fr30bf_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = fr30bf_insn_sem, tend = t + sizeof (fr30bf_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Enum declaration for all instruction semantic formats.  */
+typedef enum sfmt {
+  FMT_EMPTY, FMT_ADD, FMT_ADDI, FMT_ADD2
+ , FMT_ADDC, FMT_ADDN, FMT_ADDNI, FMT_ADDN2
+ , FMT_CMP, FMT_CMPI, FMT_CMP2, FMT_AND
+ , FMT_ANDM, FMT_ANDH, FMT_ANDB, FMT_BANDL
+ , FMT_BTSTL, FMT_MUL, FMT_MULU, FMT_MULH
+ , FMT_DIV0S, FMT_DIV0U, FMT_DIV1, FMT_DIV2
+ , FMT_DIV3, FMT_DIV4S, FMT_LSL, FMT_LSLI
+ , FMT_LDI8, FMT_LDI20, FMT_LDI32, FMT_LD
+ , FMT_LDUH, FMT_LDUB, FMT_LDR13, FMT_LDR13UH
+ , FMT_LDR13UB, FMT_LDR14, FMT_LDR14UH, FMT_LDR14UB
+ , FMT_LDR15, FMT_LDR15GR, FMT_LDR15DR, FMT_LDR15PS
+ , FMT_ST, FMT_STH, FMT_STB, FMT_STR13
+ , FMT_STR13H, FMT_STR13B, FMT_STR14, FMT_STR14H
+ , FMT_STR14B, FMT_STR15, FMT_STR15GR, FMT_STR15DR
+ , FMT_STR15PS, FMT_MOV, FMT_MOVDR, FMT_MOVPS
+ , FMT_MOV2DR, FMT_MOV2PS, FMT_JMP, FMT_CALLR
+ , FMT_CALL, FMT_RET, FMT_INT, FMT_INTE
+ , FMT_RETI, FMT_BRAD, FMT_BNOD, FMT_BEQD
+ , FMT_BCD, FMT_BND, FMT_BVD, FMT_BLTD
+ , FMT_BLED, FMT_BLSD, FMT_DMOVR13, FMT_DMOVR13H
+ , FMT_DMOVR13B, FMT_DMOVR13PI, FMT_DMOVR13PIH, FMT_DMOVR13PIB
+ , FMT_DMOVR15PI, FMT_DMOV2R13, FMT_DMOV2R13H, FMT_DMOV2R13B
+ , FMT_DMOV2R13PI, FMT_DMOV2R13PIH, FMT_DMOV2R13PIB, FMT_DMOV2R15PD
+ , FMT_LDRES, FMT_COPOP, FMT_COPLD, FMT_COPST
+ , FMT_NOP, FMT_ANDCCR, FMT_STILM, FMT_ADDSP
+ , FMT_EXTSB, FMT_EXTUB, FMT_EXTSH, FMT_EXTUH
+ , FMT_LDM0, FMT_LDM1, FMT_STM0, FMT_STM1
+ , FMT_ENTER, FMT_LEAVE, FMT_XCHB
+} SFMT;
+
+/* The decoder uses this to record insns and direct extraction handling.  */
+
+typedef struct {
+  const IDESC *idesc;
+#ifdef __GNUC__
+  void *sfmt;
+#else
+  enum sfmt sfmt;
+#endif
+} DECODE_DESC;
+
+/* Macro to go from decode phase to extraction phase.  */
+
+#ifdef __GNUC__
+#define GOTO_EXTRACT(id) goto *(id)->sfmt
+#else
+#define GOTO_EXTRACT(id) goto extract
+#endif
+
+/* The decoder needs a slightly different computed goto switch control.  */
+#ifdef __GNUC__
+#define DECODE_SWITCH(N, X) goto *labels_##N[X];
+#else
+#define DECODE_SWITCH(N, X) switch (X)
+#endif
+
+/* Given an instruction, return a pointer to its IDESC entry.  */
+
+const IDESC *
+fr30bf_decode (SIM_CPU *current_cpu, IADDR pc,
+              CGEN_INSN_INT base_insn,
+              ARGBUF *abuf)
+{
+  /* Result of decoder, used by extractor.  */
+  const DECODE_DESC *idecode;
+
+  /* First decode the instruction.  */
+
+  {
+#define I(insn) & fr30bf_insn_data[CONCAT2 (FR30BF_,insn)]
+#ifdef __GNUC__
+#define E(fmt) && case_ex_##fmt
+#else
+#define E(fmt) fmt
+#endif
+    CGEN_INSN_INT insn = base_insn;
+    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
+
+    {
+#ifdef __GNUC__
+      static const void *labels_0[256] = {
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_7, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_23, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_151, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_159, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+      };
+#endif
+      static const DECODE_DESC insns[256] = {
+        { I (INSN_LDR13), E (FMT_LDR13) }, { I (INSN_LDR13UH), E (FMT_LDR13UH) }, 
+        { I (INSN_LDR13UB), E (FMT_LDR13UB) }, { I (INSN_LDR15), E (FMT_LDR15) }, 
+        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LDUH), E (FMT_LDUH) }, 
+        { I (INSN_LDUB), E (FMT_LDUB) }, { 0 }, 
+        { I (INSN_DMOV2R13), E (FMT_DMOV2R13) }, { I (INSN_DMOV2R13H), E (FMT_DMOV2R13H) }, 
+        { I (INSN_DMOV2R13B), E (FMT_DMOV2R13B) }, { I (INSN_DMOV2R15PD), E (FMT_DMOV2R15PD) }, 
+        { I (INSN_DMOV2R13PI), E (FMT_DMOV2R13PI) }, { I (INSN_DMOV2R13PIH), E (FMT_DMOV2R13PIH) }, 
+        { I (INSN_DMOV2R13PIB), E (FMT_DMOV2R13PIB) }, { I (INSN_ENTER), E (FMT_ENTER) }, 
+        { I (INSN_STR13), E (FMT_STR13) }, { I (INSN_STR13H), E (FMT_STR13H) }, 
+        { I (INSN_STR13B), E (FMT_STR13B) }, { I (INSN_STR15), E (FMT_STR15) }, 
+        { I (INSN_ST), E (FMT_ST) }, { I (INSN_STH), E (FMT_STH) }, 
+        { I (INSN_STB), E (FMT_STB) }, { 0 }, 
+        { I (INSN_DMOVR13), E (FMT_DMOVR13) }, { I (INSN_DMOVR13H), E (FMT_DMOVR13H) }, 
+        { I (INSN_DMOVR13B), E (FMT_DMOVR13B) }, { I (INSN_DMOVR15PI), E (FMT_DMOVR15PI) }, 
+        { I (INSN_DMOVR13PI), E (FMT_DMOVR13PI) }, { I (INSN_DMOVR13PIH), E (FMT_DMOVR13PIH) }, 
+        { I (INSN_DMOVR13PIB), E (FMT_DMOVR13PIB) }, { I (INSN_INT), E (FMT_INT) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, 
+        { I (INSN_BANDL), E (FMT_BANDL) }, { I (INSN_BANDH), E (FMT_BANDL) }, 
+        { I (INSN_AND), E (FMT_AND) }, { I (INSN_ANDCCR), E (FMT_ANDCCR) }, 
+        { I (INSN_ANDM), E (FMT_ANDM) }, { I (INSN_ANDH), E (FMT_ANDH) }, 
+        { I (INSN_ANDB), E (FMT_ANDB) }, { I (INSN_STILM), E (FMT_STILM) }, 
+        { I (INSN_BTSTL), E (FMT_BTSTL) }, { I (INSN_BTSTH), E (FMT_BTSTL) }, 
+        { I (INSN_XCHB), E (FMT_XCHB) }, { I (INSN_MOV), E (FMT_MOV) }, 
+        { I (INSN_LDM0), E (FMT_LDM0) }, { I (INSN_LDM1), E (FMT_LDM1) }, 
+        { I (INSN_STM0), E (FMT_STM0) }, { I (INSN_STM1), E (FMT_STM1) }, 
+        { I (INSN_BORL), E (FMT_BANDL) }, { I (INSN_BORH), E (FMT_BANDL) }, 
+        { I (INSN_OR), E (FMT_AND) }, { I (INSN_ORCCR), E (FMT_ANDCCR) }, 
+        { I (INSN_ORM), E (FMT_ANDM) }, { I (INSN_ORH), E (FMT_ANDH) }, 
+        { I (INSN_ORB), E (FMT_ANDB) }, { 0 }, 
+        { I (INSN_BEORL), E (FMT_BANDL) }, { I (INSN_BEORH), E (FMT_BANDL) }, 
+        { I (INSN_EOR), E (FMT_AND) }, { I (INSN_LDI20), E (FMT_LDI20) }, 
+        { I (INSN_EORM), E (FMT_ANDM) }, { I (INSN_EORH), E (FMT_ANDH) }, 
+        { I (INSN_EORB), E (FMT_ANDB) }, { 0 }, 
+        { I (INSN_ADDNI), E (FMT_ADDNI) }, { I (INSN_ADDN2), E (FMT_ADDN2) }, 
+        { I (INSN_ADDN), E (FMT_ADDN) }, { I (INSN_ADDSP), E (FMT_ADDSP) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADD2), E (FMT_ADD2) }, 
+        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_ADDC), E (FMT_ADDC) }, 
+        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMP2), E (FMT_CMP2) }, 
+        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_MULU), E (FMT_MULU) }, 
+        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_SUBC), E (FMT_ADDC) }, 
+        { I (INSN_SUBN), E (FMT_ADDN) }, { I (INSN_MUL), E (FMT_MUL) }, 
+        { I (INSN_LSRI), E (FMT_LSLI) }, { I (INSN_LSR2), E (FMT_LSLI) }, 
+        { I (INSN_LSR), E (FMT_LSL) }, { I (INSN_MOV2DR), E (FMT_MOV2DR) }, 
+        { I (INSN_LSLI), E (FMT_LSLI) }, { I (INSN_LSL2), E (FMT_LSLI) }, 
+        { I (INSN_LSL), E (FMT_LSL) }, { I (INSN_MOVDR), E (FMT_MOVDR) }, 
+        { I (INSN_ASRI), E (FMT_LSLI) }, { I (INSN_ASR2), E (FMT_LSLI) }, 
+        { I (INSN_ASR), E (FMT_LSL) }, { I (INSN_MULUH), E (FMT_MULH) }, 
+        { I (INSN_LDRES), E (FMT_LDRES) }, { I (INSN_STRES), E (FMT_LDRES) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MULH), E (FMT_MULH) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, 
+        { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, 
+        { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, 
+        { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, 
+        { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, 
+        { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, 
+        { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, 
+        { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, 
+        { I (INSN_BRA), E (FMT_BRAD) }, { I (INSN_BNO), E (FMT_BNOD) }, 
+        { I (INSN_BEQ), E (FMT_BEQD) }, { I (INSN_BNE), E (FMT_BEQD) }, 
+        { I (INSN_BC), E (FMT_BCD) }, { I (INSN_BNC), E (FMT_BCD) }, 
+        { I (INSN_BN), E (FMT_BND) }, { I (INSN_BP), E (FMT_BND) }, 
+        { I (INSN_BV), E (FMT_BVD) }, { I (INSN_BNV), E (FMT_BVD) }, 
+        { I (INSN_BLT), E (FMT_BLTD) }, { I (INSN_BGE), E (FMT_BLTD) }, 
+        { I (INSN_BLE), E (FMT_BLED) }, { I (INSN_BGT), E (FMT_BLED) }, 
+        { I (INSN_BLS), E (FMT_BLSD) }, { I (INSN_BHI), E (FMT_BLSD) }, 
+        { I (INSN_BRAD), E (FMT_BRAD) }, { I (INSN_BNOD), E (FMT_BNOD) }, 
+        { I (INSN_BEQD), E (FMT_BEQD) }, { I (INSN_BNED), E (FMT_BEQD) }, 
+        { I (INSN_BCD), E (FMT_BCD) }, { I (INSN_BNCD), E (FMT_BCD) }, 
+        { I (INSN_BND), E (FMT_BND) }, { I (INSN_BPD), E (FMT_BND) }, 
+        { I (INSN_BVD), E (FMT_BVD) }, { I (INSN_BNVD), E (FMT_BVD) }, 
+        { I (INSN_BLTD), E (FMT_BLTD) }, { I (INSN_BGED), E (FMT_BLTD) }, 
+        { I (INSN_BLED), E (FMT_BLED) }, { I (INSN_BGTD), E (FMT_BLED) }, 
+        { I (INSN_BLSD), E (FMT_BLSD) }, { I (INSN_BHID), E (FMT_BLSD) }, 
+      };
+      unsigned int val;
+      val = (((insn >> 8) & (255 << 0)));
+      DECODE_SWITCH (0, val)
+        {
+        CASE (0, 7) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDR15GR), E (FMT_LDR15GR) }, { I (INSN_MOV2PS), E (FMT_MOV2PS) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_LDR15DR), E (FMT_LDR15DR) }, { I (INSN_LDR15PS), E (FMT_LDR15PS) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 4) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 23) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STR15GR), E (FMT_STR15GR) }, { I (INSN_MOVPS), E (FMT_MOVPS) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_STR15DR), E (FMT_STR15DR) }, { I (INSN_STR15PS), E (FMT_STR15PS) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 4) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 151) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_JMP), E (FMT_JMP) }, { I (INSN_CALLR), E (FMT_CALLR) }, 
+              { I (INSN_RET), E (FMT_RET) }, { I (INSN_RETI), E (FMT_RETI) }, 
+              { I (INSN_DIV0S), E (FMT_DIV0S) }, { I (INSN_DIV0U), E (FMT_DIV0U) }, 
+              { I (INSN_DIV1), E (FMT_DIV1) }, { I (INSN_DIV2), E (FMT_DIV2) }, 
+              { I (INSN_EXTSB), E (FMT_EXTSB) }, { I (INSN_EXTUB), E (FMT_EXTUB) }, 
+              { I (INSN_EXTSH), E (FMT_EXTSH) }, { I (INSN_EXTUH), E (FMT_EXTUH) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 4) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 159) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_JMPD), E (FMT_JMP) }, { I (INSN_CALLRD), E (FMT_CALLR) }, 
+              { I (INSN_RET_D), E (FMT_RET) }, { I (INSN_INTE), E (FMT_INTE) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_DIV3), E (FMT_DIV3) }, { I (INSN_DIV4S), E (FMT_DIV4S) }, 
+              { I (INSN_LDI32), E (FMT_LDI32) }, { I (INSN_LEAVE), E (FMT_LEAVE) }, 
+              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_COPOP), E (FMT_COPOP) }, { I (INSN_COPLD), E (FMT_COPLD) }, 
+              { I (INSN_COPST), E (FMT_COPST) }, { I (INSN_COPSV), E (FMT_COPST) }, 
+            };
+            unsigned int val = (((insn >> 4) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        DEFAULT (0) :
+          idecode = &insns[val];
+          GOTO_EXTRACT (idecode);
+        }
+      ENDSWITCH (0)
+    }
+#undef I
+#undef E
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract:
+  {
+#ifndef __GNUC__
+    switch (idecode->sfmt)
+#endif
+      {
+
+  CASE (ex, FMT_EMPTY) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+  EXTRACT_IFMT_EMPTY_VARS /* */
+
+  EXTRACT_IFMT_EMPTY_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_add.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addi.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADD2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_add2.f
+  EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */
+
+  EXTRACT_IFMT_ADD2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_m4) = f_m4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDC) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addc.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addc", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDN) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addn.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addn", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDNI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addni.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addni", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDN2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addn2.f
+  EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */
+
+  EXTRACT_IFMT_ADD2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_m4) = f_m4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addn2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmp.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMP2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmp2.f
+  EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */
+
+  EXTRACT_IFMT_ADD2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_m4) = f_m4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_AND) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_and.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ANDM) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_andm.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andm", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ANDH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_andh.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ANDB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_andb.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BANDL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_bandl.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bandl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BTSTL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_btstl.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_btstl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MUL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mul.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mul", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULU) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulu.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulu", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulh.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV0S) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div0s.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0s", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV0U) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div0u.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0u", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div1.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div1", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div2.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div2", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div3.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div3", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV4S) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_div4s.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div4s", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LSL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lsl.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lsl", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LSLI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lsli.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u4) = f_u4;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lsli", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI8) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  EXTRACT_IFMT_LDI8_VARS /* f-op1 f-i8 f-Ri */
+
+  EXTRACT_IFMT_LDI8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_i8) = f_i8;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_i8 0x%x", 'x', f_i8, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI20) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldi20.f
+  EXTRACT_IFMT_LDI20_VARS /* f-op1 f-i20 f-op2 f-Ri */
+
+  EXTRACT_IFMT_LDI20_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_i20) = f_i20;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi20", "f_i20 0x%x", 'x', f_i20, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI32) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldi32.f
+  EXTRACT_IFMT_LDI32_VARS /* f-op1 f-i32 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_LDI32_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_i32) = f_i32;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi32", "f_i32 0x%x", 'x', f_i32, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDUH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lduh.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lduh", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDUB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldub.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldub", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR13) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr13.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr13", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR13UH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr13uh.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr13uh", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR13UB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr13ub.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr13ub", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR14) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr14.f
+  EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */
+
+  EXTRACT_IFMT_LDR14_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp10) = f_disp10;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_14) = 14;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR14UH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr14uh.f
+  EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */
+
+  EXTRACT_IFMT_LDR14UH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp9) = f_disp9;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14uh", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_14) = 14;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR14UB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr14ub.f
+  EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */
+
+  EXTRACT_IFMT_LDR14UB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14ub", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_14) = 14;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR15) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr15.f
+  EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */
+
+  EXTRACT_IFMT_LDR15_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_udisp6) = f_udisp6;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR15GR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr15gr.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Ri) = f_Ri;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15gr", "f_Ri 0x%x", 'x', f_Ri, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_Ri) = f_Ri;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR15DR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr15dr.f
+  EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */
+
+  EXTRACT_IFMT_LDR15DR_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rs2) = f_Rs2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDR15PS) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldr15ps.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15ps", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_sth.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stb.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR13) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str13.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str13", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR13H) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str13h.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str13h", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR13B) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str13b.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str13b", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR14) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str14.f
+  EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */
+
+  EXTRACT_IFMT_LDR14_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp10) = f_disp10;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR14H) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str14h.f
+  EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */
+
+  EXTRACT_IFMT_LDR14UH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp9) = f_disp9;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14h", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR14B) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str14b.f
+  EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */
+
+  EXTRACT_IFMT_LDR14UB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14b", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR15) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str15.f
+  EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */
+
+  EXTRACT_IFMT_LDR15_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_udisp6) = f_udisp6;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR15GR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str15gr.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15gr", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR15DR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str15dr.f
+  EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */
+
+  EXTRACT_IFMT_LDR15DR_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rs2) = f_Rs2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STR15PS) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_str15ps.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15ps", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOV) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mov.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVDR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movdr.f
+  EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */
+
+  EXTRACT_IFMT_MOVDR_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rs1) = f_Rs1;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movdr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVPS) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movps.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movps", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOV2DR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mov2dr.f
+  EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */
+
+  EXTRACT_IFMT_MOVDR_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_Rs1) = f_Rs1;
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov2dr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOV2PS) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mov2ps.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov2ps", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JMP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALLR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callr", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  EXTRACT_IFMT_CALL_VARS /* f-op1 f-op5 f-rel12 */
+
+  EXTRACT_IFMT_CALL_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label12) = f_rel12;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_call", "label12 0x%x", 'x', f_rel12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ret", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_INT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_int.f
+  EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */
+
+  EXTRACT_IFMT_INT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u8) = f_u8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_int", "f_u8 0x%x", 'x', f_u8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_INTE) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_inte.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_inte", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RETI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_reti.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_reti", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BRAD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_brad", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BNOD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_bnod.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnod", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BEQD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BCD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BND) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BVD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bvd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BLTD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bltd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BLED) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bled", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BLSD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */
+
+  EXTRACT_IFMT_BRAD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label9) = f_rel9;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_blsd", "label9 0x%x", 'x', f_rel9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13H) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13h.f
+  EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */
+
+  EXTRACT_IFMT_DMOVR13H_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir9) = f_dir9;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13B) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13b.f
+  EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */
+
+  EXTRACT_IFMT_DMOVR13B_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir8) = f_dir8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13PI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13pi.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13PIH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13pih.f
+  EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */
+
+  EXTRACT_IFMT_DMOVR13H_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir9) = f_dir9;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR13PIB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr13pib.f
+  EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */
+
+  EXTRACT_IFMT_DMOVR13B_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir8) = f_dir8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOVR15PI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmovr15pi.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr15pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13H) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13h.f
+  EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */
+
+  EXTRACT_IFMT_DMOVR13H_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir9) = f_dir9;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13B) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13b.f
+  EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */
+
+  EXTRACT_IFMT_DMOVR13B_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir8) = f_dir8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13PI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13pi.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13PIH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13pih.f
+  EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */
+
+  EXTRACT_IFMT_DMOVR13H_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir9) = f_dir9;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R13PIB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r13pib.f
+  EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */
+
+  EXTRACT_IFMT_DMOVR13B_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir8) = f_dir8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_13) = 13;
+      FLD (out_h_gr_13) = 13;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DMOV2R15PD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_dmov2r15pd.f
+  EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */
+
+  EXTRACT_IFMT_DMOVR13_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_dir10) = f_dir10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r15pd", "f_dir10 0x%x", 'x', f_dir10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDRES) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldres.f
+  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */
+
+  EXTRACT_IFMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldres", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_COPOP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_copop.f
+  EXTRACT_IFMT_COPOP_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-CRi */
+
+  EXTRACT_IFMT_COPOP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copop", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_COPLD) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_copld.f
+  EXTRACT_IFMT_COPLD_VARS /* f-op1 f-ccc f-op2 f-op3 f-Rjc f-u4c f-CRi */
+
+  EXTRACT_IFMT_COPLD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copld", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_COPST) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_copst.f
+  EXTRACT_IFMT_COPST_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-Ric */
+
+  EXTRACT_IFMT_COPST_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copst", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_nop.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ANDCCR) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_andccr.f
+  EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */
+
+  EXTRACT_IFMT_INT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u8) = f_u8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andccr", "f_u8 0x%x", 'x', f_u8, (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STILM) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stilm.f
+  EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */
+
+  EXTRACT_IFMT_INT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u8) = f_u8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stilm", "f_u8 0x%x", 'x', f_u8, (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDSP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_addsp.f
+  EXTRACT_IFMT_ADDSP_VARS /* f-op1 f-op2 f-s10 */
+
+  EXTRACT_IFMT_ADDSP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_s10) = f_s10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addsp", "f_s10 0x%x", 'x', f_s10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EXTSB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_extsb.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extsb", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EXTUB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_extub.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extub", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EXTSH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_extsh.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extsh", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EXTUH) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_extuh.f
+  EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */
+
+  EXTRACT_IFMT_DIV0S_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extuh", "Ri 0x%x", 'x', f_Ri, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDM0) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldm0.f
+  EXTRACT_IFMT_LDM0_VARS /* f-op1 f-op2 f-reglist_low_ld */
+
+  EXTRACT_IFMT_LDM0_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_reglist_low_ld) = f_reglist_low_ld;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldm0", "f_reglist_low_ld 0x%x", 'x', f_reglist_low_ld, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_0) = 0;
+      FLD (out_h_gr_1) = 1;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_2) = 2;
+      FLD (out_h_gr_3) = 3;
+      FLD (out_h_gr_4) = 4;
+      FLD (out_h_gr_5) = 5;
+      FLD (out_h_gr_6) = 6;
+      FLD (out_h_gr_7) = 7;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDM1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldm1.f
+  EXTRACT_IFMT_LDM1_VARS /* f-op1 f-op2 f-reglist_hi_ld */
+
+  EXTRACT_IFMT_LDM1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_reglist_hi_ld) = f_reglist_hi_ld;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldm1", "f_reglist_hi_ld 0x%x", 'x', f_reglist_hi_ld, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_10) = 10;
+      FLD (out_h_gr_11) = 11;
+      FLD (out_h_gr_12) = 12;
+      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_8) = 8;
+      FLD (out_h_gr_9) = 9;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STM0) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stm0.f
+  EXTRACT_IFMT_STM0_VARS /* f-op1 f-op2 f-reglist_low_st */
+
+  EXTRACT_IFMT_STM0_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_reglist_low_st) = f_reglist_low_st;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stm0", "f_reglist_low_st 0x%x", 'x', f_reglist_low_st, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_0) = 0;
+      FLD (in_h_gr_1) = 1;
+      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_2) = 2;
+      FLD (in_h_gr_3) = 3;
+      FLD (in_h_gr_4) = 4;
+      FLD (in_h_gr_5) = 5;
+      FLD (in_h_gr_6) = 6;
+      FLD (in_h_gr_7) = 7;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STM1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stm1.f
+  EXTRACT_IFMT_STM1_VARS /* f-op1 f-op2 f-reglist_hi_st */
+
+  EXTRACT_IFMT_STM1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_reglist_hi_st) = f_reglist_hi_st;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stm1", "f_reglist_hi_st 0x%x", 'x', f_reglist_hi_st, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_10) = 10;
+      FLD (in_h_gr_11) = 11;
+      FLD (in_h_gr_12) = 12;
+      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_8) = 8;
+      FLD (in_h_gr_9) = 9;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ENTER) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_enter.f
+  EXTRACT_IFMT_ENTER_VARS /* f-op1 f-op2 f-u10 */
+
+  EXTRACT_IFMT_ENTER_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u10) = f_u10;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_enter", "f_u10 0x%x", 'x', f_u10, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LEAVE) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_leave.f
+  EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */
+
+  EXTRACT_IFMT_DIV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_leave", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_XCHB) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_xchb.f
+  EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */
+
+  EXTRACT_IFMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_Ri) = & CPU (h_gr)[f_Ri];
+  FLD (i_Rj) = & CPU (h_gr)[f_Rj];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_xchb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_Ri) = f_Ri;
+      FLD (in_Rj) = f_Rj;
+      FLD (out_Ri) = f_Ri;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+
+      }
+    ENDSWITCH (ex)
+
+  }
+
+  return idecode->idesc;
+}
diff --git a/sim/fr30/decode.h b/sim/fr30/decode.h
new file mode 100644
index 00000000000..4bc943ee95b
--- /dev/null
+++ b/sim/fr30/decode.h
@@ -0,0 +1,289 @@
+/* Decode header for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30BF_DECODE_H
+#define FR30BF_DECODE_H
+
+extern const IDESC *fr30bf_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void fr30bf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family fr30bf.  */
+typedef enum fr30bf_insn_type {
+  FR30BF_INSN_X_INVALID, FR30BF_INSN_X_AFTER, FR30BF_INSN_X_BEFORE, FR30BF_INSN_X_CTI_CHAIN
+ , FR30BF_INSN_X_CHAIN, FR30BF_INSN_X_BEGIN, FR30BF_INSN_ADD, FR30BF_INSN_ADDI
+ , FR30BF_INSN_ADD2, FR30BF_INSN_ADDC, FR30BF_INSN_ADDN, FR30BF_INSN_ADDNI
+ , FR30BF_INSN_ADDN2, FR30BF_INSN_SUB, FR30BF_INSN_SUBC, FR30BF_INSN_SUBN
+ , FR30BF_INSN_CMP, FR30BF_INSN_CMPI, FR30BF_INSN_CMP2, FR30BF_INSN_AND
+ , FR30BF_INSN_OR, FR30BF_INSN_EOR, FR30BF_INSN_ANDM, FR30BF_INSN_ANDH
+ , FR30BF_INSN_ANDB, FR30BF_INSN_ORM, FR30BF_INSN_ORH, FR30BF_INSN_ORB
+ , FR30BF_INSN_EORM, FR30BF_INSN_EORH, FR30BF_INSN_EORB, FR30BF_INSN_BANDL
+ , FR30BF_INSN_BORL, FR30BF_INSN_BEORL, FR30BF_INSN_BANDH, FR30BF_INSN_BORH
+ , FR30BF_INSN_BEORH, FR30BF_INSN_BTSTL, FR30BF_INSN_BTSTH, FR30BF_INSN_MUL
+ , FR30BF_INSN_MULU, FR30BF_INSN_MULH, FR30BF_INSN_MULUH, FR30BF_INSN_DIV0S
+ , FR30BF_INSN_DIV0U, FR30BF_INSN_DIV1, FR30BF_INSN_DIV2, FR30BF_INSN_DIV3
+ , FR30BF_INSN_DIV4S, FR30BF_INSN_LSL, FR30BF_INSN_LSLI, FR30BF_INSN_LSL2
+ , FR30BF_INSN_LSR, FR30BF_INSN_LSRI, FR30BF_INSN_LSR2, FR30BF_INSN_ASR
+ , FR30BF_INSN_ASRI, FR30BF_INSN_ASR2, FR30BF_INSN_LDI8, FR30BF_INSN_LDI20
+ , FR30BF_INSN_LDI32, FR30BF_INSN_LD, FR30BF_INSN_LDUH, FR30BF_INSN_LDUB
+ , FR30BF_INSN_LDR13, FR30BF_INSN_LDR13UH, FR30BF_INSN_LDR13UB, FR30BF_INSN_LDR14
+ , FR30BF_INSN_LDR14UH, FR30BF_INSN_LDR14UB, FR30BF_INSN_LDR15, FR30BF_INSN_LDR15GR
+ , FR30BF_INSN_LDR15DR, FR30BF_INSN_LDR15PS, FR30BF_INSN_ST, FR30BF_INSN_STH
+ , FR30BF_INSN_STB, FR30BF_INSN_STR13, FR30BF_INSN_STR13H, FR30BF_INSN_STR13B
+ , FR30BF_INSN_STR14, FR30BF_INSN_STR14H, FR30BF_INSN_STR14B, FR30BF_INSN_STR15
+ , FR30BF_INSN_STR15GR, FR30BF_INSN_STR15DR, FR30BF_INSN_STR15PS, FR30BF_INSN_MOV
+ , FR30BF_INSN_MOVDR, FR30BF_INSN_MOVPS, FR30BF_INSN_MOV2DR, FR30BF_INSN_MOV2PS
+ , FR30BF_INSN_JMP, FR30BF_INSN_JMPD, FR30BF_INSN_CALLR, FR30BF_INSN_CALLRD
+ , FR30BF_INSN_CALL, FR30BF_INSN_CALLD, FR30BF_INSN_RET, FR30BF_INSN_RET_D
+ , FR30BF_INSN_INT, FR30BF_INSN_INTE, FR30BF_INSN_RETI, FR30BF_INSN_BRAD
+ , FR30BF_INSN_BRA, FR30BF_INSN_BNOD, FR30BF_INSN_BNO, FR30BF_INSN_BEQD
+ , FR30BF_INSN_BEQ, FR30BF_INSN_BNED, FR30BF_INSN_BNE, FR30BF_INSN_BCD
+ , FR30BF_INSN_BC, FR30BF_INSN_BNCD, FR30BF_INSN_BNC, FR30BF_INSN_BND
+ , FR30BF_INSN_BN, FR30BF_INSN_BPD, FR30BF_INSN_BP, FR30BF_INSN_BVD
+ , FR30BF_INSN_BV, FR30BF_INSN_BNVD, FR30BF_INSN_BNV, FR30BF_INSN_BLTD
+ , FR30BF_INSN_BLT, FR30BF_INSN_BGED, FR30BF_INSN_BGE, FR30BF_INSN_BLED
+ , FR30BF_INSN_BLE, FR30BF_INSN_BGTD, FR30BF_INSN_BGT, FR30BF_INSN_BLSD
+ , FR30BF_INSN_BLS, FR30BF_INSN_BHID, FR30BF_INSN_BHI, FR30BF_INSN_DMOVR13
+ , FR30BF_INSN_DMOVR13H, FR30BF_INSN_DMOVR13B, FR30BF_INSN_DMOVR13PI, FR30BF_INSN_DMOVR13PIH
+ , FR30BF_INSN_DMOVR13PIB, FR30BF_INSN_DMOVR15PI, FR30BF_INSN_DMOV2R13, FR30BF_INSN_DMOV2R13H
+ , FR30BF_INSN_DMOV2R13B, FR30BF_INSN_DMOV2R13PI, FR30BF_INSN_DMOV2R13PIH, FR30BF_INSN_DMOV2R13PIB
+ , FR30BF_INSN_DMOV2R15PD, FR30BF_INSN_LDRES, FR30BF_INSN_STRES, FR30BF_INSN_COPOP
+ , FR30BF_INSN_COPLD, FR30BF_INSN_COPST, FR30BF_INSN_COPSV, FR30BF_INSN_NOP
+ , FR30BF_INSN_ANDCCR, FR30BF_INSN_ORCCR, FR30BF_INSN_STILM, FR30BF_INSN_ADDSP
+ , FR30BF_INSN_EXTSB, FR30BF_INSN_EXTUB, FR30BF_INSN_EXTSH, FR30BF_INSN_EXTUH
+ , FR30BF_INSN_LDM0, FR30BF_INSN_LDM1, FR30BF_INSN_STM0, FR30BF_INSN_STM1
+ , FR30BF_INSN_ENTER, FR30BF_INSN_LEAVE, FR30BF_INSN_XCHB, FR30BF_INSN_MAX
+} FR30BF_INSN_TYPE;
+
+#if ! WITH_SEM_SWITCH_FULL
+#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,fn);
+#else
+#define SEMFULL(fn)
+#endif
+
+#if ! WITH_SEM_SWITCH_FAST
+#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_semf_,fn);
+#else
+#define SEMFAST(fn)
+#endif
+
+#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
+
+/* The function version of the before/after handlers is always needed,
+   so we always want the SEMFULL declaration of them.  */
+extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_before);
+extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_after);
+
+SEM (x_invalid)
+SEM (x_after)
+SEM (x_before)
+SEM (x_cti_chain)
+SEM (x_chain)
+SEM (x_begin)
+SEM (add)
+SEM (addi)
+SEM (add2)
+SEM (addc)
+SEM (addn)
+SEM (addni)
+SEM (addn2)
+SEM (sub)
+SEM (subc)
+SEM (subn)
+SEM (cmp)
+SEM (cmpi)
+SEM (cmp2)
+SEM (and)
+SEM (or)
+SEM (eor)
+SEM (andm)
+SEM (andh)
+SEM (andb)
+SEM (orm)
+SEM (orh)
+SEM (orb)
+SEM (eorm)
+SEM (eorh)
+SEM (eorb)
+SEM (bandl)
+SEM (borl)
+SEM (beorl)
+SEM (bandh)
+SEM (borh)
+SEM (beorh)
+SEM (btstl)
+SEM (btsth)
+SEM (mul)
+SEM (mulu)
+SEM (mulh)
+SEM (muluh)
+SEM (div0s)
+SEM (div0u)
+SEM (div1)
+SEM (div2)
+SEM (div3)
+SEM (div4s)
+SEM (lsl)
+SEM (lsli)
+SEM (lsl2)
+SEM (lsr)
+SEM (lsri)
+SEM (lsr2)
+SEM (asr)
+SEM (asri)
+SEM (asr2)
+SEM (ldi8)
+SEM (ldi20)
+SEM (ldi32)
+SEM (ld)
+SEM (lduh)
+SEM (ldub)
+SEM (ldr13)
+SEM (ldr13uh)
+SEM (ldr13ub)
+SEM (ldr14)
+SEM (ldr14uh)
+SEM (ldr14ub)
+SEM (ldr15)
+SEM (ldr15gr)
+SEM (ldr15dr)
+SEM (ldr15ps)
+SEM (st)
+SEM (sth)
+SEM (stb)
+SEM (str13)
+SEM (str13h)
+SEM (str13b)
+SEM (str14)
+SEM (str14h)
+SEM (str14b)
+SEM (str15)
+SEM (str15gr)
+SEM (str15dr)
+SEM (str15ps)
+SEM (mov)
+SEM (movdr)
+SEM (movps)
+SEM (mov2dr)
+SEM (mov2ps)
+SEM (jmp)
+SEM (jmpd)
+SEM (callr)
+SEM (callrd)
+SEM (call)
+SEM (calld)
+SEM (ret)
+SEM (ret_d)
+SEM (int)
+SEM (inte)
+SEM (reti)
+SEM (brad)
+SEM (bra)
+SEM (bnod)
+SEM (bno)
+SEM (beqd)
+SEM (beq)
+SEM (bned)
+SEM (bne)
+SEM (bcd)
+SEM (bc)
+SEM (bncd)
+SEM (bnc)
+SEM (bnd)
+SEM (bn)
+SEM (bpd)
+SEM (bp)
+SEM (bvd)
+SEM (bv)
+SEM (bnvd)
+SEM (bnv)
+SEM (bltd)
+SEM (blt)
+SEM (bged)
+SEM (bge)
+SEM (bled)
+SEM (ble)
+SEM (bgtd)
+SEM (bgt)
+SEM (blsd)
+SEM (bls)
+SEM (bhid)
+SEM (bhi)
+SEM (dmovr13)
+SEM (dmovr13h)
+SEM (dmovr13b)
+SEM (dmovr13pi)
+SEM (dmovr13pih)
+SEM (dmovr13pib)
+SEM (dmovr15pi)
+SEM (dmov2r13)
+SEM (dmov2r13h)
+SEM (dmov2r13b)
+SEM (dmov2r13pi)
+SEM (dmov2r13pih)
+SEM (dmov2r13pib)
+SEM (dmov2r15pd)
+SEM (ldres)
+SEM (stres)
+SEM (copop)
+SEM (copld)
+SEM (copst)
+SEM (copsv)
+SEM (nop)
+SEM (andccr)
+SEM (orccr)
+SEM (stilm)
+SEM (addsp)
+SEM (extsb)
+SEM (extub)
+SEM (extsh)
+SEM (extuh)
+SEM (ldm0)
+SEM (ldm1)
+SEM (stm0)
+SEM (stm1)
+SEM (enter)
+SEM (leave)
+SEM (xchb)
+
+#undef SEMFULL
+#undef SEMFAST
+#undef SEM
+
+/* Function unit handlers (user written).  */
+
+extern int fr30bf_model_fr30_1_u_stm (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*reglist*/);
+extern int fr30bf_model_fr30_1_u_ldm (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*reglist*/);
+extern int fr30bf_model_fr30_1_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/, INT /*Rj*/);
+extern int fr30bf_model_fr30_1_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rj*/, INT /*Ri*/);
+extern int fr30bf_model_fr30_1_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/);
+extern int fr30bf_model_fr30_1_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/, INT /*Rj*/, INT /*Ri*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void fr30bf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void fr30bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* FR30BF_DECODE_H */
diff --git a/sim/fr30/devices.c b/sim/fr30/devices.c
new file mode 100644
index 00000000000..f378a525cc3
--- /dev/null
+++ b/sim/fr30/devices.c
@@ -0,0 +1,99 @@
+/* fr30 device support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? All of this is just to get something going.  wip!  */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+device fr30_devices;
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+		       address_word addr, unsigned nr_bytes,
+		       SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#ifdef HAVE_DV_SOCKSER
+  if (addr == UART_INCHAR_ADDR)
+    {
+      int c = dv_sockser_read (sd);
+      if (c == -1)
+	return 0;
+      *(char *) source = c;
+      return 1;
+    }
+  if (addr == UART_STATUS_ADDR)
+    {
+      int status = dv_sockser_status (sd);
+      unsigned char *p = source;
+      p[0] = 0;
+      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
+#ifdef UART_INPUT_READY0
+	       ? UART_INPUT_READY : 0)
+#else
+	       ? 0 : UART_INPUT_READY)
+#endif
+	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
+      return 2;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+			address_word addr, unsigned nr_bytes,
+			SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+#if WITH_SCACHE
+  if (addr == MCCR_ADDR)
+    {
+      if ((*(const char *) source & MCCR_CP) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#if HAVE_DV_SOCKSER
+  if (addr == UART_OUTCHAR_ADDR)
+    {
+      int rc = dv_sockser_write (sd, *(char *) source);
+      return rc == 1;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+void device_error () {}
diff --git a/sim/fr30/fr30-sim.h b/sim/fr30/fr30-sim.h
new file mode 100644
index 00000000000..b9018efe6d4
--- /dev/null
+++ b/sim/fr30/fr30-sim.h
@@ -0,0 +1,108 @@
+/* collection of junk waiting time to sort out
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef FR30_SIM_H
+#define FR30_SIM_H
+
+/* gdb register numbers */
+#define PC_REGNUM	16
+#define PS_REGNUM	17
+#define TBR_REGNUM	18
+#define RP_REGNUM	19
+#define SSP_REGNUM	20
+#define USP_REGNUM	21
+#define MDH_REGNUM	22
+#define MDL_REGNUM	23
+
+extern BI fr30bf_h_sbit_get_handler (SIM_CPU *);
+extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI);
+#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
+#define SET_H_SBIT(val) fr30bf_h_sbit_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *);
+extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI);
+#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
+#define SET_H_CCR(val) fr30bf_h_ccr_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_scr_get_handler (SIM_CPU *);
+extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI);
+#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
+#define SET_H_SCR(val) fr30bf_h_scr_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *);
+extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI);
+#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
+#define SET_H_ILM(val) fr30bf_h_ilm_set_handler (current_cpu, (val))
+
+extern USI fr30bf_h_ps_get_handler (SIM_CPU *);
+extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI);
+#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
+#define SET_H_PS(val) fr30bf_h_ps_set_handler (current_cpu, (val))
+
+extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT);
+extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI);
+#define GET_H_DR(regno) fr30bf_h_dr_get_handler (current_cpu, (regno))
+#define SET_H_DR(regno, val) fr30bf_h_dr_set_handler (current_cpu, (regno), (val))
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+
+/* Hardware/device support.
+   ??? Will eventually want to move device stuff to config files.  */
+
+/* Special purpose traps.  */
+#define TRAP_SYSCALL	10
+#define TRAP_BREAKPOINT	9
+
+/* Support for the MCCR register (Cache Control Register) is needed in order
+   for overlays to work correctly with the scache: cached instructions need
+   to be flushed when the instruction space is changed at runtime.  */
+
+/* Cache Control Register */
+#define MCCR_ADDR 0xffffffff
+#define MCCR_CP 0x80
+/* not supported */
+#define MCCR_CM0 2
+#define MCCR_CM1 1
+
+/* Serial device addresses.  */
+/* These are the values for the MSA2000 board.
+   ??? Will eventually need to move this to a config file.  */
+#define UART_INCHAR_ADDR	0xff004009
+#define UART_OUTCHAR_ADDR	0xff004007
+#define UART_STATUS_ADDR	0xff004002
+
+#define UART_INPUT_READY	0x4
+#define UART_OUTPUT_READY	0x1
+
+/* Start address and length of all device support.  */
+#define FR30_DEVICE_ADDR	0xff000000
+#define FR30_DEVICE_LEN		0x00ffffff
+
+/* sim_core_attach device argument.  */
+extern device fr30_devices;
+
+/* FIXME: Temporary, until device support ready.  */
+struct _device { int foo; };
+
+/* Handle the trap insn.  */
+USI fr30_int (SIM_CPU *, PCADDR, int);
+
+#endif /* FR30_SIM_H */
diff --git a/sim/fr30/fr30.c b/sim/fr30/fr30.c
new file mode 100644
index 00000000000..78b9b7ce8b2
--- /dev/null
+++ b/sim/fr30/fr30.c
@@ -0,0 +1,423 @@
+/* fr30 simulator support code
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* Convert gdb dedicated register number to actual dr reg number.  */
+
+static int
+decode_gdb_dr_regnum (int gdb_regnum)
+{
+  switch (gdb_regnum)
+    {
+    case TBR_REGNUM : return H_DR_TBR;
+    case RP_REGNUM : return H_DR_RP;
+    case SSP_REGNUM : return H_DR_SSP;
+    case USP_REGNUM : return H_DR_USP;
+    case MDH_REGNUM : return H_DR_MDH;
+    case MDL_REGNUM : return H_DR_MDL;
+    }
+  abort ();
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn < 16)
+    SETTWI (buf, a_fr30_h_gr_get (current_cpu, rn));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	SETTWI (buf, a_fr30_h_pc_get (current_cpu));
+	break;
+      case PS_REGNUM :
+	SETTWI (buf, a_fr30_h_ps_get (current_cpu));
+	break;
+      case TBR_REGNUM :
+      case RP_REGNUM :
+      case SSP_REGNUM :
+      case USP_REGNUM :
+      case MDH_REGNUM :
+      case MDL_REGNUM :
+	SETTWI (buf, a_fr30_h_dr_get (current_cpu,
+				      decode_gdb_dr_regnum (rn)));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn < 16)
+    a_fr30_h_gr_set (current_cpu, rn, GETTWI (buf));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	a_fr30_h_pc_set (current_cpu, GETTWI (buf));
+	break;
+      case PS_REGNUM :
+	a_fr30_h_ps_set (current_cpu, GETTWI (buf));
+	break;
+      case TBR_REGNUM :
+      case RP_REGNUM :
+      case SSP_REGNUM :
+      case USP_REGNUM :
+      case MDH_REGNUM :
+      case MDL_REGNUM :
+	a_fr30_h_dr_set (current_cpu,
+			 decode_gdb_dr_regnum (rn),
+			 GETTWI (buf));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+}
+
+/* Cover fns to access the ccr bits.  */
+
+BI
+fr30bf_h_sbit_get_handler (SIM_CPU *current_cpu)
+{
+  return CPU (h_sbit);
+}
+
+void
+fr30bf_h_sbit_set_handler (SIM_CPU *current_cpu, BI newval)
+{
+  int old_sbit = CPU (h_sbit);
+  int new_sbit = (newval != 0);
+
+  CPU (h_sbit) = new_sbit;
+
+  /* When switching stack modes, update the registers.  */
+  if (old_sbit != new_sbit)
+    {
+      if (old_sbit)
+	{
+	  /* Switching user -> system.  */
+	  CPU (h_dr[H_DR_USP]) = CPU (h_gr[H_GR_SP]);
+	  CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_SSP]);
+	}
+      else
+	{
+	  /* Switching system -> user.  */
+	  CPU (h_dr[H_DR_SSP]) = CPU (h_gr[H_GR_SP]);
+	  CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_USP]);
+	}
+    }
+
+  /* TODO: r15 interlock */
+}
+
+/* Cover fns to access the ccr bits.  */
+
+UQI
+fr30bf_h_ccr_get_handler (SIM_CPU *current_cpu)
+{
+  int ccr = (  (GET_H_CBIT () << 0)
+	     | (GET_H_VBIT () << 1)
+	     | (GET_H_ZBIT () << 2)
+	     | (GET_H_NBIT () << 3)
+	     | (GET_H_IBIT () << 4)
+	     | (GET_H_SBIT () << 5));
+
+  return ccr;
+}
+
+void
+fr30bf_h_ccr_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int ccr = newval & 0x3f;
+
+  SET_H_CBIT ((ccr & 1) != 0);
+  SET_H_VBIT ((ccr & 2) != 0);
+  SET_H_ZBIT ((ccr & 4) != 0);
+  SET_H_NBIT ((ccr & 8) != 0);
+  SET_H_IBIT ((ccr & 0x10) != 0);
+  SET_H_SBIT ((ccr & 0x20) != 0);
+}
+
+/* Cover fns to access the scr bits.  */
+
+UQI
+fr30bf_h_scr_get_handler (SIM_CPU *current_cpu)
+{
+  int scr = (  (GET_H_TBIT () << 0)
+	     | (GET_H_D0BIT () << 1)
+	     | (GET_H_D1BIT () << 2));
+  return scr;
+}
+
+void
+fr30bf_h_scr_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int scr = newval & 7;
+
+  SET_H_TBIT  ((scr & 1) != 0);
+  SET_H_D0BIT ((scr & 2) != 0);
+  SET_H_D1BIT ((scr & 4) != 0);
+}
+
+/* Cover fns to access the ilm bits.  */
+
+UQI
+fr30bf_h_ilm_get_handler (SIM_CPU *current_cpu)
+{
+  return CPU (h_ilm);
+}
+
+void
+fr30bf_h_ilm_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int ilm = newval & 0x1f;
+  int current_ilm = CPU (h_ilm);
+
+  /* We can only set new ilm values < 16 if the current ilm is < 16.  Otherwise
+     we add 16 to the value we are given.  */
+  if (current_ilm >= 16 && ilm < 16)
+    ilm += 16;
+
+  CPU (h_ilm) = ilm;
+}
+
+/* Cover fns to access the ps register.  */
+
+USI
+fr30bf_h_ps_get_handler (SIM_CPU *current_cpu)
+{
+  int ccr = GET_H_CCR ();
+  int scr = GET_H_SCR ();
+  int ilm = GET_H_ILM ();
+
+  return ccr | (scr << 8) | (ilm << 16);
+}
+
+void
+fr30bf_h_ps_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int ccr = newval & 0xff;
+  int scr = (newval >> 8) & 7;
+  int ilm = (newval >> 16) & 0x1f;
+
+  SET_H_CCR (ccr);
+  SET_H_SCR (scr);
+  SET_H_ILM (ilm);
+}
+
+/* Cover fns to access the dedicated registers.  */
+
+SI
+fr30bf_h_dr_get_handler (SIM_CPU *current_cpu, UINT dr)
+{
+  switch (dr)
+    {
+    case H_DR_SSP :
+      if (! GET_H_SBIT ())
+	return GET_H_GR (H_GR_SP);
+      else
+	return CPU (h_dr[H_DR_SSP]);
+    case H_DR_USP :
+      if (GET_H_SBIT ())
+	return GET_H_GR (H_GR_SP);
+      else
+	return CPU (h_dr[H_DR_USP]);
+    case H_DR_TBR :
+    case H_DR_RP :
+    case H_DR_MDH :
+    case H_DR_MDL :
+      return CPU (h_dr[dr]);
+    }
+  return 0;
+}
+
+void
+fr30bf_h_dr_set_handler (SIM_CPU *current_cpu, UINT dr, SI newval)
+{
+  switch (dr)
+    {
+    case H_DR_SSP :
+      if (! GET_H_SBIT ())
+	SET_H_GR (H_GR_SP, newval);
+      else
+	CPU (h_dr[H_DR_SSP]) = newval;
+      break;
+    case H_DR_USP :
+      if (GET_H_SBIT ())
+	SET_H_GR (H_GR_SP, newval);
+      else
+	CPU (h_dr[H_DR_USP]) = newval;
+      break;
+    case H_DR_TBR :
+    case H_DR_RP :
+    case H_DR_MDH :
+    case H_DR_MDL :
+      CPU (h_dr[dr]) = newval;
+      break;
+    }
+}
+
+#if WITH_PROFILE_MODEL_P
+
+/* FIXME: Some of these should be inline or macros.  Later.  */
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+fr30bf_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  d->load_regs_pending = 0;
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+fr30bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+
+  PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
+  PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
+  d->load_regs = d->load_regs_pending;
+}
+
+static INLINE int
+check_load_stall (SIM_CPU *cpu, int regno)
+{
+  const MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  UINT load_regs = d->load_regs;
+
+  if (regno != -1
+      && (load_regs & (1 << regno)) != 0)
+    {
+      PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+      ++ PROFILE_MODEL_LOAD_STALL_CYCLES (p);
+      if (TRACE_INSN_P (cpu))
+	cgen_trace_printf (cpu, " ; Load stall.");
+      return 1;
+    }
+  else
+    return 0;
+}
+
+int
+fr30bf_model_fr30_1_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_Ri, INT in_Rj, INT out_Ri)
+{
+  int cycles = idesc->timing->units[unit_num].done;
+  cycles += check_load_stall (cpu, in_Ri);
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_cti (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_Ri)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  /* (1 << 1): The pc is the 2nd element in inputs, outputs.
+     ??? can be cleaned up */
+  int taken_p = (referenced & (1 << 1)) != 0;
+  int cycles = idesc->timing->units[unit_num].done;
+  int delay_slot_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT);
+
+  cycles += check_load_stall (cpu, in_Ri);
+  if (taken_p)
+    {
+      /* ??? Handling cti's without delay slots this way will run afoul of
+	 accurate system simulation.  Later.  */
+      if (! delay_slot_p)
+	{
+	  ++cycles;
+	  ++PROFILE_MODEL_CTI_STALL_CYCLES (p);
+	}
+      ++PROFILE_MODEL_TAKEN_COUNT (p);
+    }
+  else
+    ++PROFILE_MODEL_UNTAKEN_COUNT (p);
+
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_load (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_Rj, INT out_Ri)
+{
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  int cycles = idesc->timing->units[unit_num].done;
+  d->load_regs_pending |= 1 << out_Ri;
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_store (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_Ri, INT in_Rj)
+{
+  int cycles = idesc->timing->units[unit_num].done;
+  cycles += check_load_stall (cpu, in_Ri);
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_ldm (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT reglist)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+fr30bf_model_fr30_1_u_stm (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT reglist)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/fr30/mloop.in b/sim/fr30/mloop.in
new file mode 100644
index 00000000000..1a82d8332b6
--- /dev/null
+++ b/sim/fr30/mloop.in
@@ -0,0 +1,236 @@
+# Simulator main loop for fr30. -*- C -*-
+# Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+# Contributed by Cygnus Solutions.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this, however for illustration's sake the FR30
+# port provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+         int fast_p)
+{
+  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, abuf);
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  if (! fast_p)
+    {
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+    }
+  return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+  SEM_PC vpc;
+
+  if (fast_p)
+    {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+    }
+  else
+    {
+#if ! WITH_SEM_SWITCH_FULL
+      ARGBUF *abuf = &sc->argbuf;
+      const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+      int virtual_p = 0;
+#endif
+
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-before */
+	  if (ARGBUF_PROFILE_P (abuf))
+	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+	  TRACE_INSN_INIT (current_cpu, abuf, 1);
+	  TRACE_INSN (current_cpu, idesc->idata,
+		      (const struct argbuf *) abuf, abuf->addr);
+	}
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-after */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    {
+	      int cycles;
+
+	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+	    }
+	  TRACE_INSN_FINI (current_cpu, abuf, 1);
+	}
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+    }
+
+  return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+/*xxxinit*/
+EOF
+
+;;
+
+xextract-simple | xextract-scache)
+
+# Inputs:  current_cpu, vpc, sc, FAST_P
+# Outputs: sc filled in
+
+cat <<EOF
+{
+  CGEN_INSN_INT insn = GETIMEMUHI (current_cpu, vpc);
+  extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+  const IDESC *idesc;
+  int icount = 0;
+
+  while (max_insns > 0)
+    {
+      UHI insn = GETIMEMUHI (current_cpu, pc);
+      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+      ++sc;
+      --max_insns;
+      ++icount;
+      pc += idesc->length;
+      if (IDESC_CTI_P (idesc))
+	{
+	  SET_CTI_VPC (sc - 1);
+
+	  /* Delay slot? */
+	  /* ??? breakpoints in delay slots */
+	  if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+	    {
+	      UHI insn = GETIMEMUHI (current_cpu, pc);
+	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+	      if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_NOT_IN_DELAY_SLOT))
+		{
+		  /* malformed program */
+		  sim_io_eprintf (CPU_STATE (current_cpu),
+				  "malformed program, \`%s' insn in delay slot\n",
+				  CGEN_INSN_NAME (idesc->idata));
+		}
+	      else
+		{
+		  ++sc;
+		  --max_insns;
+		  ++icount;
+		  pc += idesc->length;
+		}
+	    }
+	  break;
+	}
+    }
+
+ Finish:
+  SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, sc, FAST_P
+# Outputs: vpc
+# vpc contains the address of the next insn to execute
+
+cat <<EOF
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-switch.c"
+#else
+  vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/fr30/model.c b/sim/fr30/model.c
new file mode 100644
index 00000000000..7be6305e407
--- /dev/null
+++ b/sim/fr30/model.c
@@ -0,0 +1,4004 @@
+/* Simulator model support for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU fr30bf
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+   mechanism.  After all, this is information for profiling.  */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn.  */
+
+static int
+model_fr30_1_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_add2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addni (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addni.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addn2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_subc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_subn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_cmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_cmpi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_cmp2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmp2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_eor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_andm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_andh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_andb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_orm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_orh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_orb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_eorm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_eorh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_eorb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bandl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_borl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_beorl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bandh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_borh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_beorh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 1, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 2, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_btstl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_btstl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 1, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_btsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_btstl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 1, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mul.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mulu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mulh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_muluh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div0s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div0s.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div0u (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div0u.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_div4s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div4s.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsl2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lsr2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_asr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_asri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_asr2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldi20 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi20.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldi32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi32.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lduh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldub.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr13uh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13uh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr13ub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13ub.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr14 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr14uh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14uh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr14ub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14ub.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr15 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr15gr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15gr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr15dr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15dr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldr15ps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15ps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_sth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str13h (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13h.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str13b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str14 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str14h (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14h.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str14b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str15 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str15gr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15gr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str15dr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15dr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_str15ps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15ps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mov (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_movdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movdr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_movps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mov2dr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov2dr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_mov2ps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov2ps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_jmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_jmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_callr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_callrd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_calld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ret (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ret_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_int (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_int.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_inte (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_inte.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_reti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_reti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_brad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bnod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bnod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bnod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_beqd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bned (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bcd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bncd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bnd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bvd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bnvd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bltd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bged (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bled (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bgtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_blsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bhid (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_cti (current_cpu, idesc, 0, referenced, in_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13h (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13h.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 0, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13pi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13pih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr13pib (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pib.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmovr15pi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr15pi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13h (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13h.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13pi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13pih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r13pib (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pib.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_dmov2r15pd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r15pd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldres (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldres.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_stres (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldres.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_copop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copop.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_copld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copld.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_copst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copst.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_copsv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copst.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_nop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_nop.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_andccr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andccr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_orccr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andccr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_stilm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stilm.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_addsp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addsp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_extsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extsb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_extub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extub.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_extsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_extuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extuh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Ri = FLD (in_Ri);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldm0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldm0.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_reglist = 0;
+    cycles += fr30bf_model_fr30_1_u_ldm (current_cpu, idesc, 0, referenced, in_reglist);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_ldm1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldm1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_reglist = 0;
+    cycles += fr30bf_model_fr30_1_u_ldm (current_cpu, idesc, 0, referenced, in_reglist);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_stm0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stm0.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_reglist = 0;
+    cycles += fr30bf_model_fr30_1_u_stm (current_cpu, idesc, 0, referenced, in_reglist);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_stm1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stm1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_reglist = 0;
+    cycles += fr30bf_model_fr30_1_u_stm (current_cpu, idesc, 0, referenced, in_reglist);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_enter (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_enter.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_leave (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_leave.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    cycles += fr30bf_model_fr30_1_u_exec (current_cpu, idesc, 0, referenced, in_Ri, in_Rj, out_Ri);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr30_1_xchb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_xchb.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Rj = -1;
+    INT out_Ri = -1;
+    in_Rj = FLD (in_Rj);
+    out_Ri = FLD (out_Ri);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_load (current_cpu, idesc, 0, referenced, in_Rj, out_Ri);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_Ri = -1;
+    INT in_Rj = -1;
+    in_Ri = FLD (in_Ri);
+    in_Rj = FLD (in_Rj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += fr30bf_model_fr30_1_u_store (current_cpu, idesc, 1, referenced, in_Ri, in_Rj);
+  }
+  return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+   entries with it.  */
+
+/* Model timing data for `fr30-1'.  */
+
+static const INSN_TIMING fr30_1_timing[] = {
+  { FR30BF_INSN_X_INVALID, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_X_AFTER, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_X_BEFORE, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_X_CHAIN, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_X_BEGIN, 0, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADD, model_fr30_1_add, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDI, model_fr30_1_addi, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADD2, model_fr30_1_add2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDC, model_fr30_1_addc, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDN, model_fr30_1_addn, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDNI, model_fr30_1_addni, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDN2, model_fr30_1_addn2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_SUB, model_fr30_1_sub, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_SUBC, model_fr30_1_subc, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_SUBN, model_fr30_1_subn, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_CMP, model_fr30_1_cmp, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_CMPI, model_fr30_1_cmpi, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_CMP2, model_fr30_1_cmp2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_AND, model_fr30_1_and, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_OR, model_fr30_1_or, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_EOR, model_fr30_1_eor, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ANDM, model_fr30_1_andm, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_ANDH, model_fr30_1_andh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_ANDB, model_fr30_1_andb, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_ORM, model_fr30_1_orm, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_ORH, model_fr30_1_orh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_ORB, model_fr30_1_orb, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_EORM, model_fr30_1_eorm, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_EORH, model_fr30_1_eorh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_EORB, model_fr30_1_eorb, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BANDL, model_fr30_1_bandl, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BORL, model_fr30_1_borl, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BEORL, model_fr30_1_beorl, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BANDH, model_fr30_1_bandh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BORH, model_fr30_1_borh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BEORH, model_fr30_1_beorh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 }, { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_BTSTL, model_fr30_1_btstl, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_EXEC, 1, 2 } } },
+  { FR30BF_INSN_BTSTH, model_fr30_1_btsth, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_EXEC, 1, 2 } } },
+  { FR30BF_INSN_MUL, model_fr30_1_mul, { { (int) UNIT_FR30_1_U_EXEC, 1, 5 } } },
+  { FR30BF_INSN_MULU, model_fr30_1_mulu, { { (int) UNIT_FR30_1_U_EXEC, 1, 5 } } },
+  { FR30BF_INSN_MULH, model_fr30_1_mulh, { { (int) UNIT_FR30_1_U_EXEC, 1, 3 } } },
+  { FR30BF_INSN_MULUH, model_fr30_1_muluh, { { (int) UNIT_FR30_1_U_EXEC, 1, 3 } } },
+  { FR30BF_INSN_DIV0S, model_fr30_1_div0s, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_DIV0U, model_fr30_1_div0u, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_DIV1, model_fr30_1_div1, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_DIV2, model_fr30_1_div2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_DIV3, model_fr30_1_div3, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_DIV4S, model_fr30_1_div4s, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSL, model_fr30_1_lsl, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSLI, model_fr30_1_lsli, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSL2, model_fr30_1_lsl2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSR, model_fr30_1_lsr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSRI, model_fr30_1_lsri, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LSR2, model_fr30_1_lsr2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ASR, model_fr30_1_asr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ASRI, model_fr30_1_asri, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ASR2, model_fr30_1_asr2, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LDI8, model_fr30_1_ldi8, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LDI20, model_fr30_1_ldi20, { { (int) UNIT_FR30_1_U_EXEC, 1, 2 } } },
+  { FR30BF_INSN_LDI32, model_fr30_1_ldi32, { { (int) UNIT_FR30_1_U_EXEC, 1, 3 } } },
+  { FR30BF_INSN_LD, model_fr30_1_ld, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDUH, model_fr30_1_lduh, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDUB, model_fr30_1_ldub, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR13, model_fr30_1_ldr13, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR13UH, model_fr30_1_ldr13uh, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR13UB, model_fr30_1_ldr13ub, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR14, model_fr30_1_ldr14, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR14UH, model_fr30_1_ldr14uh, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR14UB, model_fr30_1_ldr14ub, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR15, model_fr30_1_ldr15, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR15GR, model_fr30_1_ldr15gr, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR15DR, model_fr30_1_ldr15dr, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_LDR15PS, model_fr30_1_ldr15ps, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_ST, model_fr30_1_st, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STH, model_fr30_1_sth, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STB, model_fr30_1_stb, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR13, model_fr30_1_str13, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR13H, model_fr30_1_str13h, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR13B, model_fr30_1_str13b, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR14, model_fr30_1_str14, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR14H, model_fr30_1_str14h, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR14B, model_fr30_1_str14b, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR15, model_fr30_1_str15, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR15GR, model_fr30_1_str15gr, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR15DR, model_fr30_1_str15dr, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_STR15PS, model_fr30_1_str15ps, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_MOV, model_fr30_1_mov, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_MOVDR, model_fr30_1_movdr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_MOVPS, model_fr30_1_movps, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_MOV2DR, model_fr30_1_mov2dr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_MOV2PS, model_fr30_1_mov2ps, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_JMP, model_fr30_1_jmp, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_JMPD, model_fr30_1_jmpd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_CALLR, model_fr30_1_callr, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_CALLRD, model_fr30_1_callrd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_CALL, model_fr30_1_call, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_CALLD, model_fr30_1_calld, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_RET, model_fr30_1_ret, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_RET_D, model_fr30_1_ret_d, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_INT, model_fr30_1_int, { { (int) UNIT_FR30_1_U_EXEC, 1, 6 } } },
+  { FR30BF_INSN_INTE, model_fr30_1_inte, { { (int) UNIT_FR30_1_U_EXEC, 1, 6 } } },
+  { FR30BF_INSN_RETI, model_fr30_1_reti, { { (int) UNIT_FR30_1_U_EXEC, 1, 4 } } },
+  { FR30BF_INSN_BRAD, model_fr30_1_brad, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BRA, model_fr30_1_bra, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNOD, model_fr30_1_bnod, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNO, model_fr30_1_bno, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BEQD, model_fr30_1_beqd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BEQ, model_fr30_1_beq, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNED, model_fr30_1_bned, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNE, model_fr30_1_bne, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BCD, model_fr30_1_bcd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BC, model_fr30_1_bc, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNCD, model_fr30_1_bncd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNC, model_fr30_1_bnc, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BND, model_fr30_1_bnd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BN, model_fr30_1_bn, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BPD, model_fr30_1_bpd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BP, model_fr30_1_bp, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BVD, model_fr30_1_bvd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BV, model_fr30_1_bv, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNVD, model_fr30_1_bnvd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BNV, model_fr30_1_bnv, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLTD, model_fr30_1_bltd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLT, model_fr30_1_blt, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BGED, model_fr30_1_bged, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BGE, model_fr30_1_bge, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLED, model_fr30_1_bled, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLE, model_fr30_1_ble, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BGTD, model_fr30_1_bgtd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BGT, model_fr30_1_bgt, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLSD, model_fr30_1_blsd, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BLS, model_fr30_1_bls, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BHID, model_fr30_1_bhid, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_BHI, model_fr30_1_bhi, { { (int) UNIT_FR30_1_U_CTI, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13, model_fr30_1_dmovr13, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13H, model_fr30_1_dmovr13h, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13B, model_fr30_1_dmovr13b, { { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13PI, model_fr30_1_dmovr13pi, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13PIH, model_fr30_1_dmovr13pih, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR13PIB, model_fr30_1_dmovr13pib, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOVR15PI, model_fr30_1_dmovr15pi, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13, model_fr30_1_dmov2r13, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13H, model_fr30_1_dmov2r13h, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13B, model_fr30_1_dmov2r13b, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13PI, model_fr30_1_dmov2r13pi, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13PIH, model_fr30_1_dmov2r13pih, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R13PIB, model_fr30_1_dmov2r13pib, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_DMOV2R15PD, model_fr30_1_dmov2r15pd, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+  { FR30BF_INSN_LDRES, model_fr30_1_ldres, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_STRES, model_fr30_1_stres, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_COPOP, model_fr30_1_copop, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_COPLD, model_fr30_1_copld, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_COPST, model_fr30_1_copst, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_COPSV, model_fr30_1_copsv, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_NOP, model_fr30_1_nop, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ANDCCR, model_fr30_1_andccr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ORCCR, model_fr30_1_orccr, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_STILM, model_fr30_1_stilm, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_ADDSP, model_fr30_1_addsp, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_EXTSB, model_fr30_1_extsb, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_EXTUB, model_fr30_1_extub, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_EXTSH, model_fr30_1_extsh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_EXTUH, model_fr30_1_extuh, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_LDM0, model_fr30_1_ldm0, { { (int) UNIT_FR30_1_U_LDM, 1, 1 } } },
+  { FR30BF_INSN_LDM1, model_fr30_1_ldm1, { { (int) UNIT_FR30_1_U_LDM, 1, 1 } } },
+  { FR30BF_INSN_STM0, model_fr30_1_stm0, { { (int) UNIT_FR30_1_U_STM, 1, 1 } } },
+  { FR30BF_INSN_STM1, model_fr30_1_stm1, { { (int) UNIT_FR30_1_U_STM, 1, 1 } } },
+  { FR30BF_INSN_ENTER, model_fr30_1_enter, { { (int) UNIT_FR30_1_U_EXEC, 1, 2 } } },
+  { FR30BF_INSN_LEAVE, model_fr30_1_leave, { { (int) UNIT_FR30_1_U_EXEC, 1, 1 } } },
+  { FR30BF_INSN_XCHB, model_fr30_1_xchb, { { (int) UNIT_FR30_1_U_LOAD, 1, 1 }, { (int) UNIT_FR30_1_U_STORE, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+fr30_1_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR30_1_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL fr30_models[] =
+{
+  { "fr30-1", & fr30_mach, MODEL_FR30_1, TIMING_DATA (& fr30_1_timing[0]), fr30_1_model_init },
+  { 0 }
+};
+
+/* The properties of this cpu's implementation.  */
+
+static const MACH_IMP_PROPERTIES fr30bf_imp_properties =
+{
+  sizeof (SIM_CPU),
+#if WITH_SCACHE
+  sizeof (SCACHE)
+#else
+  0
+#endif
+};
+
+
+static void
+fr30bf_prepare_run (SIM_CPU *cpu)
+{
+  if (CPU_IDESC (cpu) == NULL)
+    fr30bf_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+fr30bf_get_idata (SIM_CPU *cpu, int inum)
+{
+  return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+fr30_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = fr30bf_fetch_register;
+  CPU_REG_STORE (cpu) = fr30bf_store_register;
+  CPU_PC_FETCH (cpu) = fr30bf_h_pc_get;
+  CPU_PC_STORE (cpu) = fr30bf_h_pc_set;
+  CPU_GET_IDATA (cpu) = fr30bf_get_idata;
+  CPU_MAX_INSNS (cpu) = FR30BF_INSN_MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = fr30bf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = fr30bf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = fr30bf_engine_run_full;
+#endif
+}
+
+const MACH fr30_mach =
+{
+  "fr30", "fr30",
+  32, 32, & fr30_models[0], & fr30bf_imp_properties,
+  fr30_init_cpu,
+  fr30bf_prepare_run
+};
+
diff --git a/sim/fr30/sem-switch.c b/sim/fr30/sem-switch.c
new file mode 100644
index 00000000000..86950b27edf
--- /dev/null
+++ b/sim/fr30/sem-switch.c
@@ -0,0 +1,5397 @@
+/* Simulator instruction semantics for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+  /* The labels have the case they have because the enum of insn types
+     is all uppercase and in the non-stdc case the insn symbol is built
+     into the enum name.  */
+
+  static struct {
+    int index;
+    void *label;
+  } labels[] = {
+    { FR30BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+    { FR30BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+    { FR30BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+    { FR30BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+    { FR30BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+    { FR30BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+    { FR30BF_INSN_ADD, && case_sem_INSN_ADD },
+    { FR30BF_INSN_ADDI, && case_sem_INSN_ADDI },
+    { FR30BF_INSN_ADD2, && case_sem_INSN_ADD2 },
+    { FR30BF_INSN_ADDC, && case_sem_INSN_ADDC },
+    { FR30BF_INSN_ADDN, && case_sem_INSN_ADDN },
+    { FR30BF_INSN_ADDNI, && case_sem_INSN_ADDNI },
+    { FR30BF_INSN_ADDN2, && case_sem_INSN_ADDN2 },
+    { FR30BF_INSN_SUB, && case_sem_INSN_SUB },
+    { FR30BF_INSN_SUBC, && case_sem_INSN_SUBC },
+    { FR30BF_INSN_SUBN, && case_sem_INSN_SUBN },
+    { FR30BF_INSN_CMP, && case_sem_INSN_CMP },
+    { FR30BF_INSN_CMPI, && case_sem_INSN_CMPI },
+    { FR30BF_INSN_CMP2, && case_sem_INSN_CMP2 },
+    { FR30BF_INSN_AND, && case_sem_INSN_AND },
+    { FR30BF_INSN_OR, && case_sem_INSN_OR },
+    { FR30BF_INSN_EOR, && case_sem_INSN_EOR },
+    { FR30BF_INSN_ANDM, && case_sem_INSN_ANDM },
+    { FR30BF_INSN_ANDH, && case_sem_INSN_ANDH },
+    { FR30BF_INSN_ANDB, && case_sem_INSN_ANDB },
+    { FR30BF_INSN_ORM, && case_sem_INSN_ORM },
+    { FR30BF_INSN_ORH, && case_sem_INSN_ORH },
+    { FR30BF_INSN_ORB, && case_sem_INSN_ORB },
+    { FR30BF_INSN_EORM, && case_sem_INSN_EORM },
+    { FR30BF_INSN_EORH, && case_sem_INSN_EORH },
+    { FR30BF_INSN_EORB, && case_sem_INSN_EORB },
+    { FR30BF_INSN_BANDL, && case_sem_INSN_BANDL },
+    { FR30BF_INSN_BORL, && case_sem_INSN_BORL },
+    { FR30BF_INSN_BEORL, && case_sem_INSN_BEORL },
+    { FR30BF_INSN_BANDH, && case_sem_INSN_BANDH },
+    { FR30BF_INSN_BORH, && case_sem_INSN_BORH },
+    { FR30BF_INSN_BEORH, && case_sem_INSN_BEORH },
+    { FR30BF_INSN_BTSTL, && case_sem_INSN_BTSTL },
+    { FR30BF_INSN_BTSTH, && case_sem_INSN_BTSTH },
+    { FR30BF_INSN_MUL, && case_sem_INSN_MUL },
+    { FR30BF_INSN_MULU, && case_sem_INSN_MULU },
+    { FR30BF_INSN_MULH, && case_sem_INSN_MULH },
+    { FR30BF_INSN_MULUH, && case_sem_INSN_MULUH },
+    { FR30BF_INSN_DIV0S, && case_sem_INSN_DIV0S },
+    { FR30BF_INSN_DIV0U, && case_sem_INSN_DIV0U },
+    { FR30BF_INSN_DIV1, && case_sem_INSN_DIV1 },
+    { FR30BF_INSN_DIV2, && case_sem_INSN_DIV2 },
+    { FR30BF_INSN_DIV3, && case_sem_INSN_DIV3 },
+    { FR30BF_INSN_DIV4S, && case_sem_INSN_DIV4S },
+    { FR30BF_INSN_LSL, && case_sem_INSN_LSL },
+    { FR30BF_INSN_LSLI, && case_sem_INSN_LSLI },
+    { FR30BF_INSN_LSL2, && case_sem_INSN_LSL2 },
+    { FR30BF_INSN_LSR, && case_sem_INSN_LSR },
+    { FR30BF_INSN_LSRI, && case_sem_INSN_LSRI },
+    { FR30BF_INSN_LSR2, && case_sem_INSN_LSR2 },
+    { FR30BF_INSN_ASR, && case_sem_INSN_ASR },
+    { FR30BF_INSN_ASRI, && case_sem_INSN_ASRI },
+    { FR30BF_INSN_ASR2, && case_sem_INSN_ASR2 },
+    { FR30BF_INSN_LDI8, && case_sem_INSN_LDI8 },
+    { FR30BF_INSN_LDI20, && case_sem_INSN_LDI20 },
+    { FR30BF_INSN_LDI32, && case_sem_INSN_LDI32 },
+    { FR30BF_INSN_LD, && case_sem_INSN_LD },
+    { FR30BF_INSN_LDUH, && case_sem_INSN_LDUH },
+    { FR30BF_INSN_LDUB, && case_sem_INSN_LDUB },
+    { FR30BF_INSN_LDR13, && case_sem_INSN_LDR13 },
+    { FR30BF_INSN_LDR13UH, && case_sem_INSN_LDR13UH },
+    { FR30BF_INSN_LDR13UB, && case_sem_INSN_LDR13UB },
+    { FR30BF_INSN_LDR14, && case_sem_INSN_LDR14 },
+    { FR30BF_INSN_LDR14UH, && case_sem_INSN_LDR14UH },
+    { FR30BF_INSN_LDR14UB, && case_sem_INSN_LDR14UB },
+    { FR30BF_INSN_LDR15, && case_sem_INSN_LDR15 },
+    { FR30BF_INSN_LDR15GR, && case_sem_INSN_LDR15GR },
+    { FR30BF_INSN_LDR15DR, && case_sem_INSN_LDR15DR },
+    { FR30BF_INSN_LDR15PS, && case_sem_INSN_LDR15PS },
+    { FR30BF_INSN_ST, && case_sem_INSN_ST },
+    { FR30BF_INSN_STH, && case_sem_INSN_STH },
+    { FR30BF_INSN_STB, && case_sem_INSN_STB },
+    { FR30BF_INSN_STR13, && case_sem_INSN_STR13 },
+    { FR30BF_INSN_STR13H, && case_sem_INSN_STR13H },
+    { FR30BF_INSN_STR13B, && case_sem_INSN_STR13B },
+    { FR30BF_INSN_STR14, && case_sem_INSN_STR14 },
+    { FR30BF_INSN_STR14H, && case_sem_INSN_STR14H },
+    { FR30BF_INSN_STR14B, && case_sem_INSN_STR14B },
+    { FR30BF_INSN_STR15, && case_sem_INSN_STR15 },
+    { FR30BF_INSN_STR15GR, && case_sem_INSN_STR15GR },
+    { FR30BF_INSN_STR15DR, && case_sem_INSN_STR15DR },
+    { FR30BF_INSN_STR15PS, && case_sem_INSN_STR15PS },
+    { FR30BF_INSN_MOV, && case_sem_INSN_MOV },
+    { FR30BF_INSN_MOVDR, && case_sem_INSN_MOVDR },
+    { FR30BF_INSN_MOVPS, && case_sem_INSN_MOVPS },
+    { FR30BF_INSN_MOV2DR, && case_sem_INSN_MOV2DR },
+    { FR30BF_INSN_MOV2PS, && case_sem_INSN_MOV2PS },
+    { FR30BF_INSN_JMP, && case_sem_INSN_JMP },
+    { FR30BF_INSN_JMPD, && case_sem_INSN_JMPD },
+    { FR30BF_INSN_CALLR, && case_sem_INSN_CALLR },
+    { FR30BF_INSN_CALLRD, && case_sem_INSN_CALLRD },
+    { FR30BF_INSN_CALL, && case_sem_INSN_CALL },
+    { FR30BF_INSN_CALLD, && case_sem_INSN_CALLD },
+    { FR30BF_INSN_RET, && case_sem_INSN_RET },
+    { FR30BF_INSN_RET_D, && case_sem_INSN_RET_D },
+    { FR30BF_INSN_INT, && case_sem_INSN_INT },
+    { FR30BF_INSN_INTE, && case_sem_INSN_INTE },
+    { FR30BF_INSN_RETI, && case_sem_INSN_RETI },
+    { FR30BF_INSN_BRAD, && case_sem_INSN_BRAD },
+    { FR30BF_INSN_BRA, && case_sem_INSN_BRA },
+    { FR30BF_INSN_BNOD, && case_sem_INSN_BNOD },
+    { FR30BF_INSN_BNO, && case_sem_INSN_BNO },
+    { FR30BF_INSN_BEQD, && case_sem_INSN_BEQD },
+    { FR30BF_INSN_BEQ, && case_sem_INSN_BEQ },
+    { FR30BF_INSN_BNED, && case_sem_INSN_BNED },
+    { FR30BF_INSN_BNE, && case_sem_INSN_BNE },
+    { FR30BF_INSN_BCD, && case_sem_INSN_BCD },
+    { FR30BF_INSN_BC, && case_sem_INSN_BC },
+    { FR30BF_INSN_BNCD, && case_sem_INSN_BNCD },
+    { FR30BF_INSN_BNC, && case_sem_INSN_BNC },
+    { FR30BF_INSN_BND, && case_sem_INSN_BND },
+    { FR30BF_INSN_BN, && case_sem_INSN_BN },
+    { FR30BF_INSN_BPD, && case_sem_INSN_BPD },
+    { FR30BF_INSN_BP, && case_sem_INSN_BP },
+    { FR30BF_INSN_BVD, && case_sem_INSN_BVD },
+    { FR30BF_INSN_BV, && case_sem_INSN_BV },
+    { FR30BF_INSN_BNVD, && case_sem_INSN_BNVD },
+    { FR30BF_INSN_BNV, && case_sem_INSN_BNV },
+    { FR30BF_INSN_BLTD, && case_sem_INSN_BLTD },
+    { FR30BF_INSN_BLT, && case_sem_INSN_BLT },
+    { FR30BF_INSN_BGED, && case_sem_INSN_BGED },
+    { FR30BF_INSN_BGE, && case_sem_INSN_BGE },
+    { FR30BF_INSN_BLED, && case_sem_INSN_BLED },
+    { FR30BF_INSN_BLE, && case_sem_INSN_BLE },
+    { FR30BF_INSN_BGTD, && case_sem_INSN_BGTD },
+    { FR30BF_INSN_BGT, && case_sem_INSN_BGT },
+    { FR30BF_INSN_BLSD, && case_sem_INSN_BLSD },
+    { FR30BF_INSN_BLS, && case_sem_INSN_BLS },
+    { FR30BF_INSN_BHID, && case_sem_INSN_BHID },
+    { FR30BF_INSN_BHI, && case_sem_INSN_BHI },
+    { FR30BF_INSN_DMOVR13, && case_sem_INSN_DMOVR13 },
+    { FR30BF_INSN_DMOVR13H, && case_sem_INSN_DMOVR13H },
+    { FR30BF_INSN_DMOVR13B, && case_sem_INSN_DMOVR13B },
+    { FR30BF_INSN_DMOVR13PI, && case_sem_INSN_DMOVR13PI },
+    { FR30BF_INSN_DMOVR13PIH, && case_sem_INSN_DMOVR13PIH },
+    { FR30BF_INSN_DMOVR13PIB, && case_sem_INSN_DMOVR13PIB },
+    { FR30BF_INSN_DMOVR15PI, && case_sem_INSN_DMOVR15PI },
+    { FR30BF_INSN_DMOV2R13, && case_sem_INSN_DMOV2R13 },
+    { FR30BF_INSN_DMOV2R13H, && case_sem_INSN_DMOV2R13H },
+    { FR30BF_INSN_DMOV2R13B, && case_sem_INSN_DMOV2R13B },
+    { FR30BF_INSN_DMOV2R13PI, && case_sem_INSN_DMOV2R13PI },
+    { FR30BF_INSN_DMOV2R13PIH, && case_sem_INSN_DMOV2R13PIH },
+    { FR30BF_INSN_DMOV2R13PIB, && case_sem_INSN_DMOV2R13PIB },
+    { FR30BF_INSN_DMOV2R15PD, && case_sem_INSN_DMOV2R15PD },
+    { FR30BF_INSN_LDRES, && case_sem_INSN_LDRES },
+    { FR30BF_INSN_STRES, && case_sem_INSN_STRES },
+    { FR30BF_INSN_COPOP, && case_sem_INSN_COPOP },
+    { FR30BF_INSN_COPLD, && case_sem_INSN_COPLD },
+    { FR30BF_INSN_COPST, && case_sem_INSN_COPST },
+    { FR30BF_INSN_COPSV, && case_sem_INSN_COPSV },
+    { FR30BF_INSN_NOP, && case_sem_INSN_NOP },
+    { FR30BF_INSN_ANDCCR, && case_sem_INSN_ANDCCR },
+    { FR30BF_INSN_ORCCR, && case_sem_INSN_ORCCR },
+    { FR30BF_INSN_STILM, && case_sem_INSN_STILM },
+    { FR30BF_INSN_ADDSP, && case_sem_INSN_ADDSP },
+    { FR30BF_INSN_EXTSB, && case_sem_INSN_EXTSB },
+    { FR30BF_INSN_EXTUB, && case_sem_INSN_EXTUB },
+    { FR30BF_INSN_EXTSH, && case_sem_INSN_EXTSH },
+    { FR30BF_INSN_EXTUH, && case_sem_INSN_EXTUH },
+    { FR30BF_INSN_LDM0, && case_sem_INSN_LDM0 },
+    { FR30BF_INSN_LDM1, && case_sem_INSN_LDM1 },
+    { FR30BF_INSN_STM0, && case_sem_INSN_STM0 },
+    { FR30BF_INSN_STM1, && case_sem_INSN_STM1 },
+    { FR30BF_INSN_ENTER, && case_sem_INSN_ENTER },
+    { FR30BF_INSN_LEAVE, && case_sem_INSN_LEAVE },
+    { FR30BF_INSN_XCHB, && case_sem_INSN_XCHB },
+    { 0, 0 }
+  };
+  int i;
+
+  for (i = 0; labels[i].label != 0; ++i)
+#if FAST_P
+    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+   off frills like tracing and profiling.  */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+   that can cause it to be optimized out.  Another way would be to emit
+   special handlers into the instruction "stream".  */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop.  */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+    {
+
+  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    fr30bf_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    fr30bf_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+#ifdef DEFINE_SWITCH
+    vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    vpc = fr30bf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = fr30bf_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = fr30bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD) : /* add $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDI) : /* add $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD2) : /* add2 $m4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDC) : /* addc $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDN) : /* addn $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addn.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDNI) : /* addn $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addni.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDN2) : /* addn2 $m4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addn2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUB) : /* sub $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBC) : /* subc $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBN) : /* subn $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addn.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMP) : /* cmp $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI) : /* cmp $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMP2) : /* cmp2 $m4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND) : /* and $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_and.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR) : /* or $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_and.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EOR) : /* eor $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_and.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDM) : /* and $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andm.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDH) : /* andh $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDB) : /* andb $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ORM) : /* or $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andm.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ORH) : /* orh $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ORB) : /* orb $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EORM) : /* eor $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andm.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EORH) : /* eorh $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EORB) : /* eorb $Rj,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BANDL) : /* bandl $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ANDQI (ORQI (FLD (f_u4), 240), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BORL) : /* borl $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEORL) : /* beorl $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = XORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BANDH) : /* bandh $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ANDQI (ORQI (SLLQI (FLD (f_u4), 4), 15), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BORH) : /* borh $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEORH) : /* beorh $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bandl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = XORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BTSTL) : /* btstl $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_btstl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = 0;
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BTSTH) : /* btsth $u4,@$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_btstl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MUL) : /* mul $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mul.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp;
+  tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri)));
+  {
+    SI opval = TRUNCDISI (tmp_tmp);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQDI (tmp_tmp, MAKEDI (0, 0));
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = ORIF (GTDI (tmp_tmp, MAKEDI (0, 2147483647)), LTDI (tmp_tmp, NEGDI (MAKEDI (0, 0x80000000))));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULU) : /* mulu $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulu.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp;
+  tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri)));
+  {
+    SI opval = TRUNCDISI (tmp_tmp);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = NESI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULH) : /* mulh $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri)));
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULUH) : /* muluh $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535));
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV0S) : /* div0s $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div0s.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_d0bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
+  }
+  {
+    BI opval = XORBI (CPU (h_d0bit), LTSI (* FLD (i_Ri), 0));
+    CPU (h_d1bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
+  }
+if (NEBI (CPU (h_d0bit), 0)) {
+  {
+    SI opval = 0xffffffff;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} else {
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV0U) : /* div0u $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div0u.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = 0;
+    CPU (h_d0bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
+  }
+  {
+    BI opval = 0;
+    CPU (h_d1bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV1) : /* div1 $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  {
+    SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1);
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+if (LTSI (GET_H_DR (((UINT) 5)), 0)) {
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 4)), 1);
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+}
+  {
+    SI opval = SLLSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+if (EQBI (CPU (h_d1bit), 1)) {
+do {
+  tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+}
+if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) {
+do {
+  {
+    SI opval = tmp_tmp;
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    SI opval = ORSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+} while (0);
+}
+  {
+    BI opval = EQSI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV2) : /* div2 $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+if (EQBI (CPU (h_d1bit), 1)) {
+do {
+  tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+}
+if (EQSI (tmp_tmp, 0)) {
+do {
+  {
+    BI opval = 1;
+    CPU (h_zbit) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_zbit) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV3) : /* div3 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (CPU (h_zbit), 1)) {
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV4S) : /* div4s */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div4s.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (CPU (h_d1bit), 1)) {
+  {
+    SI opval = NEGSI (GET_H_DR (((UINT) 5)));
+    SET_H_DR (((UINT) 5), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSL) : /* lsl $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSLI) : /* lsl $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSL2) : /* lsl2 $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSR) : /* lsr $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSRI) : /* lsr $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LSR2) : /* lsr2 $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ASR) : /* asr $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ASRI) : /* asr $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ASR2) : /* asr2 $u4,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lsli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI8) : /* ldi:8 $i8,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_i8);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI20) : /* ldi:20 $i20,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi20.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_i20);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI32) : /* ldi:32 $i32,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi32.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+  {
+    SI opval = FLD (f_i32);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD) : /* ld @$Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUH) : /* lduh @$Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lduh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUB) : /* ldub @$Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldub.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR13) : /* ld @($R13,$Rj),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr13.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR13UH) : /* lduh @($R13,$Rj),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr13uh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR13UB) : /* ldub @($R13,$Rj),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr13ub.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR14) : /* ld @($R14,$disp10),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr14.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR14UH) : /* lduh @($R14,$disp9),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr14uh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR14UB) : /* ldub @($R14,$disp8),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr14ub.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR15) : /* ld @($R15,$udisp6),$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr15.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_udisp6), CPU (h_gr[((UINT) 15)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR15GR) : /* ld @$R15+,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr15gr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+if (NESI (FLD (f_Ri), 15)) {
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR15DR) : /* ld @$R15+,$Rs2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr15dr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SET_H_DR (FLD (f_Rs2), opval);
+    TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDR15PS) : /* ld @$R15+,$ps */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldr15ps.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    SET_H_PS (opval);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST) : /* st $Ri,@$Rj */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH) : /* sth $Ri,@$Rj */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sth.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB) : /* stb $Ri,@$Rj */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR13) : /* st $Ri,@($R13,$Rj) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str13.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR13H) : /* sth $Ri,@($R13,$Rj) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str13h.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR13B) : /* stb $Ri,@($R13,$Rj) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str13b.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR14) : /* st $Ri,@($R14,$disp10) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str14.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR14H) : /* sth $Ri,@($R14,$disp9) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str14h.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR14B) : /* stb $Ri,@($R14,$disp8) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str14b.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR15) : /* st $Ri,@($R15,$udisp6) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str15.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_udisp6)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR15GR) : /* st $Ri,@-$R15 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str15gr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = * FLD (i_Ri);
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR15DR) : /* st $Rs2,@-$R15 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str15dr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = GET_H_DR (FLD (f_Rs2));
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STR15PS) : /* st $ps,@-$R15 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_str15ps.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GET_H_PS ();
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOV) : /* mov $Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mov.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Rj);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVDR) : /* mov $Rs1,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movdr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_DR (FLD (f_Rs1));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVPS) : /* mov $ps,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movps.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_PS ();
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOV2DR) : /* mov $Ri,$Rs1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mov2dr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SET_H_DR (FLD (f_Rs1), opval);
+    TRACE_RESULT (current_cpu, abuf, "Rs1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOV2PS) : /* mov $Ri,$ps */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mov2ps.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_Ri);
+    SET_H_PS (opval);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JMP) : /* jmp @$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JMPD) : /* jmp:d @$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLR) : /* call @$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (pc, 2);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLRD) : /* call:d @$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALL) : /* call $label12 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (pc, 2);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_label12);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLD) : /* call:d $label12 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_label12);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RET) : /* ret */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = GET_H_DR (((UINT) 1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RET_D) : /* ret:d */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = GET_H_DR (((UINT) 1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_INT) : /* int $u8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_int.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+  {
+    SI opval = fr30_int (current_cpu, pc, FLD (f_u8));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_INTE) : /* inte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_inte.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+  {
+    SI opval = fr30_inte (current_cpu, pc);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RETI) : /* reti */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_reti.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (GET_H_SBIT (), 0)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
+    SET_H_DR (((UINT) 2), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
+    SET_H_PS (opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
+    SET_H_DR (((UINT) 2), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
+    SET_H_DR (((UINT) 3), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
+    SET_H_PS (opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
+    SET_H_DR (((UINT) 3), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRAD) : /* bra:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRA) : /* bra $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNOD) : /* bno:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bnod.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do { } while (0); /*nop*/
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNO) : /* bno $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_bnod.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQD) : /* beq:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_zbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQ) : /* beq $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_zbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNED) : /* bne:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNE) : /* bne $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCD) : /* bc:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_cbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BC) : /* bc $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNCD) : /* bnc:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_cbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNC) : /* bnc $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BND) : /* bn:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_nbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BN) : /* bn $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_nbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BPD) : /* bp:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BP) : /* bp $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BVD) : /* bv:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_vbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BV) : /* bv $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_vbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNVD) : /* bnv:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_vbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNV) : /* bnv $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_vbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLTD) : /* blt:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLT) : /* blt $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGED) : /* bge:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGE) : /* bge $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLED) : /* ble:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLE) : /* ble $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGTD) : /* bgt:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGT) : /* bgt $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLSD) : /* bls:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLS) : /* bls $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BHID) : /* bhi:d $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BHI) : /* bhi $label9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13) : /* dmov $R13,@$dir10 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13H) : /* dmovh $R13,@$dir9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13h.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13B) : /* dmovb $R13,@$dir8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13b.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13PI) : /* dmov @$R13+,@$dir10 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13pi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13PIH) : /* dmovh @$R13+,@$dir9 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13pih.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR13PIB) : /* dmovb @$R13+,@$dir8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr13pib.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOVR15PI) : /* dmov @$R15+,@$dir10 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmovr15pi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13) : /* dmov @$dir10,$R13 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13H) : /* dmovh @$dir9,$R13 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13h.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13B) : /* dmovb @$dir8,$R13 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13b.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13PI) : /* dmov @$dir10,@$R13+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13pi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13PIH) : /* dmovh @$dir9,@$R13+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13pih.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
+    SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R13PIB) : /* dmovb @$dir8,@$R13+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r13pib.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
+    SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DMOV2R15PD) : /* dmov @$dir10,@-$R15 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_dmov2r15pd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDRES) : /* ldres @$Ri+,$u4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldres.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), 4);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STRES) : /* stres $u4,@$Ri+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldres.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), 4);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_COPOP) : /* copop $u4c,$ccc,$CRj,$CRi */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_copop.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_COPLD) : /* copld $u4c,$ccc,$Rjc,$CRi */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_copld.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_COPST) : /* copst $u4c,$ccc,$CRj,$Ric */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_copst.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_COPSV) : /* copsv $u4c,$ccc,$CRj,$Ric */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_copst.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_nop.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDCCR) : /* andccr $u8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andccr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ANDQI (GET_H_CCR (), FLD (f_u8));
+    SET_H_CCR (opval);
+    TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ORCCR) : /* orccr $u8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_andccr.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ORQI (GET_H_CCR (), FLD (f_u8));
+    SET_H_CCR (opval);
+    TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STILM) : /* stilm $u8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stilm.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ANDSI (FLD (f_u8), 31);
+    SET_H_ILM (opval);
+    TRACE_RESULT (current_cpu, abuf, "ilm", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDSP) : /* addsp $s10 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addsp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_s10));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EXTSB) : /* extsb $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_extsb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (ANDQI (* FLD (i_Ri), 255));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EXTUB) : /* extub $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_extub.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (ANDQI (* FLD (i_Ri), 255));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EXTSH) : /* extsh $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_extsh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (ANDHI (* FLD (i_Ri), 65535));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EXTUH) : /* extuh $Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_extuh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (ANDHI (* FLD (i_Ri), 65535));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDM0) : /* ldm0 ($reglist_low_ld) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldm0.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_low_ld), 1)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 0)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 2)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 1)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 4)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 2)]) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 8)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 3)]) = opval;
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr-3", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 16)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 4)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-4", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 32)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 5)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-5", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 64)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 6)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-6", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 128)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 7)]) = opval;
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "gr-7", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDM1) : /* ldm1 ($reglist_hi_ld) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldm1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_hi_ld), 1)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 8)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-8", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 2)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 9)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-9", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 4)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 10)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr-10", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 8)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 11)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-11", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 16)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 12)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-12", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 32)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 64)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 128)) {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STM0) : /* stm0 ($reglist_low_st) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stm0.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_low_st), 1)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 7)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 2)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 6)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 4)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 5)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 8)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 4)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 16)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 3)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 32)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 2)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 64)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 1)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 128)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 0)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STM1) : /* stm1 ($reglist_hi_st) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stm1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_hi_st), 1)) {
+do {
+  SI tmp_save_r15;
+  tmp_save_r15 = CPU (h_gr[((UINT) 15)]);
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_save_r15;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 2)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 14)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 4)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 8)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 12)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 16)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 11)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 32)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 10)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 64)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 9)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 128)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 8)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ENTER) : /* enter $u10 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_enter.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+  {
+    SI opval = CPU (h_gr[((UINT) 14)]);
+    SETMEMSI (current_cpu, pc, tmp_tmp, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), FLD (f_u10));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LEAVE) : /* leave */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_leave.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, SUBSI (CPU (h_gr[((UINT) 15)]), 4));
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XCHB) : /* xchb @$Rj,$Ri */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_xchb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = * FLD (i_Ri);
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+  {
+    UQI opval = tmp_tmp;
+    SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+
+    }
+  ENDSWITCH (sem) /* End of semantic switch.  */
+
+  /* At this point `vpc' contains the next insn to execute.  */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
diff --git a/sim/fr30/sem.c b/sim/fr30/sem.c
new file mode 100644
index 00000000000..8224c3350d9
--- /dev/null
+++ b/sim/fr30/sem.c
@@ -0,0 +1,5504 @@
+/* Simulator instruction semantics for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU fr30bf
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+/* x-invalid: --invalid-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    fr30bf_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    fr30bf_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+#ifdef DEFINE_SWITCH
+    vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+    vpc = fr30bf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FR30BF
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = fr30bf_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = fr30bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* add: add $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* addi: add $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* add2: add2 $m4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,add2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* addc: addc $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+  {
+    BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* addn: addn $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addni: addn $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addni) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addni.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addn2: addn2 $m4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addn2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sub: sub $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* subc: subc $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* subn: subn $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,subn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addn.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmp: cmp $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpi: cmp $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_u4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* cmp2: cmp2 $m4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,cmp2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmp2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp1;
+  {
+    BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+  {
+    BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_m4), 0);
+    CPU (h_cbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4));
+do {
+  {
+    BI opval = EQSI (tmp_tmp1, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp1, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* and: and $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* or: or $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* eor: eor $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,eor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+do {
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* andm: and $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,andm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* andh: andh $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,andh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* andb: andb $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,andb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* orm: or $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,orm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* orh: orh $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,orh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* orb: orb $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,orb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* eorm: eor $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,eorm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andm.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQSI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTSI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* eorh: eorh $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,eorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  HI tmp_tmp;
+  tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQHI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTHI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    HI opval = tmp_tmp;
+    SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* eorb: eorb $Rj,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,eorb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
+do {
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+  {
+    QI opval = tmp_tmp;
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* bandl: bandl $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bandl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ANDQI (ORQI (FLD (f_u4), 240), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* borl: borl $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,borl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* beorl: beorl $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,beorl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = XORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* bandh: bandh $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bandh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ANDQI (ORQI (SLLQI (FLD (f_u4), 4), 15), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* borh: borh $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,borh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = ORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* beorh: beorh $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,beorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bandl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = XORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+    SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* btstl: btstl $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,btstl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_btstl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = 0;
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* btsth: btsth $u4,@$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,btsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_btstl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  QI tmp_tmp;
+  tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
+  {
+    BI opval = EQQI (tmp_tmp, 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = LTQI (tmp_tmp, 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* mul: mul $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mul.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp;
+  tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri)));
+  {
+    SI opval = TRUNCDISI (tmp_tmp);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQDI (tmp_tmp, MAKEDI (0, 0));
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = ORIF (GTDI (tmp_tmp, MAKEDI (0, 2147483647)), LTDI (tmp_tmp, NEGDI (MAKEDI (0, 0x80000000))));
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* mulu: mulu $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp;
+  tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri)));
+  {
+    SI opval = TRUNCDISI (tmp_tmp);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    BI opval = NESI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_vbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* mulh: mulh $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mulh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri)));
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* muluh: muluh $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,muluh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535));
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* div0s: div0s $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div0s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div0s.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
+    CPU (h_d0bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
+  }
+  {
+    BI opval = XORBI (CPU (h_d0bit), LTSI (* FLD (i_Ri), 0));
+    CPU (h_d1bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
+  }
+if (NEBI (CPU (h_d0bit), 0)) {
+  {
+    SI opval = 0xffffffff;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} else {
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* div0u: div0u $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div0u) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div0u.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = 0;
+    CPU (h_d0bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
+  }
+  {
+    BI opval = 0;
+    CPU (h_d1bit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* div1: div1 $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  {
+    SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1);
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+if (LTSI (GET_H_DR (((UINT) 5)), 0)) {
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 4)), 1);
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+}
+  {
+    SI opval = SLLSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+if (EQBI (CPU (h_d1bit), 1)) {
+do {
+  tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+}
+if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) {
+do {
+  {
+    SI opval = tmp_tmp;
+    SET_H_DR (((UINT) 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+  {
+    SI opval = ORSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+} while (0);
+}
+  {
+    BI opval = EQSI (GET_H_DR (((UINT) 4)), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* div2: div2 $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+if (EQBI (CPU (h_d1bit), 1)) {
+do {
+  tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
+  {
+    BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+} while (0);
+}
+if (EQSI (tmp_tmp, 0)) {
+do {
+  {
+    BI opval = 1;
+    CPU (h_zbit) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    SET_H_DR (((UINT) 4), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_zbit) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* div3: div3 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (CPU (h_zbit), 1)) {
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 5)), 1);
+    SET_H_DR (((UINT) 5), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* div4s: div4s */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,div4s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_div4s.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (CPU (h_d1bit), 1)) {
+  {
+    SI opval = NEGSI (GET_H_DR (((UINT) 5)));
+    SET_H_DR (((UINT) 5), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsl: lsl $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsli: lsl $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsl2: lsl2 $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsl2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsr: lsr $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsri: lsr $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lsr2: lsr2 $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lsr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* asr: asr $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ANDSI (* FLD (i_Rj), 31);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* asri: asr $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,asri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = FLD (f_u4);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* asr2: asr2 $u4,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,asr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lsli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_shift;
+  tmp_shift = ADDSI (FLD (f_u4), 16);
+if (NESI (tmp_shift, 0)) {
+do {
+  {
+    BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+  {
+    SI opval = SRASI (* FLD (i_Ri), tmp_shift);
+    * FLD (i_Ri) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+} while (0);
+} else {
+  {
+    BI opval = 0;
+    CPU (h_cbit) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+  }
+}
+  {
+    BI opval = LTSI (* FLD (i_Ri), 0);
+    CPU (h_nbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+  }
+  {
+    BI opval = EQSI (* FLD (i_Ri), 0);
+    CPU (h_zbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldi8: ldi:8 $i8,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_i8);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldi20: ldi:20 $i20,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldi20) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi20.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_i20);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldi32: ldi:32 $i32,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldi32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldi32.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+  {
+    SI opval = FLD (f_i32);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld: ld @$Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lduh: lduh @$Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lduh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldub: ldub @$Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldub.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr13: ld @($R13,$Rj),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr13uh: lduh @($R13,$Rj),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr13uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13uh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr13ub: ldub @($R13,$Rj),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr13ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr13ub.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr14: ld @($R14,$disp10),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr14) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr14uh: lduh @($R14,$disp9),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr14uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14uh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr14ub: ldub @($R14,$disp8),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr14ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr14ub.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr15: ld @($R15,$udisp6),$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr15) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_udisp6), CPU (h_gr[((UINT) 15)])));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr15gr: ld @$R15+,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15gr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+if (NESI (FLD (f_Ri), 15)) {
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldr15dr: ld @$R15+,$Rs2 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15dr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SET_H_DR (FLD (f_Rs2), opval);
+    TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldr15ps: ld @$R15+,$ps */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldr15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldr15ps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    SET_H_PS (opval);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* st: st $Ri,@$Rj */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sth: sth $Ri,@$Rj */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_sth.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stb: stb $Ri,@$Rj */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str13: st $Ri,@($R13,$Rj) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str13h: sth $Ri,@($R13,$Rj) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13h.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str13b: stb $Ri,@($R13,$Rj) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str13b.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str14: st $Ri,@($R14,$disp10) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str14) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str14h: sth $Ri,@($R14,$disp9) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str14h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14h.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_Ri);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str14b: stb $Ri,@($R14,$disp8) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str14b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str14b.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_Ri);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str15: st $Ri,@($R15,$udisp6) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str15) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_udisp6)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* str15gr: st $Ri,@-$R15 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15gr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = * FLD (i_Ri);
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* str15dr: st $Rs2,@-$R15 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15dr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = GET_H_DR (FLD (f_Rs2));
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* str15ps: st $ps,@-$R15 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,str15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_str15ps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GET_H_PS ();
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* mov: mov $Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Rj);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movdr: mov $Rs1,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,movdr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movdr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_DR (FLD (f_Rs1));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movps: mov $ps,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,movps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_PS ();
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mov2dr: mov $Ri,$Rs1 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mov2dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov2dr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_Ri);
+    SET_H_DR (FLD (f_Rs1), opval);
+    TRACE_RESULT (current_cpu, abuf, "Rs1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mov2ps: mov $Ri,$ps */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,mov2ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mov2ps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_Ri);
+    SET_H_PS (opval);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* jmp: jmp @$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* jmpd: jmp:d @$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,jmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* callr: call @$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,callr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (pc, 2);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* callrd: call:d @$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,callrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = * FLD (i_Ri);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* call: call $label12 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (pc, 2);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_label12);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* calld: call:d $label12 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_call.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    SET_H_DR (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_label12);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* ret: ret */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = GET_H_DR (((UINT) 1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* ret:d: ret:d */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ret_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = GET_H_DR (((UINT) 1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* int: int $u8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,int) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_int.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+  {
+    SI opval = fr30_int (current_cpu, pc, FLD (f_u8));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* inte: inte */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,inte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_inte.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+  {
+    SI opval = fr30_inte (current_cpu, pc);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* reti: reti */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,reti) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_reti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (EQBI (GET_H_SBIT (), 0)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
+    SET_H_DR (((UINT) 2), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
+    SET_H_PS (opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
+    SET_H_DR (((UINT) 2), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
+  }
+} while (0);
+} else {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
+    SET_H_DR (((UINT) 3), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
+    SET_H_PS (opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
+    SET_H_DR (((UINT) 3), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* brad: bra:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bra: bra $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_brad.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bnod: bno:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bnod) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bnod.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+do { } while (0); /*nop*/
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* bno: bno $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_bnod.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* beqd: beq:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,beqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_zbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* beq: beq $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_zbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bned: bne:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bned) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bne: bne $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bcd: bc:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bcd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_cbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bc: bc $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bncd: bnc:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bncd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_cbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bnc: bnc $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bnd: bn:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bnd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_nbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bn: bn $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_nbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bpd: bp:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bp: bp $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bvd: bv:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_vbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bv: bv $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_vbit)) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bnvd: bnv:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bnvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (CPU (h_vbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bnv: bnv $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_vbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bltd: blt:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bltd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* blt: blt $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,blt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bged: bge:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bged) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bge: bge $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bled: ble:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bled) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* ble: ble $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bgtd: bgt:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bgt: bgt $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bled.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* blsd: bls:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,blsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bls: bls $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bhid: bhi:d $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bhid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bhi: bhi $label9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,bhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
+  {
+    USI opval = FLD (i_label9);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13: dmov $R13,@$dir10 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13h: dmovh $R13,@$dir9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13h.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13b: dmovb $R13,@$dir8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13b.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13pi: dmov @$R13+,@$dir10 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13pih: dmovh @$R13+,@$dir9 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pih.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr13pib: dmovb @$R13+,@$dir8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr13pib.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
+    SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmovr15pi: dmov @$R15+,@$dir10 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmovr15pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmovr15pi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13: dmov @$dir10,$R13 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13h: dmovh @$dir9,$R13 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13h.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13b: dmovb @$dir8,$R13 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13b.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13pi: dmov @$dir10,@$R13+ */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13pih: dmovh @$dir9,@$R13+ */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pih.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
+    SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r13pib: dmovb @$dir8,@$R13+ */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r13pib.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
+    SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
+    CPU (h_gr[((UINT) 13)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dmov2r15pd: dmov @$dir10,@-$R15 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,dmov2r15pd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_dmov2r15pd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldres: ldres @$Ri+,$u4 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldres) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldres.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), 4);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stres: stres $u4,@$Ri+ */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,stres) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldres.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_Ri), 4);
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* copop: copop $u4c,$ccc,$CRj,$CRi */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,copop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copop.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* copld: copld $u4c,$ccc,$Rjc,$CRi */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,copld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copld.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* copst: copst $u4c,$ccc,$CRj,$Ric */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,copst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copst.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* copsv: copsv $u4c,$ccc,$CRj,$Ric */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,copsv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_copst.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* nop: nop */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_nop.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* andccr: andccr $u8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,andccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andccr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ANDQI (GET_H_CCR (), FLD (f_u8));
+    SET_H_CCR (opval);
+    TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* orccr: orccr $u8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,orccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_andccr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ORQI (GET_H_CCR (), FLD (f_u8));
+    SET_H_CCR (opval);
+    TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stilm: stilm $u8 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,stilm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stilm.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    UQI opval = ANDSI (FLD (f_u8), 31);
+    SET_H_ILM (opval);
+    TRACE_RESULT (current_cpu, abuf, "ilm", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addsp: addsp $s10 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,addsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_addsp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_s10));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* extsb: extsb $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,extsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extsb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (ANDQI (* FLD (i_Ri), 255));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* extub: extub $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,extub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extub.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (ANDQI (* FLD (i_Ri), 255));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* extsh: extsh $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,extsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extsh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (ANDHI (* FLD (i_Ri), 65535));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* extuh: extuh $Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,extuh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_extuh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (ANDHI (* FLD (i_Ri), 65535));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldm0: ldm0 ($reglist_low_ld) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldm0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_low_ld), 1)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 0)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 2)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 1)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 4)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 2)]) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 8)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 3)]) = opval;
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr-3", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 16)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 4)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-4", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 32)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 5)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-5", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 64)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 6)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-6", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_ld), 128)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 7)]) = opval;
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "gr-7", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldm1: ldm1 ($reglist_hi_ld) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,ldm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldm1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_hi_ld), 1)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 8)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-8", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 2)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 9)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-9", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 4)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 10)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr-10", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 8)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 11)]) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr-11", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 16)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 12)]) = opval;
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr-12", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 32)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 13)]) = opval;
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 64)) {
+do {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_ld), 128)) {
+  {
+    SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* stm0: stm0 ($reglist_low_st) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,stm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stm0.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_low_st), 1)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 7)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 2)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 6)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 4)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 5)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 8)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 4)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 16)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 3)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 32)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 2)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 64)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 1)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_low_st), 128)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 0)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* stm1: stm1 ($reglist_hi_st) */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,stm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stm1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (ANDSI (FLD (f_reglist_hi_st), 1)) {
+do {
+  SI tmp_save_r15;
+  tmp_save_r15 = CPU (h_gr[((UINT) 15)]);
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = tmp_save_r15;
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 2)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 14)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 4)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 13)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 8)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 12)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 16)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 11)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 32)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 10)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 64)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 9)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+if (ANDSI (FLD (f_reglist_hi_st), 128)) {
+do {
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((UINT) 8)]);
+    SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+}
+} while (0);
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* enter: enter $u10 */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,enter) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_enter.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
+  {
+    SI opval = CPU (h_gr[((UINT) 14)]);
+    SETMEMSI (current_cpu, pc, tmp_tmp, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_tmp;
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+  {
+    SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), FLD (f_u10));
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* leave: leave */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,leave) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_leave.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4);
+    CPU (h_gr[((UINT) 15)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, SUBSI (CPU (h_gr[((UINT) 15)]), 4));
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* xchb: xchb @$Rj,$Ri */
+
+SEM_PC
+SEM_FN_NAME (fr30bf,xchb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_xchb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_tmp;
+  tmp_tmp = * FLD (i_Ri);
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
+    * FLD (i_Ri) = opval;
+    TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
+  }
+  {
+    UQI opval = tmp_tmp;
+    SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
diff --git a/sim/fr30/sim-if.c b/sim/fr30/sim-if.c
new file mode 100644
index 00000000000..5df0f83f57a
--- /dev/null
+++ b/sim/fr30/sim-if.c
@@ -0,0 +1,208 @@
+/* Main simulator entry points specific to the FR30.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+
+static void free_state (SIM_DESC);
+static void print_fr30_misc_cpu (SIM_CPU *cpu, int verbose);
+
+/* Records simulator descriptor so utilities like fr30_dump_regs can be
+   called from gdb.  */
+SIM_DESC current_state;
+
+/* Cover function of sim_state_free to free the cpu buffers as well.  */
+
+static void
+free_state (SIM_DESC sd)
+{
+  if (STATE_MODULES (sd) != NULL)
+    sim_module_uninstall (sd);
+  sim_cpu_free_all (sd);
+  sim_state_free (sd);
+}
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+     SIM_OPEN_KIND kind;
+     host_callback *callback;
+     struct _bfd *abfd;
+     char **argv;
+{
+  char c;
+  int i;
+  SIM_DESC sd = sim_state_alloc (kind, callback);
+
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+  /* FIXME: watchpoints code shouldn't need this */
+  {
+    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+    STATE_WATCHPOINTS (sd)->pc = &(PC);
+    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  }
+#endif
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  if (extra_options != NULL)
+    sim_add_option_table (sd, extra_options);
+#endif
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0
+  /* Allocate a handler for the control registers and other devices
+     if no memory for that range has been allocated by the user.
+     All are allocated in one chunk to keep things from being
+     unnecessarily complicated.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, FR30_DEVICE_ADDR, 1) == 0)
+    sim_core_attach (sd, NULL,
+		     0 /*level*/,
+		     access_read_write,
+		     0 /*space ???*/,
+		     FR30_DEVICE_ADDR, FR30_DEVICE_LEN /*nr_bytes*/,
+		     0 /*modulo*/,
+		     &fr30_devices,
+		     NULL /*buffer*/);
+#endif
+
+  /* Allocate core managed memory if none specified by user.
+     Use address 4 here in case the user wanted address 0 unmapped.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+    sim_do_commandf (sd, "memory region 0,0x%lx", FR30_DEFAULT_MEM_SIZE);
+
+  /* check for/establish the reference program image */
+  if (sim_analyze_program (sd,
+			   (STATE_PROG_ARGV (sd) != NULL
+			    ? *STATE_PROG_ARGV (sd)
+			    : NULL),
+			   abfd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Establish any remaining configuration options.  */
+  if (sim_config (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Open a copy of the cpu descriptor table.  */
+  {
+    CGEN_CPU_DESC cd = fr30_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
+					   CGEN_ENDIAN_BIG);
+    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+      {
+	SIM_CPU *cpu = STATE_CPU (sd, i);
+	CPU_CPU_DESC (cpu) = cd;
+	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
+      }
+    fr30_cgen_init_dis (cd);
+  }
+
+  /* Initialize various cgen things not done by common framework.
+     Must be done after fr30_cgen_cpu_open.  */
+  cgen_init (sd);
+
+  /* Store in a global so things like sparc32_dump_regs can be invoked
+     from the gdb command line.  */
+  current_state = sd;
+
+  return sd;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  fr30_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+     SIM_DESC sd;
+     struct _bfd *abfd;
+     char **argv;
+     char **envp;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+  SIM_ADDR addr;
+
+  if (abfd != NULL)
+    addr = bfd_get_start_address (abfd);
+  else
+    addr = 0;
+  sim_pc_set (current_cpu, addr);
+
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+  return SIM_RC_OK;
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
diff --git a/sim/fr30/sim-main.h b/sim/fr30/sim-main.h
new file mode 100644
index 00000000000..8cbf085a697
--- /dev/null
+++ b/sim/fr30/sim-main.h
@@ -0,0 +1,70 @@
+/* Main header for the fr30.  */
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+/* sim-basics.h includes config.h but cgen-types.h must be included before
+   sim-basics.h and cgen-types.h needs config.h.  */
+#include "config.h"
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "fr30-desc.h"
+#include "fr30-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h.  */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu)     CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "fr30-sim.h"
+
+/* The _sim_cpu struct.  */
+
+struct _sim_cpu {
+  /* sim/common cpu base.  */
+  sim_cpu_base base;
+
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+
+  /* CPU specific parts go here.
+     Note that in files that don't need to access these pieces WANT_CPU_FOO
+     won't be defined and thus these parts won't appear.  This is ok in the
+     sense that things work.  It is a source of bugs though.
+     One has to of course be careful to not take the size of this
+     struct and no structure members accessed in non-cpu specific files can
+     go after here.  Oh for a better language.  */
+#if defined (WANT_CPU_FR30BF)
+  FR30BF_CPU_DATA cpu_data;
+#endif
+};
+
+/* The sim_state struct.  */
+
+struct sim_state {
+  sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+  CGEN_STATE cgen_state;
+
+  sim_state_base base;
+};
+
+/* Misc.  */
+
+/* Catch address exceptions.  */
+extern SIM_CORE_SIGNAL_FN fr30_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+fr30_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+		  (TRANSFER), (ERROR))
+
+/* Default memory size.  */
+#define FR30_DEFAULT_MEM_SIZE 0x800000 /* 8M */
diff --git a/sim/fr30/tconfig.in b/sim/fr30/tconfig.in
new file mode 100644
index 00000000000..a67e2275de6
--- /dev/null
+++ b/sim/fr30/tconfig.in
@@ -0,0 +1,42 @@
+/* FR30 target configuration file.  -*- C -*- */
+
+/* Define this if the simulator can vary the size of memory.
+   See the xxx simulator for an example.
+   This enables the `-m size' option.
+   The memory size is stored in STATE_MEM_SIZE.  */
+/* Not used for FR30 since we use the memory module. TODO -- check this  */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c.  We properly handle LMA. -- TODO: check this */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support.  FIXME: revisit.  */
+#define WITH_DEVICES 1
+
+/* FIXME: Revisit.  */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints.  */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified.  */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
+   duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+
+/* This is a global setting.  Different cpu families can't mix-n-match -scache
+   and -pbb.  However some cpu families may use -simple while others use
+   one of -scache/-pbb. ???? */
+#define WITH_SCACHE_PBB 1
diff --git a/sim/fr30/traps.c b/sim/fr30/traps.c
new file mode 100644
index 00000000000..599bca28891
--- /dev/null
+++ b/sim/fr30/traps.c
@@ -0,0 +1,217 @@
+/* fr30 exception, interrupt, and trap (EIT) support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#include "targ-vals.h"
+#include "cgen-engine.h"
+
+/* The semantic code invokes this for invalid (unrecognized) instructions.  */
+
+void
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_RSVD_INSN_ADDR);
+    }
+  else
+#endif
+    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+}
+
+/* Process an address exception.  */
+
+void
+fr30_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+		  unsigned int map, int nr_bytes, address_word addr,
+		  transfer_type transfer, sim_core_signals sig)
+{
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_ADDR_EXCP_ADDR);
+    }
+  else
+#endif
+    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+		     transfer, sig);
+}
+
+/* Read/write functions for system call interface.  */
+
+static int
+syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
+		  unsigned long taddr, char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
+		   unsigned long taddr, const char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* Subroutine of fr30_int to save the PS and PC and setup for INT and INTE.  */
+
+static void
+setup_int (SIM_CPU *current_cpu, PCADDR pc)
+{
+  USI ssp = a_fr30_h_dr_get (current_cpu, H_DR_SSP);
+  USI ps = a_fr30_h_ps_get (current_cpu);
+
+  ssp -= 4;
+  SETMEMSI (current_cpu, pc, ssp, ps);
+  ssp -= 4;
+  SETMEMSI (current_cpu, pc, ssp, pc + 2);
+  a_fr30_h_dr_set (current_cpu, H_DR_SSP, ssp);
+  a_fr30_h_sbit_set (current_cpu, 0);
+}
+
+/* Trap support.
+   The result is the pc address to continue at.
+   Preprocessing like saving the various registers has already been done.  */
+
+USI
+fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  host_callback *cb = STATE_CALLBACK (sd);
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* Check for breakpoints "owned" by the simulator first, regardless
+     of --environment.  */
+  if (num == TRAP_BREAKPOINT)
+    {
+      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+	 it doesn't return.  Otherwise it returns and let's us try.  */
+      sim_handle_breakpoint (sd, current_cpu, pc);
+      /* Fall through.  */
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      /* The new pc is the trap vector entry.
+	 We assume there's a branch there to some handler.  */
+      USI new_pc;
+      setup_int (current_cpu, pc);
+      a_fr30_h_ibit_set (current_cpu, 0);
+      new_pc = GETMEMSI (current_cpu, pc,
+			 a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+			 + 1024 - ((num + 1) * 4));
+      return new_pc;
+    }
+
+  switch (num)
+    {
+    case TRAP_SYSCALL :
+      {
+	/* TODO: find out what the ABI for this is */
+	CB_SYSCALL s;
+
+	CB_SYSCALL_INIT (&s);
+	s.func = a_fr30_h_gr_get (current_cpu, 0);
+	s.arg1 = a_fr30_h_gr_get (current_cpu, 4);
+	s.arg2 = a_fr30_h_gr_get (current_cpu, 5);
+	s.arg3 = a_fr30_h_gr_get (current_cpu, 6);
+
+	if (s.func == TARGET_SYS_exit)
+	  {
+	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+	  }
+
+	s.p1 = (PTR) sd;
+	s.p2 = (PTR) current_cpu;
+	s.read_mem = syscall_read_mem;
+	s.write_mem = syscall_write_mem;
+	cb_syscall (cb, &s);
+	a_fr30_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
+	a_fr30_h_gr_set (current_cpu, 4, s.result);
+	a_fr30_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
+	break;
+      }
+
+    case TRAP_BREAKPOINT:
+      sim_engine_halt (sd, current_cpu, NULL, pc,
+		       sim_stopped, SIM_SIGTRAP);
+      break;
+
+    default :
+      {
+	USI new_pc;
+	setup_int (current_cpu, pc);
+	a_fr30_h_ibit_set (current_cpu, 0);
+	new_pc = GETMEMSI (current_cpu, pc,
+			   a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+			   + 1024 - ((num + 1) * 4));
+	return new_pc;
+      }
+    }
+
+  /* Fake an "reti" insn.
+     Since we didn't push anything to stack, all we need to do is
+     update pc.  */
+  return pc + 2;
+}
+
+USI
+fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num)
+{
+  /* The new pc is the trap #9 vector entry.
+     We assume there's a branch there to some handler.  */
+  USI new_pc;
+  setup_int (current_cpu, pc);
+  a_fr30_h_ilm_set (current_cpu, 4);
+  new_pc = GETMEMSI (current_cpu, pc,
+		     a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+		     + 1024 - ((9 + 1) * 4));
+  return new_pc;
+}