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| author | Jason Molenda <jmolenda@apple.com> | 2000-01-18 00:55:13 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 2000-01-18 00:55:13 +0000 |
| commit | c5394b80aefdea6b2f589723a4b79bcbc1942629 (patch) | |
| tree | c53989048ae15966e62006aaee403659bde346bf /sim/mcore | |
| parent | 67a95c88f38aa938757c92389ba59bbc89e7fa79 (diff) | |
| download | binutils-gdb-c5394b80aefdea6b2f589723a4b79bcbc1942629.tar.gz | |
import gdb-2000-01-17 snapshot
Diffstat (limited to 'sim/mcore')
| -rw-r--r-- | sim/mcore/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mcore/interp.c | 15 |
2 files changed, 17 insertions, 3 deletions
diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog index 0dca47421c5..a43e7cbc756 100644 --- a/sim/mcore/ChangeLog +++ b/sim/mcore/ChangeLog @@ -1,3 +1,8 @@ +2000-01-13 Nick Clifton <nickc@cygnus.com> + + * interp.c (sim_resume): Do not rely upon host semantics of shift + operators to implement M*Core semantics. + Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 810bb069835..899b3718a5a 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -1181,7 +1181,9 @@ sim_resume (sd, step, siggnal) unsigned long dst, src; dst = cpu.gr[RD]; src = cpu.gr[RS]; - dst = dst >> src; + /* We must not rely solely upon the native shift operations, since they + may not match the M*Core's behaviour on boundary conditions. */ + dst = src > 31 ? 0 : dst >> src; cpu.gr[RD] = dst; } break; @@ -1256,11 +1258,18 @@ sim_resume (sd, step, siggnal) break; case 0x1A: /* asr */ - cpu.gr[RD] = (long)cpu.gr[RD] >> cpu.gr[RS]; + /* We must not rely solely upon the native shift operations, since they + may not match the M*Core's behaviour on boundary conditions. */ + if (cpu.gr[RS] > 30) + cpu.gr[RD] = ((long) cpu.gr[RD]) < 0 ? -1 : 0; + else + cpu.gr[RD] = (long) cpu.gr[RD] >> cpu.gr[RS]; break; case 0x1B: /* lsl */ - cpu.gr[RD] = cpu.gr[RD] << cpu.gr[RS]; + /* We must not rely solely upon the native shift operations, since they + may not match the M*Core's behaviour on boundary conditions. */ + cpu.gr[RD] = cpu.gr[RS] > 31 ? 0 : cpu.gr[RD] << cpu.gr[RS]; break; case 0x1C: /* addu */ |