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authorChris Demetriou <cgd@google.com>2002-03-01 07:34:57 +0000
committerChris Demetriou <cgd@google.com>2002-03-01 07:34:57 +0000
commitbb22bd7d9ec6a874d1b8797ed81a4763dee3b917 (patch)
treeaa1a618e1294e816ac9f04b1a77124ce0c6dc798 /sim
parent91a177cf814ef4cdaad1d1114491be360c2d0f88 (diff)
downloadbinutils-gdb-bb22bd7d9ec6a874d1b8797ed81a4763dee3b917.tar.gz
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DSRA32, DSRAV): Fix order of arguments in instruction-printing string. (LWU): Use '64' as the filter flag.
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog6
-rw-r--r--sim/mips/mips.igen6
2 files changed, 9 insertions, 3 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index e3ca0ec04ac..cb69ddb74c2 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,11 @@
2002-02-28 Chris Demetriou <cgd@broadcom.com>
+ * mips.igen (DSRA32, DSRAV): Fix order of arguments in
+ instruction-printing string.
+ (LWU): Use '64' as the filter flag.
+
+2002-02-28 Chris Demetriou <cgd@broadcom.com>
+
* mips.igen (SDXC1): Fix instruction-printing string.
2002-02-28 Chris Demetriou <cgd@broadcom.com>
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index eb511194591..02ae7607835 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1248,7 +1248,7 @@
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RT>, r<RD>, <SHIFT>"
+"dsra32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
@@ -1270,7 +1270,7 @@
}
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
-"dsrav r<RT>, r<RD>, r<RS>"
+"dsrav r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
@@ -1824,7 +1824,7 @@
}
-100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
+100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV: