diff options
59 files changed, 9783 insertions, 9712 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 1830ea2b113..e4ebf0e9e46 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,26 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (print_operands): Print spaces between + operands. + * testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after "," + in addresses. + * testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise. + * testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise. + * testsuite/gas/aarch64/ldst-reg-pair.d: Likewise. + * testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise. + * testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise. + * testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. + * testsuite/gas/aarch64/reloc-insn.d: Likewise. + * testsuite/gas/aarch64/sve.d: Likewise. + * testsuite/gas/aarch64/symbol.d: Likewise. + * testsuite/gas/aarch64/system.d: Likewise. + * testsuite/gas/aarch64/tls-desc.d: Likewise. + * testsuite/gas/aarch64/sve-invalid.l: Expect spaces after "," + in suggested alternatives. + * testsuite/gas/aarch64/verbose-error.l: Likewise. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * config/tc-aarch64.c (output_operand_error_record): Use "must be" rather than "should be" or "expected to be" in error messages. (parse_operands): Likewise. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 9963c61c8ae..5d53064cf48 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4478,7 +4478,7 @@ print_operands (char *buf, const aarch64_opcode *opcode, /* Delimiter. */ if (str[0] != '\0') - strcat (buf, i == 0 ? " " : ","); + strcat (buf, i == 0 ? " " : ", "); /* Append the operand string. */ strcat (buf, str); diff --git a/gas/testsuite/gas/aarch64/ilp32-basic.d b/gas/testsuite/gas/aarch64/ilp32-basic.d index 3caef3e040a..876f28cba28 100644 --- a/gas/testsuite/gas/aarch64/ilp32-basic.d +++ b/gas/testsuite/gas/aarch64/ilp32-basic.d @@ -13,8 +13,8 @@ Disassembly of section \.text: 4: R_AARCH64_P32_ADD_ABS_LO12_NC ptrs 8: b9000080 str w0, \[x4\] 8: R_AARCH64_P32_LDST32_ABS_LO12_NC ptrs - c: b9000461 str w1, \[x3,#4\] - 10: b9000862 str w2, \[x3,#8\] + c: b9000461 str w1, \[x3, #4\] + 10: b9000862 str w2, \[x3, #8\] 14: 90000004 adrp x4, c <.*> 14: R_AARCH64_P32_ADR_GOT_PAGE ptrs 18: f9400083 ldr x3, \[x4\] diff --git a/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d b/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d index 37c8cb9bf25..1c611bbaed6 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d @@ -5,210 +5,210 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 3c1007e7 str b7, \[sp\],#-256 - 4: 3c1557e7 str b7, \[sp\],#-171 - 8: 3c0007e7 str b7, \[sp\],#0 - c: 3c0027e7 str b7, \[sp\],#2 - 10: 3c0047e7 str b7, \[sp\],#4 - 14: 3c0087e7 str b7, \[sp\],#8 - 18: 3c0107e7 str b7, \[sp\],#16 - 1c: 3c0557e7 str b7, \[sp\],#85 - 20: 3c0ff7e7 str b7, \[sp\],#255 - 24: 7c1007e7 str h7, \[sp\],#-256 - 28: 7c1557e7 str h7, \[sp\],#-171 - 2c: 7c0007e7 str h7, \[sp\],#0 - 30: 7c0027e7 str h7, \[sp\],#2 - 34: 7c0047e7 str h7, \[sp\],#4 - 38: 7c0087e7 str h7, \[sp\],#8 - 3c: 7c0107e7 str h7, \[sp\],#16 - 40: 7c0557e7 str h7, \[sp\],#85 - 44: 7c0ff7e7 str h7, \[sp\],#255 - 48: bc1007e7 str s7, \[sp\],#-256 - 4c: bc1557e7 str s7, \[sp\],#-171 - 50: bc0007e7 str s7, \[sp\],#0 - 54: bc0027e7 str s7, \[sp\],#2 - 58: bc0047e7 str s7, \[sp\],#4 - 5c: bc0087e7 str s7, \[sp\],#8 - 60: bc0107e7 str s7, \[sp\],#16 - 64: bc0557e7 str s7, \[sp\],#85 - 68: bc0ff7e7 str s7, \[sp\],#255 - 6c: fc1007e7 str d7, \[sp\],#-256 - 70: fc1557e7 str d7, \[sp\],#-171 - 74: fc0007e7 str d7, \[sp\],#0 - 78: fc0027e7 str d7, \[sp\],#2 - 7c: fc0047e7 str d7, \[sp\],#4 - 80: fc0087e7 str d7, \[sp\],#8 - 84: fc0107e7 str d7, \[sp\],#16 - 88: fc0557e7 str d7, \[sp\],#85 - 8c: fc0ff7e7 str d7, \[sp\],#255 - 90: 3c9007e7 str q7, \[sp\],#-256 - 94: 3c9557e7 str q7, \[sp\],#-171 - 98: 3c8007e7 str q7, \[sp\],#0 - 9c: 3c8027e7 str q7, \[sp\],#2 - a0: 3c8047e7 str q7, \[sp\],#4 - a4: 3c8087e7 str q7, \[sp\],#8 - a8: 3c8107e7 str q7, \[sp\],#16 - ac: 3c8557e7 str q7, \[sp\],#85 - b0: 3c8ff7e7 str q7, \[sp\],#255 - b4: 3c5007e7 ldr b7, \[sp\],#-256 - b8: 3c5557e7 ldr b7, \[sp\],#-171 - bc: 3c4007e7 ldr b7, \[sp\],#0 - c0: 3c4027e7 ldr b7, \[sp\],#2 - c4: 3c4047e7 ldr b7, \[sp\],#4 - c8: 3c4087e7 ldr b7, \[sp\],#8 - cc: 3c4107e7 ldr b7, \[sp\],#16 - d0: 3c4557e7 ldr b7, \[sp\],#85 - d4: 3c4ff7e7 ldr b7, \[sp\],#255 - d8: 7c5007e7 ldr h7, \[sp\],#-256 - dc: 7c5557e7 ldr h7, \[sp\],#-171 - e0: 7c4007e7 ldr h7, \[sp\],#0 - e4: 7c4027e7 ldr h7, \[sp\],#2 - e8: 7c4047e7 ldr h7, \[sp\],#4 - ec: 7c4087e7 ldr h7, \[sp\],#8 - f0: 7c4107e7 ldr h7, \[sp\],#16 - f4: 7c4557e7 ldr h7, \[sp\],#85 - f8: 7c4ff7e7 ldr h7, \[sp\],#255 - fc: bc5007e7 ldr s7, \[sp\],#-256 - 100: bc5557e7 ldr s7, \[sp\],#-171 - 104: bc4007e7 ldr s7, \[sp\],#0 - 108: bc4027e7 ldr s7, \[sp\],#2 - 10c: bc4047e7 ldr s7, \[sp\],#4 - 110: bc4087e7 ldr s7, \[sp\],#8 - 114: bc4107e7 ldr s7, \[sp\],#16 - 118: bc4557e7 ldr s7, \[sp\],#85 - 11c: bc4ff7e7 ldr s7, \[sp\],#255 - 120: fc5007e7 ldr d7, \[sp\],#-256 - 124: fc5557e7 ldr d7, \[sp\],#-171 - 128: fc4007e7 ldr d7, \[sp\],#0 - 12c: fc4027e7 ldr d7, \[sp\],#2 - 130: fc4047e7 ldr d7, \[sp\],#4 - 134: fc4087e7 ldr d7, \[sp\],#8 - 138: fc4107e7 ldr d7, \[sp\],#16 - 13c: fc4557e7 ldr d7, \[sp\],#85 - 140: fc4ff7e7 ldr d7, \[sp\],#255 - 144: 3cd007e7 ldr q7, \[sp\],#-256 - 148: 3cd557e7 ldr q7, \[sp\],#-171 - 14c: 3cc007e7 ldr q7, \[sp\],#0 - 150: 3cc027e7 ldr q7, \[sp\],#2 - 154: 3cc047e7 ldr q7, \[sp\],#4 - 158: 3cc087e7 ldr q7, \[sp\],#8 - 15c: 3cc107e7 ldr q7, \[sp\],#16 - 160: 3cc557e7 ldr q7, \[sp\],#85 - 164: 3ccff7e7 ldr q7, \[sp\],#255 - 168: 381007e7 strb w7, \[sp\],#-256 - 16c: 381557e7 strb w7, \[sp\],#-171 - 170: 380007e7 strb w7, \[sp\],#0 - 174: 380027e7 strb w7, \[sp\],#2 - 178: 380047e7 strb w7, \[sp\],#4 - 17c: 380087e7 strb w7, \[sp\],#8 - 180: 380107e7 strb w7, \[sp\],#16 - 184: 380557e7 strb w7, \[sp\],#85 - 188: 380ff7e7 strb w7, \[sp\],#255 - 18c: 781007e7 strh w7, \[sp\],#-256 - 190: 781557e7 strh w7, \[sp\],#-171 - 194: 780007e7 strh w7, \[sp\],#0 - 198: 780027e7 strh w7, \[sp\],#2 - 19c: 780047e7 strh w7, \[sp\],#4 - 1a0: 780087e7 strh w7, \[sp\],#8 - 1a4: 780107e7 strh w7, \[sp\],#16 - 1a8: 780557e7 strh w7, \[sp\],#85 - 1ac: 780ff7e7 strh w7, \[sp\],#255 - 1b0: b81007e7 str w7, \[sp\],#-256 - 1b4: b81557e7 str w7, \[sp\],#-171 - 1b8: b80007e7 str w7, \[sp\],#0 - 1bc: b80027e7 str w7, \[sp\],#2 - 1c0: b80047e7 str w7, \[sp\],#4 - 1c4: b80087e7 str w7, \[sp\],#8 - 1c8: b80107e7 str w7, \[sp\],#16 - 1cc: b80557e7 str w7, \[sp\],#85 - 1d0: b80ff7e7 str w7, \[sp\],#255 - 1d4: f81007e7 str x7, \[sp\],#-256 - 1d8: f81557e7 str x7, \[sp\],#-171 - 1dc: f80007e7 str x7, \[sp\],#0 - 1e0: f80027e7 str x7, \[sp\],#2 - 1e4: f80047e7 str x7, \[sp\],#4 - 1e8: f80087e7 str x7, \[sp\],#8 - 1ec: f80107e7 str x7, \[sp\],#16 - 1f0: f80557e7 str x7, \[sp\],#85 - 1f4: f80ff7e7 str x7, \[sp\],#255 - 1f8: 385007e7 ldrb w7, \[sp\],#-256 - 1fc: 385557e7 ldrb w7, \[sp\],#-171 - 200: 384007e7 ldrb w7, \[sp\],#0 - 204: 384027e7 ldrb w7, \[sp\],#2 - 208: 384047e7 ldrb w7, \[sp\],#4 - 20c: 384087e7 ldrb w7, \[sp\],#8 - 210: 384107e7 ldrb w7, \[sp\],#16 - 214: 384557e7 ldrb w7, \[sp\],#85 - 218: 384ff7e7 ldrb w7, \[sp\],#255 - 21c: 785007e7 ldrh w7, \[sp\],#-256 - 220: 785557e7 ldrh w7, \[sp\],#-171 - 224: 784007e7 ldrh w7, \[sp\],#0 - 228: 784027e7 ldrh w7, \[sp\],#2 - 22c: 784047e7 ldrh w7, \[sp\],#4 - 230: 784087e7 ldrh w7, \[sp\],#8 - 234: 784107e7 ldrh w7, \[sp\],#16 - 238: 784557e7 ldrh w7, \[sp\],#85 - 23c: 784ff7e7 ldrh w7, \[sp\],#255 - 240: b85007e7 ldr w7, \[sp\],#-256 - 244: b85557e7 ldr w7, \[sp\],#-171 - 248: b84007e7 ldr w7, \[sp\],#0 - 24c: b84027e7 ldr w7, \[sp\],#2 - 250: b84047e7 ldr w7, \[sp\],#4 - 254: b84087e7 ldr w7, \[sp\],#8 - 258: b84107e7 ldr w7, \[sp\],#16 - 25c: b84557e7 ldr w7, \[sp\],#85 - 260: b84ff7e7 ldr w7, \[sp\],#255 - 264: f85007e7 ldr x7, \[sp\],#-256 - 268: f85557e7 ldr x7, \[sp\],#-171 - 26c: f84007e7 ldr x7, \[sp\],#0 - 270: f84027e7 ldr x7, \[sp\],#2 - 274: f84047e7 ldr x7, \[sp\],#4 - 278: f84087e7 ldr x7, \[sp\],#8 - 27c: f84107e7 ldr x7, \[sp\],#16 - 280: f84557e7 ldr x7, \[sp\],#85 - 284: f84ff7e7 ldr x7, \[sp\],#255 - 288: 389007e7 ldrsb x7, \[sp\],#-256 - 28c: 389557e7 ldrsb x7, \[sp\],#-171 - 290: 388007e7 ldrsb x7, \[sp\],#0 - 294: 388027e7 ldrsb x7, \[sp\],#2 - 298: 388047e7 ldrsb x7, \[sp\],#4 - 29c: 388087e7 ldrsb x7, \[sp\],#8 - 2a0: 388107e7 ldrsb x7, \[sp\],#16 - 2a4: 388557e7 ldrsb x7, \[sp\],#85 - 2a8: 388ff7e7 ldrsb x7, \[sp\],#255 - 2ac: 789007e7 ldrsh x7, \[sp\],#-256 - 2b0: 789557e7 ldrsh x7, \[sp\],#-171 - 2b4: 788007e7 ldrsh x7, \[sp\],#0 - 2b8: 788027e7 ldrsh x7, \[sp\],#2 - 2bc: 788047e7 ldrsh x7, \[sp\],#4 - 2c0: 788087e7 ldrsh x7, \[sp\],#8 - 2c4: 788107e7 ldrsh x7, \[sp\],#16 - 2c8: 788557e7 ldrsh x7, \[sp\],#85 - 2cc: 788ff7e7 ldrsh x7, \[sp\],#255 - 2d0: b89007e7 ldrsw x7, \[sp\],#-256 - 2d4: b89557e7 ldrsw x7, \[sp\],#-171 - 2d8: b88007e7 ldrsw x7, \[sp\],#0 - 2dc: b88027e7 ldrsw x7, \[sp\],#2 - 2e0: b88047e7 ldrsw x7, \[sp\],#4 - 2e4: b88087e7 ldrsw x7, \[sp\],#8 - 2e8: b88107e7 ldrsw x7, \[sp\],#16 - 2ec: b88557e7 ldrsw x7, \[sp\],#85 - 2f0: b88ff7e7 ldrsw x7, \[sp\],#255 - 2f4: 38d007e7 ldrsb w7, \[sp\],#-256 - 2f8: 38d557e7 ldrsb w7, \[sp\],#-171 - 2fc: 38c007e7 ldrsb w7, \[sp\],#0 - 300: 38c027e7 ldrsb w7, \[sp\],#2 - 304: 38c047e7 ldrsb w7, \[sp\],#4 - 308: 38c087e7 ldrsb w7, \[sp\],#8 - 30c: 38c107e7 ldrsb w7, \[sp\],#16 - 310: 38c557e7 ldrsb w7, \[sp\],#85 - 314: 38cff7e7 ldrsb w7, \[sp\],#255 - 318: 78d007e7 ldrsh w7, \[sp\],#-256 - 31c: 78d557e7 ldrsh w7, \[sp\],#-171 - 320: 78c007e7 ldrsh w7, \[sp\],#0 - 324: 78c027e7 ldrsh w7, \[sp\],#2 - 328: 78c047e7 ldrsh w7, \[sp\],#4 - 32c: 78c087e7 ldrsh w7, \[sp\],#8 - 330: 78c107e7 ldrsh w7, \[sp\],#16 - 334: 78c557e7 ldrsh w7, \[sp\],#85 - 338: 78cff7e7 ldrsh w7, \[sp\],#255 + 0: 3c1007e7 str b7, \[sp\], #-256 + 4: 3c1557e7 str b7, \[sp\], #-171 + 8: 3c0007e7 str b7, \[sp\], #0 + c: 3c0027e7 str b7, \[sp\], #2 + 10: 3c0047e7 str b7, \[sp\], #4 + 14: 3c0087e7 str b7, \[sp\], #8 + 18: 3c0107e7 str b7, \[sp\], #16 + 1c: 3c0557e7 str b7, \[sp\], #85 + 20: 3c0ff7e7 str b7, \[sp\], #255 + 24: 7c1007e7 str h7, \[sp\], #-256 + 28: 7c1557e7 str h7, \[sp\], #-171 + 2c: 7c0007e7 str h7, \[sp\], #0 + 30: 7c0027e7 str h7, \[sp\], #2 + 34: 7c0047e7 str h7, \[sp\], #4 + 38: 7c0087e7 str h7, \[sp\], #8 + 3c: 7c0107e7 str h7, \[sp\], #16 + 40: 7c0557e7 str h7, \[sp\], #85 + 44: 7c0ff7e7 str h7, \[sp\], #255 + 48: bc1007e7 str s7, \[sp\], #-256 + 4c: bc1557e7 str s7, \[sp\], #-171 + 50: bc0007e7 str s7, \[sp\], #0 + 54: bc0027e7 str s7, \[sp\], #2 + 58: bc0047e7 str s7, \[sp\], #4 + 5c: bc0087e7 str s7, \[sp\], #8 + 60: bc0107e7 str s7, \[sp\], #16 + 64: bc0557e7 str s7, \[sp\], #85 + 68: bc0ff7e7 str s7, \[sp\], #255 + 6c: fc1007e7 str d7, \[sp\], #-256 + 70: fc1557e7 str d7, \[sp\], #-171 + 74: fc0007e7 str d7, \[sp\], #0 + 78: fc0027e7 str d7, \[sp\], #2 + 7c: fc0047e7 str d7, \[sp\], #4 + 80: fc0087e7 str d7, \[sp\], #8 + 84: fc0107e7 str d7, \[sp\], #16 + 88: fc0557e7 str d7, \[sp\], #85 + 8c: fc0ff7e7 str d7, \[sp\], #255 + 90: 3c9007e7 str q7, \[sp\], #-256 + 94: 3c9557e7 str q7, \[sp\], #-171 + 98: 3c8007e7 str q7, \[sp\], #0 + 9c: 3c8027e7 str q7, \[sp\], #2 + a0: 3c8047e7 str q7, \[sp\], #4 + a4: 3c8087e7 str q7, \[sp\], #8 + a8: 3c8107e7 str q7, \[sp\], #16 + ac: 3c8557e7 str q7, \[sp\], #85 + b0: 3c8ff7e7 str q7, \[sp\], #255 + b4: 3c5007e7 ldr b7, \[sp\], #-256 + b8: 3c5557e7 ldr b7, \[sp\], #-171 + bc: 3c4007e7 ldr b7, \[sp\], #0 + c0: 3c4027e7 ldr b7, \[sp\], #2 + c4: 3c4047e7 ldr b7, \[sp\], #4 + c8: 3c4087e7 ldr b7, \[sp\], #8 + cc: 3c4107e7 ldr b7, \[sp\], #16 + d0: 3c4557e7 ldr b7, \[sp\], #85 + d4: 3c4ff7e7 ldr b7, \[sp\], #255 + d8: 7c5007e7 ldr h7, \[sp\], #-256 + dc: 7c5557e7 ldr h7, \[sp\], #-171 + e0: 7c4007e7 ldr h7, \[sp\], #0 + e4: 7c4027e7 ldr h7, \[sp\], #2 + e8: 7c4047e7 ldr h7, \[sp\], #4 + ec: 7c4087e7 ldr h7, \[sp\], #8 + f0: 7c4107e7 ldr h7, \[sp\], #16 + f4: 7c4557e7 ldr h7, \[sp\], #85 + f8: 7c4ff7e7 ldr h7, \[sp\], #255 + fc: bc5007e7 ldr s7, \[sp\], #-256 + 100: bc5557e7 ldr s7, \[sp\], #-171 + 104: bc4007e7 ldr s7, \[sp\], #0 + 108: bc4027e7 ldr s7, \[sp\], #2 + 10c: bc4047e7 ldr s7, \[sp\], #4 + 110: bc4087e7 ldr s7, \[sp\], #8 + 114: bc4107e7 ldr s7, \[sp\], #16 + 118: bc4557e7 ldr s7, \[sp\], #85 + 11c: bc4ff7e7 ldr s7, \[sp\], #255 + 120: fc5007e7 ldr d7, \[sp\], #-256 + 124: fc5557e7 ldr d7, \[sp\], #-171 + 128: fc4007e7 ldr d7, \[sp\], #0 + 12c: fc4027e7 ldr d7, \[sp\], #2 + 130: fc4047e7 ldr d7, \[sp\], #4 + 134: fc4087e7 ldr d7, \[sp\], #8 + 138: fc4107e7 ldr d7, \[sp\], #16 + 13c: fc4557e7 ldr d7, \[sp\], #85 + 140: fc4ff7e7 ldr d7, \[sp\], #255 + 144: 3cd007e7 ldr q7, \[sp\], #-256 + 148: 3cd557e7 ldr q7, \[sp\], #-171 + 14c: 3cc007e7 ldr q7, \[sp\], #0 + 150: 3cc027e7 ldr q7, \[sp\], #2 + 154: 3cc047e7 ldr q7, \[sp\], #4 + 158: 3cc087e7 ldr q7, \[sp\], #8 + 15c: 3cc107e7 ldr q7, \[sp\], #16 + 160: 3cc557e7 ldr q7, \[sp\], #85 + 164: 3ccff7e7 ldr q7, \[sp\], #255 + 168: 381007e7 strb w7, \[sp\], #-256 + 16c: 381557e7 strb w7, \[sp\], #-171 + 170: 380007e7 strb w7, \[sp\], #0 + 174: 380027e7 strb w7, \[sp\], #2 + 178: 380047e7 strb w7, \[sp\], #4 + 17c: 380087e7 strb w7, \[sp\], #8 + 180: 380107e7 strb w7, \[sp\], #16 + 184: 380557e7 strb w7, \[sp\], #85 + 188: 380ff7e7 strb w7, \[sp\], #255 + 18c: 781007e7 strh w7, \[sp\], #-256 + 190: 781557e7 strh w7, \[sp\], #-171 + 194: 780007e7 strh w7, \[sp\], #0 + 198: 780027e7 strh w7, \[sp\], #2 + 19c: 780047e7 strh w7, \[sp\], #4 + 1a0: 780087e7 strh w7, \[sp\], #8 + 1a4: 780107e7 strh w7, \[sp\], #16 + 1a8: 780557e7 strh w7, \[sp\], #85 + 1ac: 780ff7e7 strh w7, \[sp\], #255 + 1b0: b81007e7 str w7, \[sp\], #-256 + 1b4: b81557e7 str w7, \[sp\], #-171 + 1b8: b80007e7 str w7, \[sp\], #0 + 1bc: b80027e7 str w7, \[sp\], #2 + 1c0: b80047e7 str w7, \[sp\], #4 + 1c4: b80087e7 str w7, \[sp\], #8 + 1c8: b80107e7 str w7, \[sp\], #16 + 1cc: b80557e7 str w7, \[sp\], #85 + 1d0: b80ff7e7 str w7, \[sp\], #255 + 1d4: f81007e7 str x7, \[sp\], #-256 + 1d8: f81557e7 str x7, \[sp\], #-171 + 1dc: f80007e7 str x7, \[sp\], #0 + 1e0: f80027e7 str x7, \[sp\], #2 + 1e4: f80047e7 str x7, \[sp\], #4 + 1e8: f80087e7 str x7, \[sp\], #8 + 1ec: f80107e7 str x7, \[sp\], #16 + 1f0: f80557e7 str x7, \[sp\], #85 + 1f4: f80ff7e7 str x7, \[sp\], #255 + 1f8: 385007e7 ldrb w7, \[sp\], #-256 + 1fc: 385557e7 ldrb w7, \[sp\], #-171 + 200: 384007e7 ldrb w7, \[sp\], #0 + 204: 384027e7 ldrb w7, \[sp\], #2 + 208: 384047e7 ldrb w7, \[sp\], #4 + 20c: 384087e7 ldrb w7, \[sp\], #8 + 210: 384107e7 ldrb w7, \[sp\], #16 + 214: 384557e7 ldrb w7, \[sp\], #85 + 218: 384ff7e7 ldrb w7, \[sp\], #255 + 21c: 785007e7 ldrh w7, \[sp\], #-256 + 220: 785557e7 ldrh w7, \[sp\], #-171 + 224: 784007e7 ldrh w7, \[sp\], #0 + 228: 784027e7 ldrh w7, \[sp\], #2 + 22c: 784047e7 ldrh w7, \[sp\], #4 + 230: 784087e7 ldrh w7, \[sp\], #8 + 234: 784107e7 ldrh w7, \[sp\], #16 + 238: 784557e7 ldrh w7, \[sp\], #85 + 23c: 784ff7e7 ldrh w7, \[sp\], #255 + 240: b85007e7 ldr w7, \[sp\], #-256 + 244: b85557e7 ldr w7, \[sp\], #-171 + 248: b84007e7 ldr w7, \[sp\], #0 + 24c: b84027e7 ldr w7, \[sp\], #2 + 250: b84047e7 ldr w7, \[sp\], #4 + 254: b84087e7 ldr w7, \[sp\], #8 + 258: b84107e7 ldr w7, \[sp\], #16 + 25c: b84557e7 ldr w7, \[sp\], #85 + 260: b84ff7e7 ldr w7, \[sp\], #255 + 264: f85007e7 ldr x7, \[sp\], #-256 + 268: f85557e7 ldr x7, \[sp\], #-171 + 26c: f84007e7 ldr x7, \[sp\], #0 + 270: f84027e7 ldr x7, \[sp\], #2 + 274: f84047e7 ldr x7, \[sp\], #4 + 278: f84087e7 ldr x7, \[sp\], #8 + 27c: f84107e7 ldr x7, \[sp\], #16 + 280: f84557e7 ldr x7, \[sp\], #85 + 284: f84ff7e7 ldr x7, \[sp\], #255 + 288: 389007e7 ldrsb x7, \[sp\], #-256 + 28c: 389557e7 ldrsb x7, \[sp\], #-171 + 290: 388007e7 ldrsb x7, \[sp\], #0 + 294: 388027e7 ldrsb x7, \[sp\], #2 + 298: 388047e7 ldrsb x7, \[sp\], #4 + 29c: 388087e7 ldrsb x7, \[sp\], #8 + 2a0: 388107e7 ldrsb x7, \[sp\], #16 + 2a4: 388557e7 ldrsb x7, \[sp\], #85 + 2a8: 388ff7e7 ldrsb x7, \[sp\], #255 + 2ac: 789007e7 ldrsh x7, \[sp\], #-256 + 2b0: 789557e7 ldrsh x7, \[sp\], #-171 + 2b4: 788007e7 ldrsh x7, \[sp\], #0 + 2b8: 788027e7 ldrsh x7, \[sp\], #2 + 2bc: 788047e7 ldrsh x7, \[sp\], #4 + 2c0: 788087e7 ldrsh x7, \[sp\], #8 + 2c4: 788107e7 ldrsh x7, \[sp\], #16 + 2c8: 788557e7 ldrsh x7, \[sp\], #85 + 2cc: 788ff7e7 ldrsh x7, \[sp\], #255 + 2d0: b89007e7 ldrsw x7, \[sp\], #-256 + 2d4: b89557e7 ldrsw x7, \[sp\], #-171 + 2d8: b88007e7 ldrsw x7, \[sp\], #0 + 2dc: b88027e7 ldrsw x7, \[sp\], #2 + 2e0: b88047e7 ldrsw x7, \[sp\], #4 + 2e4: b88087e7 ldrsw x7, \[sp\], #8 + 2e8: b88107e7 ldrsw x7, \[sp\], #16 + 2ec: b88557e7 ldrsw x7, \[sp\], #85 + 2f0: b88ff7e7 ldrsw x7, \[sp\], #255 + 2f4: 38d007e7 ldrsb w7, \[sp\], #-256 + 2f8: 38d557e7 ldrsb w7, \[sp\], #-171 + 2fc: 38c007e7 ldrsb w7, \[sp\], #0 + 300: 38c027e7 ldrsb w7, \[sp\], #2 + 304: 38c047e7 ldrsb w7, \[sp\], #4 + 308: 38c087e7 ldrsb w7, \[sp\], #8 + 30c: 38c107e7 ldrsb w7, \[sp\], #16 + 310: 38c557e7 ldrsb w7, \[sp\], #85 + 314: 38cff7e7 ldrsb w7, \[sp\], #255 + 318: 78d007e7 ldrsh w7, \[sp\], #-256 + 31c: 78d557e7 ldrsh w7, \[sp\], #-171 + 320: 78c007e7 ldrsh w7, \[sp\], #0 + 324: 78c027e7 ldrsh w7, \[sp\], #2 + 328: 78c047e7 ldrsh w7, \[sp\], #4 + 32c: 78c087e7 ldrsh w7, \[sp\], #8 + 330: 78c107e7 ldrsh w7, \[sp\], #16 + 334: 78c557e7 ldrsh w7, \[sp\], #85 + 338: 78cff7e7 ldrsh w7, \[sp\], #255 diff --git a/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d b/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d index 423202c4b06..14a1e04c59b 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d @@ -5,210 +5,210 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 3c100fe7 str b7, \[sp,#-256\]! - 4: 3c155fe7 str b7, \[sp,#-171\]! - 8: 3c000fe7 str b7, \[sp,#0\]! - c: 3c002fe7 str b7, \[sp,#2\]! - 10: 3c004fe7 str b7, \[sp,#4\]! - 14: 3c008fe7 str b7, \[sp,#8\]! - 18: 3c010fe7 str b7, \[sp,#16\]! - 1c: 3c055fe7 str b7, \[sp,#85\]! - 20: 3c0fffe7 str b7, \[sp,#255\]! - 24: 7c100fe7 str h7, \[sp,#-256\]! - 28: 7c155fe7 str h7, \[sp,#-171\]! - 2c: 7c000fe7 str h7, \[sp,#0\]! - 30: 7c002fe7 str h7, \[sp,#2\]! - 34: 7c004fe7 str h7, \[sp,#4\]! - 38: 7c008fe7 str h7, \[sp,#8\]! - 3c: 7c010fe7 str h7, \[sp,#16\]! - 40: 7c055fe7 str h7, \[sp,#85\]! - 44: 7c0fffe7 str h7, \[sp,#255\]! - 48: bc100fe7 str s7, \[sp,#-256\]! - 4c: bc155fe7 str s7, \[sp,#-171\]! - 50: bc000fe7 str s7, \[sp,#0\]! - 54: bc002fe7 str s7, \[sp,#2\]! - 58: bc004fe7 str s7, \[sp,#4\]! - 5c: bc008fe7 str s7, \[sp,#8\]! - 60: bc010fe7 str s7, \[sp,#16\]! - 64: bc055fe7 str s7, \[sp,#85\]! - 68: bc0fffe7 str s7, \[sp,#255\]! - 6c: fc100fe7 str d7, \[sp,#-256\]! - 70: fc155fe7 str d7, \[sp,#-171\]! - 74: fc000fe7 str d7, \[sp,#0\]! - 78: fc002fe7 str d7, \[sp,#2\]! - 7c: fc004fe7 str d7, \[sp,#4\]! - 80: fc008fe7 str d7, \[sp,#8\]! - 84: fc010fe7 str d7, \[sp,#16\]! - 88: fc055fe7 str d7, \[sp,#85\]! - 8c: fc0fffe7 str d7, \[sp,#255\]! - 90: 3c900fe7 str q7, \[sp,#-256\]! - 94: 3c955fe7 str q7, \[sp,#-171\]! - 98: 3c800fe7 str q7, \[sp,#0\]! - 9c: 3c802fe7 str q7, \[sp,#2\]! - a0: 3c804fe7 str q7, \[sp,#4\]! - a4: 3c808fe7 str q7, \[sp,#8\]! - a8: 3c810fe7 str q7, \[sp,#16\]! - ac: 3c855fe7 str q7, \[sp,#85\]! - b0: 3c8fffe7 str q7, \[sp,#255\]! - b4: 3c500fe7 ldr b7, \[sp,#-256\]! - b8: 3c555fe7 ldr b7, \[sp,#-171\]! - bc: 3c400fe7 ldr b7, \[sp,#0\]! - c0: 3c402fe7 ldr b7, \[sp,#2\]! - c4: 3c404fe7 ldr b7, \[sp,#4\]! - c8: 3c408fe7 ldr b7, \[sp,#8\]! - cc: 3c410fe7 ldr b7, \[sp,#16\]! - d0: 3c455fe7 ldr b7, \[sp,#85\]! - d4: 3c4fffe7 ldr b7, \[sp,#255\]! - d8: 7c500fe7 ldr h7, \[sp,#-256\]! - dc: 7c555fe7 ldr h7, \[sp,#-171\]! - e0: 7c400fe7 ldr h7, \[sp,#0\]! - e4: 7c402fe7 ldr h7, \[sp,#2\]! - e8: 7c404fe7 ldr h7, \[sp,#4\]! - ec: 7c408fe7 ldr h7, \[sp,#8\]! - f0: 7c410fe7 ldr h7, \[sp,#16\]! - f4: 7c455fe7 ldr h7, \[sp,#85\]! - f8: 7c4fffe7 ldr h7, \[sp,#255\]! - fc: bc500fe7 ldr s7, \[sp,#-256\]! - 100: bc555fe7 ldr s7, \[sp,#-171\]! - 104: bc400fe7 ldr s7, \[sp,#0\]! - 108: bc402fe7 ldr s7, \[sp,#2\]! - 10c: bc404fe7 ldr s7, \[sp,#4\]! - 110: bc408fe7 ldr s7, \[sp,#8\]! - 114: bc410fe7 ldr s7, \[sp,#16\]! - 118: bc455fe7 ldr s7, \[sp,#85\]! - 11c: bc4fffe7 ldr s7, \[sp,#255\]! - 120: fc500fe7 ldr d7, \[sp,#-256\]! - 124: fc555fe7 ldr d7, \[sp,#-171\]! - 128: fc400fe7 ldr d7, \[sp,#0\]! - 12c: fc402fe7 ldr d7, \[sp,#2\]! - 130: fc404fe7 ldr d7, \[sp,#4\]! - 134: fc408fe7 ldr d7, \[sp,#8\]! - 138: fc410fe7 ldr d7, \[sp,#16\]! - 13c: fc455fe7 ldr d7, \[sp,#85\]! - 140: fc4fffe7 ldr d7, \[sp,#255\]! - 144: 3cd00fe7 ldr q7, \[sp,#-256\]! - 148: 3cd55fe7 ldr q7, \[sp,#-171\]! - 14c: 3cc00fe7 ldr q7, \[sp,#0\]! - 150: 3cc02fe7 ldr q7, \[sp,#2\]! - 154: 3cc04fe7 ldr q7, \[sp,#4\]! - 158: 3cc08fe7 ldr q7, \[sp,#8\]! - 15c: 3cc10fe7 ldr q7, \[sp,#16\]! - 160: 3cc55fe7 ldr q7, \[sp,#85\]! - 164: 3ccfffe7 ldr q7, \[sp,#255\]! - 168: 38100fe7 strb w7, \[sp,#-256\]! - 16c: 38155fe7 strb w7, \[sp,#-171\]! - 170: 38000fe7 strb w7, \[sp,#0\]! - 174: 38002fe7 strb w7, \[sp,#2\]! - 178: 38004fe7 strb w7, \[sp,#4\]! - 17c: 38008fe7 strb w7, \[sp,#8\]! - 180: 38010fe7 strb w7, \[sp,#16\]! - 184: 38055fe7 strb w7, \[sp,#85\]! - 188: 380fffe7 strb w7, \[sp,#255\]! - 18c: 78100fe7 strh w7, \[sp,#-256\]! - 190: 78155fe7 strh w7, \[sp,#-171\]! - 194: 78000fe7 strh w7, \[sp,#0\]! - 198: 78002fe7 strh w7, \[sp,#2\]! - 19c: 78004fe7 strh w7, \[sp,#4\]! - 1a0: 78008fe7 strh w7, \[sp,#8\]! - 1a4: 78010fe7 strh w7, \[sp,#16\]! - 1a8: 78055fe7 strh w7, \[sp,#85\]! - 1ac: 780fffe7 strh w7, \[sp,#255\]! - 1b0: b8100fe7 str w7, \[sp,#-256\]! - 1b4: b8155fe7 str w7, \[sp,#-171\]! - 1b8: b8000fe7 str w7, \[sp,#0\]! - 1bc: b8002fe7 str w7, \[sp,#2\]! - 1c0: b8004fe7 str w7, \[sp,#4\]! - 1c4: b8008fe7 str w7, \[sp,#8\]! - 1c8: b8010fe7 str w7, \[sp,#16\]! - 1cc: b8055fe7 str w7, \[sp,#85\]! - 1d0: b80fffe7 str w7, \[sp,#255\]! - 1d4: f8100fe7 str x7, \[sp,#-256\]! - 1d8: f8155fe7 str x7, \[sp,#-171\]! - 1dc: f8000fe7 str x7, \[sp,#0\]! - 1e0: f8002fe7 str x7, \[sp,#2\]! - 1e4: f8004fe7 str x7, \[sp,#4\]! - 1e8: f8008fe7 str x7, \[sp,#8\]! - 1ec: f8010fe7 str x7, \[sp,#16\]! - 1f0: f8055fe7 str x7, \[sp,#85\]! - 1f4: f80fffe7 str x7, \[sp,#255\]! - 1f8: 38500fe7 ldrb w7, \[sp,#-256\]! - 1fc: 38555fe7 ldrb w7, \[sp,#-171\]! - 200: 38400fe7 ldrb w7, \[sp,#0\]! - 204: 38402fe7 ldrb w7, \[sp,#2\]! - 208: 38404fe7 ldrb w7, \[sp,#4\]! - 20c: 38408fe7 ldrb w7, \[sp,#8\]! - 210: 38410fe7 ldrb w7, \[sp,#16\]! - 214: 38455fe7 ldrb w7, \[sp,#85\]! - 218: 384fffe7 ldrb w7, \[sp,#255\]! - 21c: 78500fe7 ldrh w7, \[sp,#-256\]! - 220: 78555fe7 ldrh w7, \[sp,#-171\]! - 224: 78400fe7 ldrh w7, \[sp,#0\]! - 228: 78402fe7 ldrh w7, \[sp,#2\]! - 22c: 78404fe7 ldrh w7, \[sp,#4\]! - 230: 78408fe7 ldrh w7, \[sp,#8\]! - 234: 78410fe7 ldrh w7, \[sp,#16\]! - 238: 78455fe7 ldrh w7, \[sp,#85\]! - 23c: 784fffe7 ldrh w7, \[sp,#255\]! - 240: b8500fe7 ldr w7, \[sp,#-256\]! - 244: b8555fe7 ldr w7, \[sp,#-171\]! - 248: b8400fe7 ldr w7, \[sp,#0\]! - 24c: b8402fe7 ldr w7, \[sp,#2\]! - 250: b8404fe7 ldr w7, \[sp,#4\]! - 254: b8408fe7 ldr w7, \[sp,#8\]! - 258: b8410fe7 ldr w7, \[sp,#16\]! - 25c: b8455fe7 ldr w7, \[sp,#85\]! - 260: b84fffe7 ldr w7, \[sp,#255\]! - 264: f8500fe7 ldr x7, \[sp,#-256\]! - 268: f8555fe7 ldr x7, \[sp,#-171\]! - 26c: f8400fe7 ldr x7, \[sp,#0\]! - 270: f8402fe7 ldr x7, \[sp,#2\]! - 274: f8404fe7 ldr x7, \[sp,#4\]! - 278: f8408fe7 ldr x7, \[sp,#8\]! - 27c: f8410fe7 ldr x7, \[sp,#16\]! - 280: f8455fe7 ldr x7, \[sp,#85\]! - 284: f84fffe7 ldr x7, \[sp,#255\]! - 288: 38900fe7 ldrsb x7, \[sp,#-256\]! - 28c: 38955fe7 ldrsb x7, \[sp,#-171\]! - 290: 38800fe7 ldrsb x7, \[sp,#0\]! - 294: 38802fe7 ldrsb x7, \[sp,#2\]! - 298: 38804fe7 ldrsb x7, \[sp,#4\]! - 29c: 38808fe7 ldrsb x7, \[sp,#8\]! - 2a0: 38810fe7 ldrsb x7, \[sp,#16\]! - 2a4: 38855fe7 ldrsb x7, \[sp,#85\]! - 2a8: 388fffe7 ldrsb x7, \[sp,#255\]! - 2ac: 78900fe7 ldrsh x7, \[sp,#-256\]! - 2b0: 78955fe7 ldrsh x7, \[sp,#-171\]! - 2b4: 78800fe7 ldrsh x7, \[sp,#0\]! - 2b8: 78802fe7 ldrsh x7, \[sp,#2\]! - 2bc: 78804fe7 ldrsh x7, \[sp,#4\]! - 2c0: 78808fe7 ldrsh x7, \[sp,#8\]! - 2c4: 78810fe7 ldrsh x7, \[sp,#16\]! - 2c8: 78855fe7 ldrsh x7, \[sp,#85\]! - 2cc: 788fffe7 ldrsh x7, \[sp,#255\]! - 2d0: b8900fe7 ldrsw x7, \[sp,#-256\]! - 2d4: b8955fe7 ldrsw x7, \[sp,#-171\]! - 2d8: b8800fe7 ldrsw x7, \[sp,#0\]! - 2dc: b8802fe7 ldrsw x7, \[sp,#2\]! - 2e0: b8804fe7 ldrsw x7, \[sp,#4\]! - 2e4: b8808fe7 ldrsw x7, \[sp,#8\]! - 2e8: b8810fe7 ldrsw x7, \[sp,#16\]! - 2ec: b8855fe7 ldrsw x7, \[sp,#85\]! - 2f0: b88fffe7 ldrsw x7, \[sp,#255\]! - 2f4: 38d00fe7 ldrsb w7, \[sp,#-256\]! - 2f8: 38d55fe7 ldrsb w7, \[sp,#-171\]! - 2fc: 38c00fe7 ldrsb w7, \[sp,#0\]! - 300: 38c02fe7 ldrsb w7, \[sp,#2\]! - 304: 38c04fe7 ldrsb w7, \[sp,#4\]! - 308: 38c08fe7 ldrsb w7, \[sp,#8\]! - 30c: 38c10fe7 ldrsb w7, \[sp,#16\]! - 310: 38c55fe7 ldrsb w7, \[sp,#85\]! - 314: 38cfffe7 ldrsb w7, \[sp,#255\]! - 318: 78d00fe7 ldrsh w7, \[sp,#-256\]! - 31c: 78d55fe7 ldrsh w7, \[sp,#-171\]! - 320: 78c00fe7 ldrsh w7, \[sp,#0\]! - 324: 78c02fe7 ldrsh w7, \[sp,#2\]! - 328: 78c04fe7 ldrsh w7, \[sp,#4\]! - 32c: 78c08fe7 ldrsh w7, \[sp,#8\]! - 330: 78c10fe7 ldrsh w7, \[sp,#16\]! - 334: 78c55fe7 ldrsh w7, \[sp,#85\]! - 338: 78cfffe7 ldrsh w7, \[sp,#255\]! + 0: 3c100fe7 str b7, \[sp, #-256\]! + 4: 3c155fe7 str b7, \[sp, #-171\]! + 8: 3c000fe7 str b7, \[sp, #0\]! + c: 3c002fe7 str b7, \[sp, #2\]! + 10: 3c004fe7 str b7, \[sp, #4\]! + 14: 3c008fe7 str b7, \[sp, #8\]! + 18: 3c010fe7 str b7, \[sp, #16\]! + 1c: 3c055fe7 str b7, \[sp, #85\]! + 20: 3c0fffe7 str b7, \[sp, #255\]! + 24: 7c100fe7 str h7, \[sp, #-256\]! + 28: 7c155fe7 str h7, \[sp, #-171\]! + 2c: 7c000fe7 str h7, \[sp, #0\]! + 30: 7c002fe7 str h7, \[sp, #2\]! + 34: 7c004fe7 str h7, \[sp, #4\]! + 38: 7c008fe7 str h7, \[sp, #8\]! + 3c: 7c010fe7 str h7, \[sp, #16\]! + 40: 7c055fe7 str h7, \[sp, #85\]! + 44: 7c0fffe7 str h7, \[sp, #255\]! + 48: bc100fe7 str s7, \[sp, #-256\]! + 4c: bc155fe7 str s7, \[sp, #-171\]! + 50: bc000fe7 str s7, \[sp, #0\]! + 54: bc002fe7 str s7, \[sp, #2\]! + 58: bc004fe7 str s7, \[sp, #4\]! + 5c: bc008fe7 str s7, \[sp, #8\]! + 60: bc010fe7 str s7, \[sp, #16\]! + 64: bc055fe7 str s7, \[sp, #85\]! + 68: bc0fffe7 str s7, \[sp, #255\]! + 6c: fc100fe7 str d7, \[sp, #-256\]! + 70: fc155fe7 str d7, \[sp, #-171\]! + 74: fc000fe7 str d7, \[sp, #0\]! + 78: fc002fe7 str d7, \[sp, #2\]! + 7c: fc004fe7 str d7, \[sp, #4\]! + 80: fc008fe7 str d7, \[sp, #8\]! + 84: fc010fe7 str d7, \[sp, #16\]! + 88: fc055fe7 str d7, \[sp, #85\]! + 8c: fc0fffe7 str d7, \[sp, #255\]! + 90: 3c900fe7 str q7, \[sp, #-256\]! + 94: 3c955fe7 str q7, \[sp, #-171\]! + 98: 3c800fe7 str q7, \[sp, #0\]! + 9c: 3c802fe7 str q7, \[sp, #2\]! + a0: 3c804fe7 str q7, \[sp, #4\]! + a4: 3c808fe7 str q7, \[sp, #8\]! + a8: 3c810fe7 str q7, \[sp, #16\]! + ac: 3c855fe7 str q7, \[sp, #85\]! + b0: 3c8fffe7 str q7, \[sp, #255\]! + b4: 3c500fe7 ldr b7, \[sp, #-256\]! + b8: 3c555fe7 ldr b7, \[sp, #-171\]! + bc: 3c400fe7 ldr b7, \[sp, #0\]! + c0: 3c402fe7 ldr b7, \[sp, #2\]! + c4: 3c404fe7 ldr b7, \[sp, #4\]! + c8: 3c408fe7 ldr b7, \[sp, #8\]! + cc: 3c410fe7 ldr b7, \[sp, #16\]! + d0: 3c455fe7 ldr b7, \[sp, #85\]! + d4: 3c4fffe7 ldr b7, \[sp, #255\]! + d8: 7c500fe7 ldr h7, \[sp, #-256\]! + dc: 7c555fe7 ldr h7, \[sp, #-171\]! + e0: 7c400fe7 ldr h7, \[sp, #0\]! + e4: 7c402fe7 ldr h7, \[sp, #2\]! + e8: 7c404fe7 ldr h7, \[sp, #4\]! + ec: 7c408fe7 ldr h7, \[sp, #8\]! + f0: 7c410fe7 ldr h7, \[sp, #16\]! + f4: 7c455fe7 ldr h7, \[sp, #85\]! + f8: 7c4fffe7 ldr h7, \[sp, #255\]! + fc: bc500fe7 ldr s7, \[sp, #-256\]! + 100: bc555fe7 ldr s7, \[sp, #-171\]! + 104: bc400fe7 ldr s7, \[sp, #0\]! + 108: bc402fe7 ldr s7, \[sp, #2\]! + 10c: bc404fe7 ldr s7, \[sp, #4\]! + 110: bc408fe7 ldr s7, \[sp, #8\]! + 114: bc410fe7 ldr s7, \[sp, #16\]! + 118: bc455fe7 ldr s7, \[sp, #85\]! + 11c: bc4fffe7 ldr s7, \[sp, #255\]! + 120: fc500fe7 ldr d7, \[sp, #-256\]! + 124: fc555fe7 ldr d7, \[sp, #-171\]! + 128: fc400fe7 ldr d7, \[sp, #0\]! + 12c: fc402fe7 ldr d7, \[sp, #2\]! + 130: fc404fe7 ldr d7, \[sp, #4\]! + 134: fc408fe7 ldr d7, \[sp, #8\]! + 138: fc410fe7 ldr d7, \[sp, #16\]! + 13c: fc455fe7 ldr d7, \[sp, #85\]! + 140: fc4fffe7 ldr d7, \[sp, #255\]! + 144: 3cd00fe7 ldr q7, \[sp, #-256\]! + 148: 3cd55fe7 ldr q7, \[sp, #-171\]! + 14c: 3cc00fe7 ldr q7, \[sp, #0\]! + 150: 3cc02fe7 ldr q7, \[sp, #2\]! + 154: 3cc04fe7 ldr q7, \[sp, #4\]! + 158: 3cc08fe7 ldr q7, \[sp, #8\]! + 15c: 3cc10fe7 ldr q7, \[sp, #16\]! + 160: 3cc55fe7 ldr q7, \[sp, #85\]! + 164: 3ccfffe7 ldr q7, \[sp, #255\]! + 168: 38100fe7 strb w7, \[sp, #-256\]! + 16c: 38155fe7 strb w7, \[sp, #-171\]! + 170: 38000fe7 strb w7, \[sp, #0\]! + 174: 38002fe7 strb w7, \[sp, #2\]! + 178: 38004fe7 strb w7, \[sp, #4\]! + 17c: 38008fe7 strb w7, \[sp, #8\]! + 180: 38010fe7 strb w7, \[sp, #16\]! + 184: 38055fe7 strb w7, \[sp, #85\]! + 188: 380fffe7 strb w7, \[sp, #255\]! + 18c: 78100fe7 strh w7, \[sp, #-256\]! + 190: 78155fe7 strh w7, \[sp, #-171\]! + 194: 78000fe7 strh w7, \[sp, #0\]! + 198: 78002fe7 strh w7, \[sp, #2\]! + 19c: 78004fe7 strh w7, \[sp, #4\]! + 1a0: 78008fe7 strh w7, \[sp, #8\]! + 1a4: 78010fe7 strh w7, \[sp, #16\]! + 1a8: 78055fe7 strh w7, \[sp, #85\]! + 1ac: 780fffe7 strh w7, \[sp, #255\]! + 1b0: b8100fe7 str w7, \[sp, #-256\]! + 1b4: b8155fe7 str w7, \[sp, #-171\]! + 1b8: b8000fe7 str w7, \[sp, #0\]! + 1bc: b8002fe7 str w7, \[sp, #2\]! + 1c0: b8004fe7 str w7, \[sp, #4\]! + 1c4: b8008fe7 str w7, \[sp, #8\]! + 1c8: b8010fe7 str w7, \[sp, #16\]! + 1cc: b8055fe7 str w7, \[sp, #85\]! + 1d0: b80fffe7 str w7, \[sp, #255\]! + 1d4: f8100fe7 str x7, \[sp, #-256\]! + 1d8: f8155fe7 str x7, \[sp, #-171\]! + 1dc: f8000fe7 str x7, \[sp, #0\]! + 1e0: f8002fe7 str x7, \[sp, #2\]! + 1e4: f8004fe7 str x7, \[sp, #4\]! + 1e8: f8008fe7 str x7, \[sp, #8\]! + 1ec: f8010fe7 str x7, \[sp, #16\]! + 1f0: f8055fe7 str x7, \[sp, #85\]! + 1f4: f80fffe7 str x7, \[sp, #255\]! + 1f8: 38500fe7 ldrb w7, \[sp, #-256\]! + 1fc: 38555fe7 ldrb w7, \[sp, #-171\]! + 200: 38400fe7 ldrb w7, \[sp, #0\]! + 204: 38402fe7 ldrb w7, \[sp, #2\]! + 208: 38404fe7 ldrb w7, \[sp, #4\]! + 20c: 38408fe7 ldrb w7, \[sp, #8\]! + 210: 38410fe7 ldrb w7, \[sp, #16\]! + 214: 38455fe7 ldrb w7, \[sp, #85\]! + 218: 384fffe7 ldrb w7, \[sp, #255\]! + 21c: 78500fe7 ldrh w7, \[sp, #-256\]! + 220: 78555fe7 ldrh w7, \[sp, #-171\]! + 224: 78400fe7 ldrh w7, \[sp, #0\]! + 228: 78402fe7 ldrh w7, \[sp, #2\]! + 22c: 78404fe7 ldrh w7, \[sp, #4\]! + 230: 78408fe7 ldrh w7, \[sp, #8\]! + 234: 78410fe7 ldrh w7, \[sp, #16\]! + 238: 78455fe7 ldrh w7, \[sp, #85\]! + 23c: 784fffe7 ldrh w7, \[sp, #255\]! + 240: b8500fe7 ldr w7, \[sp, #-256\]! + 244: b8555fe7 ldr w7, \[sp, #-171\]! + 248: b8400fe7 ldr w7, \[sp, #0\]! + 24c: b8402fe7 ldr w7, \[sp, #2\]! + 250: b8404fe7 ldr w7, \[sp, #4\]! + 254: b8408fe7 ldr w7, \[sp, #8\]! + 258: b8410fe7 ldr w7, \[sp, #16\]! + 25c: b8455fe7 ldr w7, \[sp, #85\]! + 260: b84fffe7 ldr w7, \[sp, #255\]! + 264: f8500fe7 ldr x7, \[sp, #-256\]! + 268: f8555fe7 ldr x7, \[sp, #-171\]! + 26c: f8400fe7 ldr x7, \[sp, #0\]! + 270: f8402fe7 ldr x7, \[sp, #2\]! + 274: f8404fe7 ldr x7, \[sp, #4\]! + 278: f8408fe7 ldr x7, \[sp, #8\]! + 27c: f8410fe7 ldr x7, \[sp, #16\]! + 280: f8455fe7 ldr x7, \[sp, #85\]! + 284: f84fffe7 ldr x7, \[sp, #255\]! + 288: 38900fe7 ldrsb x7, \[sp, #-256\]! + 28c: 38955fe7 ldrsb x7, \[sp, #-171\]! + 290: 38800fe7 ldrsb x7, \[sp, #0\]! + 294: 38802fe7 ldrsb x7, \[sp, #2\]! + 298: 38804fe7 ldrsb x7, \[sp, #4\]! + 29c: 38808fe7 ldrsb x7, \[sp, #8\]! + 2a0: 38810fe7 ldrsb x7, \[sp, #16\]! + 2a4: 38855fe7 ldrsb x7, \[sp, #85\]! + 2a8: 388fffe7 ldrsb x7, \[sp, #255\]! + 2ac: 78900fe7 ldrsh x7, \[sp, #-256\]! + 2b0: 78955fe7 ldrsh x7, \[sp, #-171\]! + 2b4: 78800fe7 ldrsh x7, \[sp, #0\]! + 2b8: 78802fe7 ldrsh x7, \[sp, #2\]! + 2bc: 78804fe7 ldrsh x7, \[sp, #4\]! + 2c0: 78808fe7 ldrsh x7, \[sp, #8\]! + 2c4: 78810fe7 ldrsh x7, \[sp, #16\]! + 2c8: 78855fe7 ldrsh x7, \[sp, #85\]! + 2cc: 788fffe7 ldrsh x7, \[sp, #255\]! + 2d0: b8900fe7 ldrsw x7, \[sp, #-256\]! + 2d4: b8955fe7 ldrsw x7, \[sp, #-171\]! + 2d8: b8800fe7 ldrsw x7, \[sp, #0\]! + 2dc: b8802fe7 ldrsw x7, \[sp, #2\]! + 2e0: b8804fe7 ldrsw x7, \[sp, #4\]! + 2e4: b8808fe7 ldrsw x7, \[sp, #8\]! + 2e8: b8810fe7 ldrsw x7, \[sp, #16\]! + 2ec: b8855fe7 ldrsw x7, \[sp, #85\]! + 2f0: b88fffe7 ldrsw x7, \[sp, #255\]! + 2f4: 38d00fe7 ldrsb w7, \[sp, #-256\]! + 2f8: 38d55fe7 ldrsb w7, \[sp, #-171\]! + 2fc: 38c00fe7 ldrsb w7, \[sp, #0\]! + 300: 38c02fe7 ldrsb w7, \[sp, #2\]! + 304: 38c04fe7 ldrsb w7, \[sp, #4\]! + 308: 38c08fe7 ldrsb w7, \[sp, #8\]! + 30c: 38c10fe7 ldrsb w7, \[sp, #16\]! + 310: 38c55fe7 ldrsb w7, \[sp, #85\]! + 314: 38cfffe7 ldrsb w7, \[sp, #255\]! + 318: 78d00fe7 ldrsh w7, \[sp, #-256\]! + 31c: 78d55fe7 ldrsh w7, \[sp, #-171\]! + 320: 78c00fe7 ldrsh w7, \[sp, #0\]! + 324: 78c02fe7 ldrsh w7, \[sp, #2\]! + 328: 78c04fe7 ldrsh w7, \[sp, #4\]! + 32c: 78c08fe7 ldrsh w7, \[sp, #8\]! + 330: 78c10fe7 ldrsh w7, \[sp, #16\]! + 334: 78c55fe7 ldrsh w7, \[sp, #85\]! + 338: 78cfffe7 ldrsh w7, \[sp, #255\]! diff --git a/gas/testsuite/gas/aarch64/ldst-reg-pair.d b/gas/testsuite/gas/aarch64/ldst-reg-pair.d index 4b24a9ff630..8ce7df6049f 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-pair.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-pair.d @@ -5,261 +5,261 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 29203fe7 stp w7, w15, \[sp,#-256\] - 4: 2930bfe7 stp w7, w15, \[sp,#-124\] - 8: 293fbfe7 stp w7, w15, \[sp,#-4\] + 0: 29203fe7 stp w7, w15, \[sp, #-256\] + 4: 2930bfe7 stp w7, w15, \[sp, #-124\] + 8: 293fbfe7 stp w7, w15, \[sp, #-4\] c: 29003fe7 stp w7, w15, \[sp\] - 10: 2907bfe7 stp w7, w15, \[sp,#60\] - 14: 291fbfe7 stp w7, w15, \[sp,#252\] - 18: 29603fe7 ldp w7, w15, \[sp,#-256\] - 1c: 2970bfe7 ldp w7, w15, \[sp,#-124\] - 20: 297fbfe7 ldp w7, w15, \[sp,#-4\] + 10: 2907bfe7 stp w7, w15, \[sp, #60\] + 14: 291fbfe7 stp w7, w15, \[sp, #252\] + 18: 29603fe7 ldp w7, w15, \[sp, #-256\] + 1c: 2970bfe7 ldp w7, w15, \[sp, #-124\] + 20: 297fbfe7 ldp w7, w15, \[sp, #-4\] 24: 29403fe7 ldp w7, w15, \[sp\] - 28: 2947bfe7 ldp w7, w15, \[sp,#60\] - 2c: 295fbfe7 ldp w7, w15, \[sp,#252\] - 30: 69603fe7 ldpsw x7, x15, \[sp,#-256\] - 34: 6970bfe7 ldpsw x7, x15, \[sp,#-124\] - 38: 697fbfe7 ldpsw x7, x15, \[sp,#-4\] + 28: 2947bfe7 ldp w7, w15, \[sp, #60\] + 2c: 295fbfe7 ldp w7, w15, \[sp, #252\] + 30: 69603fe7 ldpsw x7, x15, \[sp, #-256\] + 34: 6970bfe7 ldpsw x7, x15, \[sp, #-124\] + 38: 697fbfe7 ldpsw x7, x15, \[sp, #-4\] 3c: 69403fe7 ldpsw x7, x15, \[sp\] - 40: 6947bfe7 ldpsw x7, x15, \[sp,#60\] - 44: 695fbfe7 ldpsw x7, x15, \[sp,#252\] - 48: a9203fe7 stp x7, x15, \[sp,#-512\] - 4c: a930bfe7 stp x7, x15, \[sp,#-248\] - 50: a93fbfe7 stp x7, x15, \[sp,#-8\] + 40: 6947bfe7 ldpsw x7, x15, \[sp, #60\] + 44: 695fbfe7 ldpsw x7, x15, \[sp, #252\] + 48: a9203fe7 stp x7, x15, \[sp, #-512\] + 4c: a930bfe7 stp x7, x15, \[sp, #-248\] + 50: a93fbfe7 stp x7, x15, \[sp, #-8\] 54: a9003fe7 stp x7, x15, \[sp\] - 58: a907bfe7 stp x7, x15, \[sp,#120\] - 5c: a91fbfe7 stp x7, x15, \[sp,#504\] - 60: a9603fe7 ldp x7, x15, \[sp,#-512\] - 64: a970bfe7 ldp x7, x15, \[sp,#-248\] - 68: a97fbfe7 ldp x7, x15, \[sp,#-8\] + 58: a907bfe7 stp x7, x15, \[sp, #120\] + 5c: a91fbfe7 stp x7, x15, \[sp, #504\] + 60: a9603fe7 ldp x7, x15, \[sp, #-512\] + 64: a970bfe7 ldp x7, x15, \[sp, #-248\] + 68: a97fbfe7 ldp x7, x15, \[sp, #-8\] 6c: a9403fe7 ldp x7, x15, \[sp\] - 70: a947bfe7 ldp x7, x15, \[sp,#120\] - 74: a95fbfe7 ldp x7, x15, \[sp,#504\] - 78: 2d203fe7 stp s7, s15, \[sp,#-256\] - 7c: 2d30bfe7 stp s7, s15, \[sp,#-124\] - 80: 2d3fbfe7 stp s7, s15, \[sp,#-4\] + 70: a947bfe7 ldp x7, x15, \[sp, #120\] + 74: a95fbfe7 ldp x7, x15, \[sp, #504\] + 78: 2d203fe7 stp s7, s15, \[sp, #-256\] + 7c: 2d30bfe7 stp s7, s15, \[sp, #-124\] + 80: 2d3fbfe7 stp s7, s15, \[sp, #-4\] 84: 2d003fe7 stp s7, s15, \[sp\] - 88: 2d07bfe7 stp s7, s15, \[sp,#60\] - 8c: 2d1fbfe7 stp s7, s15, \[sp,#252\] - 90: 2d603fe7 ldp s7, s15, \[sp,#-256\] - 94: 2d70bfe7 ldp s7, s15, \[sp,#-124\] - 98: 2d7fbfe7 ldp s7, s15, \[sp,#-4\] + 88: 2d07bfe7 stp s7, s15, \[sp, #60\] + 8c: 2d1fbfe7 stp s7, s15, \[sp, #252\] + 90: 2d603fe7 ldp s7, s15, \[sp, #-256\] + 94: 2d70bfe7 ldp s7, s15, \[sp, #-124\] + 98: 2d7fbfe7 ldp s7, s15, \[sp, #-4\] 9c: 2d403fe7 ldp s7, s15, \[sp\] - a0: 2d47bfe7 ldp s7, s15, \[sp,#60\] - a4: 2d5fbfe7 ldp s7, s15, \[sp,#252\] - a8: 6d203fe7 stp d7, d15, \[sp,#-512\] - ac: 6d30bfe7 stp d7, d15, \[sp,#-248\] - b0: 6d3fbfe7 stp d7, d15, \[sp,#-8\] + a0: 2d47bfe7 ldp s7, s15, \[sp, #60\] + a4: 2d5fbfe7 ldp s7, s15, \[sp, #252\] + a8: 6d203fe7 stp d7, d15, \[sp, #-512\] + ac: 6d30bfe7 stp d7, d15, \[sp, #-248\] + b0: 6d3fbfe7 stp d7, d15, \[sp, #-8\] b4: 6d003fe7 stp d7, d15, \[sp\] - b8: 6d07bfe7 stp d7, d15, \[sp,#120\] - bc: 6d1fbfe7 stp d7, d15, \[sp,#504\] - c0: 6d603fe7 ldp d7, d15, \[sp,#-512\] - c4: 6d70bfe7 ldp d7, d15, \[sp,#-248\] - c8: 6d7fbfe7 ldp d7, d15, \[sp,#-8\] + b8: 6d07bfe7 stp d7, d15, \[sp, #120\] + bc: 6d1fbfe7 stp d7, d15, \[sp, #504\] + c0: 6d603fe7 ldp d7, d15, \[sp, #-512\] + c4: 6d70bfe7 ldp d7, d15, \[sp, #-248\] + c8: 6d7fbfe7 ldp d7, d15, \[sp, #-8\] cc: 6d403fe7 ldp d7, d15, \[sp\] - d0: 6d47bfe7 ldp d7, d15, \[sp,#120\] - d4: 6d5fbfe7 ldp d7, d15, \[sp,#504\] - d8: ad203fe7 stp q7, q15, \[sp,#-1024\] - dc: ad30bfe7 stp q7, q15, \[sp,#-496\] - e0: ad3fbfe7 stp q7, q15, \[sp,#-16\] + d0: 6d47bfe7 ldp d7, d15, \[sp, #120\] + d4: 6d5fbfe7 ldp d7, d15, \[sp, #504\] + d8: ad203fe7 stp q7, q15, \[sp, #-1024\] + dc: ad30bfe7 stp q7, q15, \[sp, #-496\] + e0: ad3fbfe7 stp q7, q15, \[sp, #-16\] e4: ad003fe7 stp q7, q15, \[sp\] - e8: ad07bfe7 stp q7, q15, \[sp,#240\] - ec: ad1fbfe7 stp q7, q15, \[sp,#1008\] - f0: ad603fe7 ldp q7, q15, \[sp,#-1024\] - f4: ad70bfe7 ldp q7, q15, \[sp,#-496\] - f8: ad7fbfe7 ldp q7, q15, \[sp,#-16\] + e8: ad07bfe7 stp q7, q15, \[sp, #240\] + ec: ad1fbfe7 stp q7, q15, \[sp, #1008\] + f0: ad603fe7 ldp q7, q15, \[sp, #-1024\] + f4: ad70bfe7 ldp q7, q15, \[sp, #-496\] + f8: ad7fbfe7 ldp q7, q15, \[sp, #-16\] fc: ad403fe7 ldp q7, q15, \[sp\] - 100: ad47bfe7 ldp q7, q15, \[sp,#240\] - 104: ad5fbfe7 ldp q7, q15, \[sp,#1008\] - 108: 28a03fe7 stp w7, w15, \[sp\],#-256 - 10c: 28b0bfe7 stp w7, w15, \[sp\],#-124 - 110: 28bfbfe7 stp w7, w15, \[sp\],#-4 - 114: 28803fe7 stp w7, w15, \[sp\],#0 - 118: 2887bfe7 stp w7, w15, \[sp\],#60 - 11c: 289fbfe7 stp w7, w15, \[sp\],#252 - 120: 28e03fe7 ldp w7, w15, \[sp\],#-256 - 124: 28f0bfe7 ldp w7, w15, \[sp\],#-124 - 128: 28ffbfe7 ldp w7, w15, \[sp\],#-4 - 12c: 28c03fe7 ldp w7, w15, \[sp\],#0 - 130: 28c7bfe7 ldp w7, w15, \[sp\],#60 - 134: 28dfbfe7 ldp w7, w15, \[sp\],#252 - 138: 68e03fe7 ldpsw x7, x15, \[sp\],#-256 - 13c: 68f0bfe7 ldpsw x7, x15, \[sp\],#-124 - 140: 68ffbfe7 ldpsw x7, x15, \[sp\],#-4 - 144: 68c03fe7 ldpsw x7, x15, \[sp\],#0 - 148: 68c7bfe7 ldpsw x7, x15, \[sp\],#60 - 14c: 68dfbfe7 ldpsw x7, x15, \[sp\],#252 - 150: a8a03fe7 stp x7, x15, \[sp\],#-512 - 154: a8b0bfe7 stp x7, x15, \[sp\],#-248 - 158: a8bfbfe7 stp x7, x15, \[sp\],#-8 - 15c: a8803fe7 stp x7, x15, \[sp\],#0 - 160: a887bfe7 stp x7, x15, \[sp\],#120 - 164: a89fbfe7 stp x7, x15, \[sp\],#504 - 168: a8e03fe7 ldp x7, x15, \[sp\],#-512 - 16c: a8f0bfe7 ldp x7, x15, \[sp\],#-248 - 170: a8ffbfe7 ldp x7, x15, \[sp\],#-8 - 174: a8c03fe7 ldp x7, x15, \[sp\],#0 - 178: a8c7bfe7 ldp x7, x15, \[sp\],#120 - 17c: a8dfbfe7 ldp x7, x15, \[sp\],#504 - 180: 2ca03fe7 stp s7, s15, \[sp\],#-256 - 184: 2cb0bfe7 stp s7, s15, \[sp\],#-124 - 188: 2cbfbfe7 stp s7, s15, \[sp\],#-4 - 18c: 2c803fe7 stp s7, s15, \[sp\],#0 - 190: 2c87bfe7 stp s7, s15, \[sp\],#60 - 194: 2c9fbfe7 stp s7, s15, \[sp\],#252 - 198: 2ce03fe7 ldp s7, s15, \[sp\],#-256 - 19c: 2cf0bfe7 ldp s7, s15, \[sp\],#-124 - 1a0: 2cffbfe7 ldp s7, s15, \[sp\],#-4 - 1a4: 2cc03fe7 ldp s7, s15, \[sp\],#0 - 1a8: 2cc7bfe7 ldp s7, s15, \[sp\],#60 - 1ac: 2cdfbfe7 ldp s7, s15, \[sp\],#252 - 1b0: 6ca03fe7 stp d7, d15, \[sp\],#-512 - 1b4: 6cb0bfe7 stp d7, d15, \[sp\],#-248 - 1b8: 6cbfbfe7 stp d7, d15, \[sp\],#-8 - 1bc: 6c803fe7 stp d7, d15, \[sp\],#0 - 1c0: 6c87bfe7 stp d7, d15, \[sp\],#120 - 1c4: 6c9fbfe7 stp d7, d15, \[sp\],#504 - 1c8: 6ce03fe7 ldp d7, d15, \[sp\],#-512 - 1cc: 6cf0bfe7 ldp d7, d15, \[sp\],#-248 - 1d0: 6cffbfe7 ldp d7, d15, \[sp\],#-8 - 1d4: 6cc03fe7 ldp d7, d15, \[sp\],#0 - 1d8: 6cc7bfe7 ldp d7, d15, \[sp\],#120 - 1dc: 6cdfbfe7 ldp d7, d15, \[sp\],#504 - 1e0: aca03fe7 stp q7, q15, \[sp\],#-1024 - 1e4: acb0bfe7 stp q7, q15, \[sp\],#-496 - 1e8: acbfbfe7 stp q7, q15, \[sp\],#-16 - 1ec: ac803fe7 stp q7, q15, \[sp\],#0 - 1f0: ac87bfe7 stp q7, q15, \[sp\],#240 - 1f4: ac9fbfe7 stp q7, q15, \[sp\],#1008 - 1f8: ace03fe7 ldp q7, q15, \[sp\],#-1024 - 1fc: acf0bfe7 ldp q7, q15, \[sp\],#-496 - 200: acffbfe7 ldp q7, q15, \[sp\],#-16 - 204: acc03fe7 ldp q7, q15, \[sp\],#0 - 208: acc7bfe7 ldp q7, q15, \[sp\],#240 - 20c: acdfbfe7 ldp q7, q15, \[sp\],#1008 - 210: 29a03fe7 stp w7, w15, \[sp,#-256\]! - 214: 29b0bfe7 stp w7, w15, \[sp,#-124\]! - 218: 29bfbfe7 stp w7, w15, \[sp,#-4\]! - 21c: 29803fe7 stp w7, w15, \[sp,#0\]! - 220: 2987bfe7 stp w7, w15, \[sp,#60\]! - 224: 299fbfe7 stp w7, w15, \[sp,#252\]! - 228: 29e03fe7 ldp w7, w15, \[sp,#-256\]! - 22c: 29f0bfe7 ldp w7, w15, \[sp,#-124\]! - 230: 29ffbfe7 ldp w7, w15, \[sp,#-4\]! - 234: 29c03fe7 ldp w7, w15, \[sp,#0\]! - 238: 29c7bfe7 ldp w7, w15, \[sp,#60\]! - 23c: 29dfbfe7 ldp w7, w15, \[sp,#252\]! - 240: 69e03fe7 ldpsw x7, x15, \[sp,#-256\]! - 244: 69f0bfe7 ldpsw x7, x15, \[sp,#-124\]! - 248: 69ffbfe7 ldpsw x7, x15, \[sp,#-4\]! - 24c: 69c03fe7 ldpsw x7, x15, \[sp,#0\]! - 250: 69c7bfe7 ldpsw x7, x15, \[sp,#60\]! - 254: 69dfbfe7 ldpsw x7, x15, \[sp,#252\]! - 258: a9a03fe7 stp x7, x15, \[sp,#-512\]! - 25c: a9b0bfe7 stp x7, x15, \[sp,#-248\]! - 260: a9bfbfe7 stp x7, x15, \[sp,#-8\]! - 264: a9803fe7 stp x7, x15, \[sp,#0\]! - 268: a987bfe7 stp x7, x15, \[sp,#120\]! - 26c: a99fbfe7 stp x7, x15, \[sp,#504\]! - 270: a9e03fe7 ldp x7, x15, \[sp,#-512\]! - 274: a9f0bfe7 ldp x7, x15, \[sp,#-248\]! - 278: a9ffbfe7 ldp x7, x15, \[sp,#-8\]! - 27c: a9c03fe7 ldp x7, x15, \[sp,#0\]! - 280: a9c7bfe7 ldp x7, x15, \[sp,#120\]! - 284: a9dfbfe7 ldp x7, x15, \[sp,#504\]! - 288: 2da03fe7 stp s7, s15, \[sp,#-256\]! - 28c: 2db0bfe7 stp s7, s15, \[sp,#-124\]! - 290: 2dbfbfe7 stp s7, s15, \[sp,#-4\]! - 294: 2d803fe7 stp s7, s15, \[sp,#0\]! - 298: 2d87bfe7 stp s7, s15, \[sp,#60\]! - 29c: 2d9fbfe7 stp s7, s15, \[sp,#252\]! - 2a0: 2de03fe7 ldp s7, s15, \[sp,#-256\]! - 2a4: 2df0bfe7 ldp s7, s15, \[sp,#-124\]! - 2a8: 2dffbfe7 ldp s7, s15, \[sp,#-4\]! - 2ac: 2dc03fe7 ldp s7, s15, \[sp,#0\]! - 2b0: 2dc7bfe7 ldp s7, s15, \[sp,#60\]! - 2b4: 2ddfbfe7 ldp s7, s15, \[sp,#252\]! - 2b8: 6da03fe7 stp d7, d15, \[sp,#-512\]! - 2bc: 6db0bfe7 stp d7, d15, \[sp,#-248\]! - 2c0: 6dbfbfe7 stp d7, d15, \[sp,#-8\]! - 2c4: 6d803fe7 stp d7, d15, \[sp,#0\]! - 2c8: 6d87bfe7 stp d7, d15, \[sp,#120\]! - 2cc: 6d9fbfe7 stp d7, d15, \[sp,#504\]! - 2d0: 6de03fe7 ldp d7, d15, \[sp,#-512\]! - 2d4: 6df0bfe7 ldp d7, d15, \[sp,#-248\]! - 2d8: 6dffbfe7 ldp d7, d15, \[sp,#-8\]! - 2dc: 6dc03fe7 ldp d7, d15, \[sp,#0\]! - 2e0: 6dc7bfe7 ldp d7, d15, \[sp,#120\]! - 2e4: 6ddfbfe7 ldp d7, d15, \[sp,#504\]! - 2e8: ada03fe7 stp q7, q15, \[sp,#-1024\]! - 2ec: adb0bfe7 stp q7, q15, \[sp,#-496\]! - 2f0: adbfbfe7 stp q7, q15, \[sp,#-16\]! - 2f4: ad803fe7 stp q7, q15, \[sp,#0\]! - 2f8: ad87bfe7 stp q7, q15, \[sp,#240\]! - 2fc: ad9fbfe7 stp q7, q15, \[sp,#1008\]! - 300: ade03fe7 ldp q7, q15, \[sp,#-1024\]! - 304: adf0bfe7 ldp q7, q15, \[sp,#-496\]! - 308: adffbfe7 ldp q7, q15, \[sp,#-16\]! - 30c: adc03fe7 ldp q7, q15, \[sp,#0\]! - 310: adc7bfe7 ldp q7, q15, \[sp,#240\]! - 314: addfbfe7 ldp q7, q15, \[sp,#1008\]! - 318: 28203fe7 stnp w7, w15, \[sp,#-256\] - 31c: 2830bfe7 stnp w7, w15, \[sp,#-124\] - 320: 283fbfe7 stnp w7, w15, \[sp,#-4\] + 100: ad47bfe7 ldp q7, q15, \[sp, #240\] + 104: ad5fbfe7 ldp q7, q15, \[sp, #1008\] + 108: 28a03fe7 stp w7, w15, \[sp\], #-256 + 10c: 28b0bfe7 stp w7, w15, \[sp\], #-124 + 110: 28bfbfe7 stp w7, w15, \[sp\], #-4 + 114: 28803fe7 stp w7, w15, \[sp\], #0 + 118: 2887bfe7 stp w7, w15, \[sp\], #60 + 11c: 289fbfe7 stp w7, w15, \[sp\], #252 + 120: 28e03fe7 ldp w7, w15, \[sp\], #-256 + 124: 28f0bfe7 ldp w7, w15, \[sp\], #-124 + 128: 28ffbfe7 ldp w7, w15, \[sp\], #-4 + 12c: 28c03fe7 ldp w7, w15, \[sp\], #0 + 130: 28c7bfe7 ldp w7, w15, \[sp\], #60 + 134: 28dfbfe7 ldp w7, w15, \[sp\], #252 + 138: 68e03fe7 ldpsw x7, x15, \[sp\], #-256 + 13c: 68f0bfe7 ldpsw x7, x15, \[sp\], #-124 + 140: 68ffbfe7 ldpsw x7, x15, \[sp\], #-4 + 144: 68c03fe7 ldpsw x7, x15, \[sp\], #0 + 148: 68c7bfe7 ldpsw x7, x15, \[sp\], #60 + 14c: 68dfbfe7 ldpsw x7, x15, \[sp\], #252 + 150: a8a03fe7 stp x7, x15, \[sp\], #-512 + 154: a8b0bfe7 stp x7, x15, \[sp\], #-248 + 158: a8bfbfe7 stp x7, x15, \[sp\], #-8 + 15c: a8803fe7 stp x7, x15, \[sp\], #0 + 160: a887bfe7 stp x7, x15, \[sp\], #120 + 164: a89fbfe7 stp x7, x15, \[sp\], #504 + 168: a8e03fe7 ldp x7, x15, \[sp\], #-512 + 16c: a8f0bfe7 ldp x7, x15, \[sp\], #-248 + 170: a8ffbfe7 ldp x7, x15, \[sp\], #-8 + 174: a8c03fe7 ldp x7, x15, \[sp\], #0 + 178: a8c7bfe7 ldp x7, x15, \[sp\], #120 + 17c: a8dfbfe7 ldp x7, x15, \[sp\], #504 + 180: 2ca03fe7 stp s7, s15, \[sp\], #-256 + 184: 2cb0bfe7 stp s7, s15, \[sp\], #-124 + 188: 2cbfbfe7 stp s7, s15, \[sp\], #-4 + 18c: 2c803fe7 stp s7, s15, \[sp\], #0 + 190: 2c87bfe7 stp s7, s15, \[sp\], #60 + 194: 2c9fbfe7 stp s7, s15, \[sp\], #252 + 198: 2ce03fe7 ldp s7, s15, \[sp\], #-256 + 19c: 2cf0bfe7 ldp s7, s15, \[sp\], #-124 + 1a0: 2cffbfe7 ldp s7, s15, \[sp\], #-4 + 1a4: 2cc03fe7 ldp s7, s15, \[sp\], #0 + 1a8: 2cc7bfe7 ldp s7, s15, \[sp\], #60 + 1ac: 2cdfbfe7 ldp s7, s15, \[sp\], #252 + 1b0: 6ca03fe7 stp d7, d15, \[sp\], #-512 + 1b4: 6cb0bfe7 stp d7, d15, \[sp\], #-248 + 1b8: 6cbfbfe7 stp d7, d15, \[sp\], #-8 + 1bc: 6c803fe7 stp d7, d15, \[sp\], #0 + 1c0: 6c87bfe7 stp d7, d15, \[sp\], #120 + 1c4: 6c9fbfe7 stp d7, d15, \[sp\], #504 + 1c8: 6ce03fe7 ldp d7, d15, \[sp\], #-512 + 1cc: 6cf0bfe7 ldp d7, d15, \[sp\], #-248 + 1d0: 6cffbfe7 ldp d7, d15, \[sp\], #-8 + 1d4: 6cc03fe7 ldp d7, d15, \[sp\], #0 + 1d8: 6cc7bfe7 ldp d7, d15, \[sp\], #120 + 1dc: 6cdfbfe7 ldp d7, d15, \[sp\], #504 + 1e0: aca03fe7 stp q7, q15, \[sp\], #-1024 + 1e4: acb0bfe7 stp q7, q15, \[sp\], #-496 + 1e8: acbfbfe7 stp q7, q15, \[sp\], #-16 + 1ec: ac803fe7 stp q7, q15, \[sp\], #0 + 1f0: ac87bfe7 stp q7, q15, \[sp\], #240 + 1f4: ac9fbfe7 stp q7, q15, \[sp\], #1008 + 1f8: ace03fe7 ldp q7, q15, \[sp\], #-1024 + 1fc: acf0bfe7 ldp q7, q15, \[sp\], #-496 + 200: acffbfe7 ldp q7, q15, \[sp\], #-16 + 204: acc03fe7 ldp q7, q15, \[sp\], #0 + 208: acc7bfe7 ldp q7, q15, \[sp\], #240 + 20c: acdfbfe7 ldp q7, q15, \[sp\], #1008 + 210: 29a03fe7 stp w7, w15, \[sp, #-256\]! + 214: 29b0bfe7 stp w7, w15, \[sp, #-124\]! + 218: 29bfbfe7 stp w7, w15, \[sp, #-4\]! + 21c: 29803fe7 stp w7, w15, \[sp, #0\]! + 220: 2987bfe7 stp w7, w15, \[sp, #60\]! + 224: 299fbfe7 stp w7, w15, \[sp, #252\]! + 228: 29e03fe7 ldp w7, w15, \[sp, #-256\]! + 22c: 29f0bfe7 ldp w7, w15, \[sp, #-124\]! + 230: 29ffbfe7 ldp w7, w15, \[sp, #-4\]! + 234: 29c03fe7 ldp w7, w15, \[sp, #0\]! + 238: 29c7bfe7 ldp w7, w15, \[sp, #60\]! + 23c: 29dfbfe7 ldp w7, w15, \[sp, #252\]! + 240: 69e03fe7 ldpsw x7, x15, \[sp, #-256\]! + 244: 69f0bfe7 ldpsw x7, x15, \[sp, #-124\]! + 248: 69ffbfe7 ldpsw x7, x15, \[sp, #-4\]! + 24c: 69c03fe7 ldpsw x7, x15, \[sp, #0\]! + 250: 69c7bfe7 ldpsw x7, x15, \[sp, #60\]! + 254: 69dfbfe7 ldpsw x7, x15, \[sp, #252\]! + 258: a9a03fe7 stp x7, x15, \[sp, #-512\]! + 25c: a9b0bfe7 stp x7, x15, \[sp, #-248\]! + 260: a9bfbfe7 stp x7, x15, \[sp, #-8\]! + 264: a9803fe7 stp x7, x15, \[sp, #0\]! + 268: a987bfe7 stp x7, x15, \[sp, #120\]! + 26c: a99fbfe7 stp x7, x15, \[sp, #504\]! + 270: a9e03fe7 ldp x7, x15, \[sp, #-512\]! + 274: a9f0bfe7 ldp x7, x15, \[sp, #-248\]! + 278: a9ffbfe7 ldp x7, x15, \[sp, #-8\]! + 27c: a9c03fe7 ldp x7, x15, \[sp, #0\]! + 280: a9c7bfe7 ldp x7, x15, \[sp, #120\]! + 284: a9dfbfe7 ldp x7, x15, \[sp, #504\]! + 288: 2da03fe7 stp s7, s15, \[sp, #-256\]! + 28c: 2db0bfe7 stp s7, s15, \[sp, #-124\]! + 290: 2dbfbfe7 stp s7, s15, \[sp, #-4\]! + 294: 2d803fe7 stp s7, s15, \[sp, #0\]! + 298: 2d87bfe7 stp s7, s15, \[sp, #60\]! + 29c: 2d9fbfe7 stp s7, s15, \[sp, #252\]! + 2a0: 2de03fe7 ldp s7, s15, \[sp, #-256\]! + 2a4: 2df0bfe7 ldp s7, s15, \[sp, #-124\]! + 2a8: 2dffbfe7 ldp s7, s15, \[sp, #-4\]! + 2ac: 2dc03fe7 ldp s7, s15, \[sp, #0\]! + 2b0: 2dc7bfe7 ldp s7, s15, \[sp, #60\]! + 2b4: 2ddfbfe7 ldp s7, s15, \[sp, #252\]! + 2b8: 6da03fe7 stp d7, d15, \[sp, #-512\]! + 2bc: 6db0bfe7 stp d7, d15, \[sp, #-248\]! + 2c0: 6dbfbfe7 stp d7, d15, \[sp, #-8\]! + 2c4: 6d803fe7 stp d7, d15, \[sp, #0\]! + 2c8: 6d87bfe7 stp d7, d15, \[sp, #120\]! + 2cc: 6d9fbfe7 stp d7, d15, \[sp, #504\]! + 2d0: 6de03fe7 ldp d7, d15, \[sp, #-512\]! + 2d4: 6df0bfe7 ldp d7, d15, \[sp, #-248\]! + 2d8: 6dffbfe7 ldp d7, d15, \[sp, #-8\]! + 2dc: 6dc03fe7 ldp d7, d15, \[sp, #0\]! + 2e0: 6dc7bfe7 ldp d7, d15, \[sp, #120\]! + 2e4: 6ddfbfe7 ldp d7, d15, \[sp, #504\]! + 2e8: ada03fe7 stp q7, q15, \[sp, #-1024\]! + 2ec: adb0bfe7 stp q7, q15, \[sp, #-496\]! + 2f0: adbfbfe7 stp q7, q15, \[sp, #-16\]! + 2f4: ad803fe7 stp q7, q15, \[sp, #0\]! + 2f8: ad87bfe7 stp q7, q15, \[sp, #240\]! + 2fc: ad9fbfe7 stp q7, q15, \[sp, #1008\]! + 300: ade03fe7 ldp q7, q15, \[sp, #-1024\]! + 304: adf0bfe7 ldp q7, q15, \[sp, #-496\]! + 308: adffbfe7 ldp q7, q15, \[sp, #-16\]! + 30c: adc03fe7 ldp q7, q15, \[sp, #0\]! + 310: adc7bfe7 ldp q7, q15, \[sp, #240\]! + 314: addfbfe7 ldp q7, q15, \[sp, #1008\]! + 318: 28203fe7 stnp w7, w15, \[sp, #-256\] + 31c: 2830bfe7 stnp w7, w15, \[sp, #-124\] + 320: 283fbfe7 stnp w7, w15, \[sp, #-4\] 324: 28003fe7 stnp w7, w15, \[sp\] - 328: 2807bfe7 stnp w7, w15, \[sp,#60\] - 32c: 281fbfe7 stnp w7, w15, \[sp,#252\] - 330: 28603fe7 ldnp w7, w15, \[sp,#-256\] - 334: 2870bfe7 ldnp w7, w15, \[sp,#-124\] - 338: 287fbfe7 ldnp w7, w15, \[sp,#-4\] + 328: 2807bfe7 stnp w7, w15, \[sp, #60\] + 32c: 281fbfe7 stnp w7, w15, \[sp, #252\] + 330: 28603fe7 ldnp w7, w15, \[sp, #-256\] + 334: 2870bfe7 ldnp w7, w15, \[sp, #-124\] + 338: 287fbfe7 ldnp w7, w15, \[sp, #-4\] 33c: 28403fe7 ldnp w7, w15, \[sp\] - 340: 2847bfe7 ldnp w7, w15, \[sp,#60\] - 344: 285fbfe7 ldnp w7, w15, \[sp,#252\] - 348: a8203fe7 stnp x7, x15, \[sp,#-512\] - 34c: a830bfe7 stnp x7, x15, \[sp,#-248\] - 350: a83fbfe7 stnp x7, x15, \[sp,#-8\] + 340: 2847bfe7 ldnp w7, w15, \[sp, #60\] + 344: 285fbfe7 ldnp w7, w15, \[sp, #252\] + 348: a8203fe7 stnp x7, x15, \[sp, #-512\] + 34c: a830bfe7 stnp x7, x15, \[sp, #-248\] + 350: a83fbfe7 stnp x7, x15, \[sp, #-8\] 354: a8003fe7 stnp x7, x15, \[sp\] - 358: a807bfe7 stnp x7, x15, \[sp,#120\] - 35c: a81fbfe7 stnp x7, x15, \[sp,#504\] - 360: a8603fe7 ldnp x7, x15, \[sp,#-512\] - 364: a870bfe7 ldnp x7, x15, \[sp,#-248\] - 368: a87fbfe7 ldnp x7, x15, \[sp,#-8\] + 358: a807bfe7 stnp x7, x15, \[sp, #120\] + 35c: a81fbfe7 stnp x7, x15, \[sp, #504\] + 360: a8603fe7 ldnp x7, x15, \[sp, #-512\] + 364: a870bfe7 ldnp x7, x15, \[sp, #-248\] + 368: a87fbfe7 ldnp x7, x15, \[sp, #-8\] 36c: a8403fe7 ldnp x7, x15, \[sp\] - 370: a847bfe7 ldnp x7, x15, \[sp,#120\] - 374: a85fbfe7 ldnp x7, x15, \[sp,#504\] - 378: 2c203fe7 stnp s7, s15, \[sp,#-256\] - 37c: 2c30bfe7 stnp s7, s15, \[sp,#-124\] - 380: 2c3fbfe7 stnp s7, s15, \[sp,#-4\] + 370: a847bfe7 ldnp x7, x15, \[sp, #120\] + 374: a85fbfe7 ldnp x7, x15, \[sp, #504\] + 378: 2c203fe7 stnp s7, s15, \[sp, #-256\] + 37c: 2c30bfe7 stnp s7, s15, \[sp, #-124\] + 380: 2c3fbfe7 stnp s7, s15, \[sp, #-4\] 384: 2c003fe7 stnp s7, s15, \[sp\] - 388: 2c07bfe7 stnp s7, s15, \[sp,#60\] - 38c: 2c1fbfe7 stnp s7, s15, \[sp,#252\] - 390: 2c603fe7 ldnp s7, s15, \[sp,#-256\] - 394: 2c70bfe7 ldnp s7, s15, \[sp,#-124\] - 398: 2c7fbfe7 ldnp s7, s15, \[sp,#-4\] + 388: 2c07bfe7 stnp s7, s15, \[sp, #60\] + 38c: 2c1fbfe7 stnp s7, s15, \[sp, #252\] + 390: 2c603fe7 ldnp s7, s15, \[sp, #-256\] + 394: 2c70bfe7 ldnp s7, s15, \[sp, #-124\] + 398: 2c7fbfe7 ldnp s7, s15, \[sp, #-4\] 39c: 2c403fe7 ldnp s7, s15, \[sp\] - 3a0: 2c47bfe7 ldnp s7, s15, \[sp,#60\] - 3a4: 2c5fbfe7 ldnp s7, s15, \[sp,#252\] - 3a8: 6c203fe7 stnp d7, d15, \[sp,#-512\] - 3ac: 6c30bfe7 stnp d7, d15, \[sp,#-248\] - 3b0: 6c3fbfe7 stnp d7, d15, \[sp,#-8\] + 3a0: 2c47bfe7 ldnp s7, s15, \[sp, #60\] + 3a4: 2c5fbfe7 ldnp s7, s15, \[sp, #252\] + 3a8: 6c203fe7 stnp d7, d15, \[sp, #-512\] + 3ac: 6c30bfe7 stnp d7, d15, \[sp, #-248\] + 3b0: 6c3fbfe7 stnp d7, d15, \[sp, #-8\] 3b4: 6c003fe7 stnp d7, d15, \[sp\] - 3b8: 6c07bfe7 stnp d7, d15, \[sp,#120\] - 3bc: 6c1fbfe7 stnp d7, d15, \[sp,#504\] - 3c0: 6c603fe7 ldnp d7, d15, \[sp,#-512\] - 3c4: 6c70bfe7 ldnp d7, d15, \[sp,#-248\] - 3c8: 6c7fbfe7 ldnp d7, d15, \[sp,#-8\] + 3b8: 6c07bfe7 stnp d7, d15, \[sp, #120\] + 3bc: 6c1fbfe7 stnp d7, d15, \[sp, #504\] + 3c0: 6c603fe7 ldnp d7, d15, \[sp, #-512\] + 3c4: 6c70bfe7 ldnp d7, d15, \[sp, #-248\] + 3c8: 6c7fbfe7 ldnp d7, d15, \[sp, #-8\] 3cc: 6c403fe7 ldnp d7, d15, \[sp\] - 3d0: 6c47bfe7 ldnp d7, d15, \[sp,#120\] - 3d4: 6c5fbfe7 ldnp d7, d15, \[sp,#504\] - 3d8: ac203fe7 stnp q7, q15, \[sp,#-1024\] - 3dc: ac30bfe7 stnp q7, q15, \[sp,#-496\] - 3e0: ac3fbfe7 stnp q7, q15, \[sp,#-16\] + 3d0: 6c47bfe7 ldnp d7, d15, \[sp, #120\] + 3d4: 6c5fbfe7 ldnp d7, d15, \[sp, #504\] + 3d8: ac203fe7 stnp q7, q15, \[sp, #-1024\] + 3dc: ac30bfe7 stnp q7, q15, \[sp, #-496\] + 3e0: ac3fbfe7 stnp q7, q15, \[sp, #-16\] 3e4: ac003fe7 stnp q7, q15, \[sp\] - 3e8: ac07bfe7 stnp q7, q15, \[sp,#240\] - 3ec: ac1fbfe7 stnp q7, q15, \[sp,#1008\] - 3f0: ac603fe7 ldnp q7, q15, \[sp,#-1024\] - 3f4: ac70bfe7 ldnp q7, q15, \[sp,#-496\] - 3f8: ac7fbfe7 ldnp q7, q15, \[sp,#-16\] + 3e8: ac07bfe7 stnp q7, q15, \[sp, #240\] + 3ec: ac1fbfe7 stnp q7, q15, \[sp, #1008\] + 3f0: ac603fe7 ldnp q7, q15, \[sp, #-1024\] + 3f4: ac70bfe7 ldnp q7, q15, \[sp, #-496\] + 3f8: ac7fbfe7 ldnp q7, q15, \[sp, #-16\] 3fc: ac403fe7 ldnp q7, q15, \[sp\] - 400: ac47bfe7 ldnp q7, q15, \[sp,#240\] - 404: ac5fbfe7 ldnp q7, q15, \[sp,#1008\] + 400: ac47bfe7 ldnp q7, q15, \[sp, #240\] + 404: ac5fbfe7 ldnp q7, q15, \[sp, #1008\] diff --git a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d index b720633f19f..bd61f0ee68e 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d @@ -5,87 +5,87 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 3c274be7 str b7, \[sp,w7,uxtw\] - 4: 3c275be7 str b7, \[sp,w7,uxtw #0\] - 8: 7c274be7 str h7, \[sp,w7,uxtw\] - c: 7c275be7 str h7, \[sp,w7,uxtw #1\] - 10: bc274be7 str s7, \[sp,w7,uxtw\] - 14: bc275be7 str s7, \[sp,w7,uxtw #2\] - 18: fc274be7 str d7, \[sp,w7,uxtw\] - 1c: fc275be7 str d7, \[sp,w7,uxtw #3\] - 20: 3ca74be7 str q7, \[sp,w7,uxtw\] - 24: 3ca75be7 str q7, \[sp,w7,uxtw #4\] - 28: 3c276be7 str b7, \[sp,x7\] - 2c: 3c277be7 str b7, \[sp,x7,lsl #0\] - 30: 7c276be7 str h7, \[sp,x7\] - 34: 7c277be7 str h7, \[sp,x7,lsl #1\] - 38: bc276be7 str s7, \[sp,x7\] - 3c: bc277be7 str s7, \[sp,x7,lsl #2\] - 40: fc276be7 str d7, \[sp,x7\] - 44: fc277be7 str d7, \[sp,x7,lsl #3\] - 48: 3ca76be7 str q7, \[sp,x7\] - 4c: 3ca77be7 str q7, \[sp,x7,lsl #4\] - 50: 3c27cbe7 str b7, \[sp,w7,sxtw\] - 54: 3c27dbe7 str b7, \[sp,w7,sxtw #0\] - 58: 7c27cbe7 str h7, \[sp,w7,sxtw\] - 5c: 7c27dbe7 str h7, \[sp,w7,sxtw #1\] - 60: bc27cbe7 str s7, \[sp,w7,sxtw\] - 64: bc27dbe7 str s7, \[sp,w7,sxtw #2\] - 68: fc27cbe7 str d7, \[sp,w7,sxtw\] - 6c: fc27dbe7 str d7, \[sp,w7,sxtw #3\] - 70: 3ca7cbe7 str q7, \[sp,w7,sxtw\] - 74: 3ca7dbe7 str q7, \[sp,w7,sxtw #4\] - 78: 3c27ebe7 str b7, \[sp,x7,sxtx\] - 7c: 3c27fbe7 str b7, \[sp,x7,sxtx #0\] - 80: 7c27ebe7 str h7, \[sp,x7,sxtx\] - 84: 7c27fbe7 str h7, \[sp,x7,sxtx #1\] - 88: bc27ebe7 str s7, \[sp,x7,sxtx\] - 8c: bc27fbe7 str s7, \[sp,x7,sxtx #2\] - 90: fc27ebe7 str d7, \[sp,x7,sxtx\] - 94: fc27fbe7 str d7, \[sp,x7,sxtx #3\] - 98: 3ca7ebe7 str q7, \[sp,x7,sxtx\] - 9c: 3ca7fbe7 str q7, \[sp,x7,sxtx #4\] - a0: 3c674be7 ldr b7, \[sp,w7,uxtw\] - a4: 3c675be7 ldr b7, \[sp,w7,uxtw #0\] - a8: 7c674be7 ldr h7, \[sp,w7,uxtw\] - ac: 7c675be7 ldr h7, \[sp,w7,uxtw #1\] - b0: bc674be7 ldr s7, \[sp,w7,uxtw\] - b4: bc675be7 ldr s7, \[sp,w7,uxtw #2\] - b8: fc674be7 ldr d7, \[sp,w7,uxtw\] - bc: fc675be7 ldr d7, \[sp,w7,uxtw #3\] - c0: 3ce74be7 ldr q7, \[sp,w7,uxtw\] - c4: 3ce75be7 ldr q7, \[sp,w7,uxtw #4\] - c8: 3c676be7 ldr b7, \[sp,x7\] - cc: 3c677be7 ldr b7, \[sp,x7,lsl #0\] - d0: 7c676be7 ldr h7, \[sp,x7\] - d4: 7c677be7 ldr h7, \[sp,x7,lsl #1\] - d8: bc676be7 ldr s7, \[sp,x7\] - dc: bc677be7 ldr s7, \[sp,x7,lsl #2\] - e0: fc676be7 ldr d7, \[sp,x7\] - e4: fc677be7 ldr d7, \[sp,x7,lsl #3\] - e8: 3ce76be7 ldr q7, \[sp,x7\] - ec: 3ce77be7 ldr q7, \[sp,x7,lsl #4\] - f0: 3c67cbe7 ldr b7, \[sp,w7,sxtw\] - f4: 3c67dbe7 ldr b7, \[sp,w7,sxtw #0\] - f8: 7c67cbe7 ldr h7, \[sp,w7,sxtw\] - fc: 7c67dbe7 ldr h7, \[sp,w7,sxtw #1\] - 100: bc67cbe7 ldr s7, \[sp,w7,sxtw\] - 104: bc67dbe7 ldr s7, \[sp,w7,sxtw #2\] - 108: fc67cbe7 ldr d7, \[sp,w7,sxtw\] - 10c: fc67dbe7 ldr d7, \[sp,w7,sxtw #3\] - 110: 3ce7cbe7 ldr q7, \[sp,w7,sxtw\] - 114: 3ce7dbe7 ldr q7, \[sp,w7,sxtw #4\] - 118: 3c67ebe7 ldr b7, \[sp,x7,sxtx\] - 11c: 3c67fbe7 ldr b7, \[sp,x7,sxtx #0\] - 120: 7c67ebe7 ldr h7, \[sp,x7,sxtx\] - 124: 7c67fbe7 ldr h7, \[sp,x7,sxtx #1\] - 128: bc67ebe7 ldr s7, \[sp,x7,sxtx\] - 12c: bc67fbe7 ldr s7, \[sp,x7,sxtx #2\] - 130: fc67ebe7 ldr d7, \[sp,x7,sxtx\] - 134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\] - 138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\] - 13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\] - 140: f87ffbe1 ldr x1, \[sp,xzr,sxtx #3\] - 144: f83ffbe1 str x1, \[sp,xzr,sxtx #3\] - 148: b87fdbe1 ldr w1, \[sp,wzr,sxtw #2\] - 14c: b83fdbe1 str w1, \[sp,wzr,sxtw #2\] + 0: 3c274be7 str b7, \[sp, w7, uxtw\] + 4: 3c275be7 str b7, \[sp, w7, uxtw #0\] + 8: 7c274be7 str h7, \[sp, w7, uxtw\] + c: 7c275be7 str h7, \[sp, w7, uxtw #1\] + 10: bc274be7 str s7, \[sp, w7, uxtw\] + 14: bc275be7 str s7, \[sp, w7, uxtw #2\] + 18: fc274be7 str d7, \[sp, w7, uxtw\] + 1c: fc275be7 str d7, \[sp, w7, uxtw #3\] + 20: 3ca74be7 str q7, \[sp, w7, uxtw\] + 24: 3ca75be7 str q7, \[sp, w7, uxtw #4\] + 28: 3c276be7 str b7, \[sp, x7\] + 2c: 3c277be7 str b7, \[sp, x7, lsl #0\] + 30: 7c276be7 str h7, \[sp, x7\] + 34: 7c277be7 str h7, \[sp, x7, lsl #1\] + 38: bc276be7 str s7, \[sp, x7\] + 3c: bc277be7 str s7, \[sp, x7, lsl #2\] + 40: fc276be7 str d7, \[sp, x7\] + 44: fc277be7 str d7, \[sp, x7, lsl #3\] + 48: 3ca76be7 str q7, \[sp, x7\] + 4c: 3ca77be7 str q7, \[sp, x7, lsl #4\] + 50: 3c27cbe7 str b7, \[sp, w7, sxtw\] + 54: 3c27dbe7 str b7, \[sp, w7, sxtw #0\] + 58: 7c27cbe7 str h7, \[sp, w7, sxtw\] + 5c: 7c27dbe7 str h7, \[sp, w7, sxtw #1\] + 60: bc27cbe7 str s7, \[sp, w7, sxtw\] + 64: bc27dbe7 str s7, \[sp, w7, sxtw #2\] + 68: fc27cbe7 str d7, \[sp, w7, sxtw\] + 6c: fc27dbe7 str d7, \[sp, w7, sxtw #3\] + 70: 3ca7cbe7 str q7, \[sp, w7, sxtw\] + 74: 3ca7dbe7 str q7, \[sp, w7, sxtw #4\] + 78: 3c27ebe7 str b7, \[sp, x7, sxtx\] + 7c: 3c27fbe7 str b7, \[sp, x7, sxtx #0\] + 80: 7c27ebe7 str h7, \[sp, x7, sxtx\] + 84: 7c27fbe7 str h7, \[sp, x7, sxtx #1\] + 88: bc27ebe7 str s7, \[sp, x7, sxtx\] + 8c: bc27fbe7 str s7, \[sp, x7, sxtx #2\] + 90: fc27ebe7 str d7, \[sp, x7, sxtx\] + 94: fc27fbe7 str d7, \[sp, x7, sxtx #3\] + 98: 3ca7ebe7 str q7, \[sp, x7, sxtx\] + 9c: 3ca7fbe7 str q7, \[sp, x7, sxtx #4\] + a0: 3c674be7 ldr b7, \[sp, w7, uxtw\] + a4: 3c675be7 ldr b7, \[sp, w7, uxtw #0\] + a8: 7c674be7 ldr h7, \[sp, w7, uxtw\] + ac: 7c675be7 ldr h7, \[sp, w7, uxtw #1\] + b0: bc674be7 ldr s7, \[sp, w7, uxtw\] + b4: bc675be7 ldr s7, \[sp, w7, uxtw #2\] + b8: fc674be7 ldr d7, \[sp, w7, uxtw\] + bc: fc675be7 ldr d7, \[sp, w7, uxtw #3\] + c0: 3ce74be7 ldr q7, \[sp, w7, uxtw\] + c4: 3ce75be7 ldr q7, \[sp, w7, uxtw #4\] + c8: 3c676be7 ldr b7, \[sp, x7\] + cc: 3c677be7 ldr b7, \[sp, x7, lsl #0\] + d0: 7c676be7 ldr h7, \[sp, x7\] + d4: 7c677be7 ldr h7, \[sp, x7, lsl #1\] + d8: bc676be7 ldr s7, \[sp, x7\] + dc: bc677be7 ldr s7, \[sp, x7, lsl #2\] + e0: fc676be7 ldr d7, \[sp, x7\] + e4: fc677be7 ldr d7, \[sp, x7, lsl #3\] + e8: 3ce76be7 ldr q7, \[sp, x7\] + ec: 3ce77be7 ldr q7, \[sp, x7, lsl #4\] + f0: 3c67cbe7 ldr b7, \[sp, w7, sxtw\] + f4: 3c67dbe7 ldr b7, \[sp, w7, sxtw #0\] + f8: 7c67cbe7 ldr h7, \[sp, w7, sxtw\] + fc: 7c67dbe7 ldr h7, \[sp, w7, sxtw #1\] + 100: bc67cbe7 ldr s7, \[sp, w7, sxtw\] + 104: bc67dbe7 ldr s7, \[sp, w7, sxtw #2\] + 108: fc67cbe7 ldr d7, \[sp, w7, sxtw\] + 10c: fc67dbe7 ldr d7, \[sp, w7, sxtw #3\] + 110: 3ce7cbe7 ldr q7, \[sp, w7, sxtw\] + 114: 3ce7dbe7 ldr q7, \[sp, w7, sxtw #4\] + 118: 3c67ebe7 ldr b7, \[sp, x7, sxtx\] + 11c: 3c67fbe7 ldr b7, \[sp, x7, sxtx #0\] + 120: 7c67ebe7 ldr h7, \[sp, x7, sxtx\] + 124: 7c67fbe7 ldr h7, \[sp, x7, sxtx #1\] + 128: bc67ebe7 ldr s7, \[sp, x7, sxtx\] + 12c: bc67fbe7 ldr s7, \[sp, x7, sxtx #2\] + 130: fc67ebe7 ldr d7, \[sp, x7, sxtx\] + 134: fc67fbe7 ldr d7, \[sp, x7, sxtx #3\] + 138: 3ce7ebe7 ldr q7, \[sp, x7, sxtx\] + 13c: 3ce7fbe7 ldr q7, \[sp, x7, sxtx #4\] + 140: f87ffbe1 ldr x1, \[sp, xzr, sxtx #3\] + 144: f83ffbe1 str x1, \[sp, xzr, sxtx #3\] + 148: b87fdbe1 ldr w1, \[sp, wzr, sxtw #2\] + 14c: b83fdbe1 str w1, \[sp, wzr, sxtw #2\] diff --git a/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d b/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d index be9fd605fcf..0b78932cde6 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d @@ -5,256 +5,256 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 3c1003e7 stur b7, \[sp,#-256\] - 4: 3c1553e7 stur b7, \[sp,#-171\] + 0: 3c1003e7 stur b7, \[sp, #-256\] + 4: 3c1553e7 stur b7, \[sp, #-171\] 8: 3d0003e7 str b7, \[sp\] c: 3d0003e7 str b7, \[sp\] - 10: 3d000be7 str b7, \[sp,#2\] - 14: 3d0013e7 str b7, \[sp,#4\] - 18: 3d0023e7 str b7, \[sp,#8\] - 1c: 3d0043e7 str b7, \[sp,#16\] - 20: 3d0157e7 str b7, \[sp,#85\] - 24: 3d03ffe7 str b7, \[sp,#255\] - 28: 3d3fffe7 str b7, \[sp,#4095\] - 2c: 7c1003e7 stur h7, \[sp,#-256\] - 30: 7c1553e7 stur h7, \[sp,#-171\] + 10: 3d000be7 str b7, \[sp, #2\] + 14: 3d0013e7 str b7, \[sp, #4\] + 18: 3d0023e7 str b7, \[sp, #8\] + 1c: 3d0043e7 str b7, \[sp, #16\] + 20: 3d0157e7 str b7, \[sp, #85\] + 24: 3d03ffe7 str b7, \[sp, #255\] + 28: 3d3fffe7 str b7, \[sp, #4095\] + 2c: 7c1003e7 stur h7, \[sp, #-256\] + 30: 7c1553e7 stur h7, \[sp, #-171\] 34: 7d0003e7 str h7, \[sp\] 38: 7d0003e7 str h7, \[sp\] - 3c: 7d0007e7 str h7, \[sp,#2\] - 40: 7d000be7 str h7, \[sp,#4\] - 44: 7d0013e7 str h7, \[sp,#8\] - 48: 7d0023e7 str h7, \[sp,#16\] - 4c: 7c0553e7 stur h7, \[sp,#85\] - 50: 7c0ff3e7 stur h7, \[sp,#255\] - 54: 7d3fffe7 str h7, \[sp,#8190\] - 58: bc1003e7 stur s7, \[sp,#-256\] - 5c: bc1553e7 stur s7, \[sp,#-171\] + 3c: 7d0007e7 str h7, \[sp, #2\] + 40: 7d000be7 str h7, \[sp, #4\] + 44: 7d0013e7 str h7, \[sp, #8\] + 48: 7d0023e7 str h7, \[sp, #16\] + 4c: 7c0553e7 stur h7, \[sp, #85\] + 50: 7c0ff3e7 stur h7, \[sp, #255\] + 54: 7d3fffe7 str h7, \[sp, #8190\] + 58: bc1003e7 stur s7, \[sp, #-256\] + 5c: bc1553e7 stur s7, \[sp, #-171\] 60: bd0003e7 str s7, \[sp\] 64: bd0003e7 str s7, \[sp\] - 68: bc0023e7 stur s7, \[sp,#2\] - 6c: bd0007e7 str s7, \[sp,#4\] - 70: bd000be7 str s7, \[sp,#8\] - 74: bd0013e7 str s7, \[sp,#16\] - 78: bc0553e7 stur s7, \[sp,#85\] - 7c: bc0ff3e7 stur s7, \[sp,#255\] - 80: bd3fffe7 str s7, \[sp,#16380\] - 84: fc1003e7 stur d7, \[sp,#-256\] - 88: fc1553e7 stur d7, \[sp,#-171\] + 68: bc0023e7 stur s7, \[sp, #2\] + 6c: bd0007e7 str s7, \[sp, #4\] + 70: bd000be7 str s7, \[sp, #8\] + 74: bd0013e7 str s7, \[sp, #16\] + 78: bc0553e7 stur s7, \[sp, #85\] + 7c: bc0ff3e7 stur s7, \[sp, #255\] + 80: bd3fffe7 str s7, \[sp, #16380\] + 84: fc1003e7 stur d7, \[sp, #-256\] + 88: fc1553e7 stur d7, \[sp, #-171\] 8c: fd0003e7 str d7, \[sp\] 90: fd0003e7 str d7, \[sp\] - 94: fc0023e7 stur d7, \[sp,#2\] - 98: fc0043e7 stur d7, \[sp,#4\] - 9c: fd0007e7 str d7, \[sp,#8\] - a0: fd000be7 str d7, \[sp,#16\] - a4: fc0553e7 stur d7, \[sp,#85\] - a8: fc0ff3e7 stur d7, \[sp,#255\] - ac: fd3fffe7 str d7, \[sp,#32760\] - b0: 3c9003e7 stur q7, \[sp,#-256\] - b4: 3c9553e7 stur q7, \[sp,#-171\] + 94: fc0023e7 stur d7, \[sp, #2\] + 98: fc0043e7 stur d7, \[sp, #4\] + 9c: fd0007e7 str d7, \[sp, #8\] + a0: fd000be7 str d7, \[sp, #16\] + a4: fc0553e7 stur d7, \[sp, #85\] + a8: fc0ff3e7 stur d7, \[sp, #255\] + ac: fd3fffe7 str d7, \[sp, #32760\] + b0: 3c9003e7 stur q7, \[sp, #-256\] + b4: 3c9553e7 stur q7, \[sp, #-171\] b8: 3d8003e7 str q7, \[sp\] bc: 3d8003e7 str q7, \[sp\] - c0: 3c8023e7 stur q7, \[sp,#2\] - c4: 3c8043e7 stur q7, \[sp,#4\] - c8: 3c8083e7 stur q7, \[sp,#8\] - cc: 3d8007e7 str q7, \[sp,#16\] - d0: 3c8553e7 stur q7, \[sp,#85\] - d4: 3c8ff3e7 stur q7, \[sp,#255\] - d8: 3dbfffe7 str q7, \[sp,#65520\] - dc: 3c5003e7 ldur b7, \[sp,#-256\] - e0: 3c5553e7 ldur b7, \[sp,#-171\] + c0: 3c8023e7 stur q7, \[sp, #2\] + c4: 3c8043e7 stur q7, \[sp, #4\] + c8: 3c8083e7 stur q7, \[sp, #8\] + cc: 3d8007e7 str q7, \[sp, #16\] + d0: 3c8553e7 stur q7, \[sp, #85\] + d4: 3c8ff3e7 stur q7, \[sp, #255\] + d8: 3dbfffe7 str q7, \[sp, #65520\] + dc: 3c5003e7 ldur b7, \[sp, #-256\] + e0: 3c5553e7 ldur b7, \[sp, #-171\] e4: 3d4003e7 ldr b7, \[sp\] e8: 3d4003e7 ldr b7, \[sp\] - ec: 3d400be7 ldr b7, \[sp,#2\] - f0: 3d4013e7 ldr b7, \[sp,#4\] - f4: 3d4023e7 ldr b7, \[sp,#8\] - f8: 3d4043e7 ldr b7, \[sp,#16\] - fc: 3d4157e7 ldr b7, \[sp,#85\] - 100: 3d43ffe7 ldr b7, \[sp,#255\] - 104: 3d7fffe7 ldr b7, \[sp,#4095\] - 108: 7c5003e7 ldur h7, \[sp,#-256\] - 10c: 7c5553e7 ldur h7, \[sp,#-171\] + ec: 3d400be7 ldr b7, \[sp, #2\] + f0: 3d4013e7 ldr b7, \[sp, #4\] + f4: 3d4023e7 ldr b7, \[sp, #8\] + f8: 3d4043e7 ldr b7, \[sp, #16\] + fc: 3d4157e7 ldr b7, \[sp, #85\] + 100: 3d43ffe7 ldr b7, \[sp, #255\] + 104: 3d7fffe7 ldr b7, \[sp, #4095\] + 108: 7c5003e7 ldur h7, \[sp, #-256\] + 10c: 7c5553e7 ldur h7, \[sp, #-171\] 110: 7d4003e7 ldr h7, \[sp\] 114: 7d4003e7 ldr h7, \[sp\] - 118: 7d4007e7 ldr h7, \[sp,#2\] - 11c: 7d400be7 ldr h7, \[sp,#4\] - 120: 7d4013e7 ldr h7, \[sp,#8\] - 124: 7d4023e7 ldr h7, \[sp,#16\] - 128: 7c4553e7 ldur h7, \[sp,#85\] - 12c: 7c4ff3e7 ldur h7, \[sp,#255\] - 130: 7d7fffe7 ldr h7, \[sp,#8190\] - 134: bc5003e7 ldur s7, \[sp,#-256\] - 138: bc5553e7 ldur s7, \[sp,#-171\] + 118: 7d4007e7 ldr h7, \[sp, #2\] + 11c: 7d400be7 ldr h7, \[sp, #4\] + 120: 7d4013e7 ldr h7, \[sp, #8\] + 124: 7d4023e7 ldr h7, \[sp, #16\] + 128: 7c4553e7 ldur h7, \[sp, #85\] + 12c: 7c4ff3e7 ldur h7, \[sp, #255\] + 130: 7d7fffe7 ldr h7, \[sp, #8190\] + 134: bc5003e7 ldur s7, \[sp, #-256\] + 138: bc5553e7 ldur s7, \[sp, #-171\] 13c: bd4003e7 ldr s7, \[sp\] 140: bd4003e7 ldr s7, \[sp\] - 144: bc4023e7 ldur s7, \[sp,#2\] - 148: bd4007e7 ldr s7, \[sp,#4\] - 14c: bd400be7 ldr s7, \[sp,#8\] - 150: bd4013e7 ldr s7, \[sp,#16\] - 154: bc4553e7 ldur s7, \[sp,#85\] - 158: bc4ff3e7 ldur s7, \[sp,#255\] - 15c: bd7fffe7 ldr s7, \[sp,#16380\] - 160: fc5003e7 ldur d7, \[sp,#-256\] - 164: fc5553e7 ldur d7, \[sp,#-171\] + 144: bc4023e7 ldur s7, \[sp, #2\] + 148: bd4007e7 ldr s7, \[sp, #4\] + 14c: bd400be7 ldr s7, \[sp, #8\] + 150: bd4013e7 ldr s7, \[sp, #16\] + 154: bc4553e7 ldur s7, \[sp, #85\] + 158: bc4ff3e7 ldur s7, \[sp, #255\] + 15c: bd7fffe7 ldr s7, \[sp, #16380\] + 160: fc5003e7 ldur d7, \[sp, #-256\] + 164: fc5553e7 ldur d7, \[sp, #-171\] 168: fd4003e7 ldr d7, \[sp\] 16c: fd4003e7 ldr d7, \[sp\] - 170: fc4023e7 ldur d7, \[sp,#2\] - 174: fc4043e7 ldur d7, \[sp,#4\] - 178: fd4007e7 ldr d7, \[sp,#8\] - 17c: fd400be7 ldr d7, \[sp,#16\] - 180: fc4553e7 ldur d7, \[sp,#85\] - 184: fc4ff3e7 ldur d7, \[sp,#255\] - 188: fd7fffe7 ldr d7, \[sp,#32760\] - 18c: 3cd003e7 ldur q7, \[sp,#-256\] - 190: 3cd553e7 ldur q7, \[sp,#-171\] + 170: fc4023e7 ldur d7, \[sp, #2\] + 174: fc4043e7 ldur d7, \[sp, #4\] + 178: fd4007e7 ldr d7, \[sp, #8\] + 17c: fd400be7 ldr d7, \[sp, #16\] + 180: fc4553e7 ldur d7, \[sp, #85\] + 184: fc4ff3e7 ldur d7, \[sp, #255\] + 188: fd7fffe7 ldr d7, \[sp, #32760\] + 18c: 3cd003e7 ldur q7, \[sp, #-256\] + 190: 3cd553e7 ldur q7, \[sp, #-171\] 194: 3dc003e7 ldr q7, \[sp\] 198: 3dc003e7 ldr q7, \[sp\] - 19c: 3cc023e7 ldur q7, \[sp,#2\] - 1a0: 3cc043e7 ldur q7, \[sp,#4\] - 1a4: 3cc083e7 ldur q7, \[sp,#8\] - 1a8: 3dc007e7 ldr q7, \[sp,#16\] - 1ac: 3cc553e7 ldur q7, \[sp,#85\] - 1b0: 3ccff3e7 ldur q7, \[sp,#255\] - 1b4: 3dffffe7 ldr q7, \[sp,#65520\] - 1b8: 381003e7 sturb w7, \[sp,#-256\] - 1bc: 381553e7 sturb w7, \[sp,#-171\] + 19c: 3cc023e7 ldur q7, \[sp, #2\] + 1a0: 3cc043e7 ldur q7, \[sp, #4\] + 1a4: 3cc083e7 ldur q7, \[sp, #8\] + 1a8: 3dc007e7 ldr q7, \[sp, #16\] + 1ac: 3cc553e7 ldur q7, \[sp, #85\] + 1b0: 3ccff3e7 ldur q7, \[sp, #255\] + 1b4: 3dffffe7 ldr q7, \[sp, #65520\] + 1b8: 381003e7 sturb w7, \[sp, #-256\] + 1bc: 381553e7 sturb w7, \[sp, #-171\] 1c0: 390003e7 strb w7, \[sp\] 1c4: 390003e7 strb w7, \[sp\] - 1c8: 39000be7 strb w7, \[sp,#2\] - 1cc: 390013e7 strb w7, \[sp,#4\] - 1d0: 390023e7 strb w7, \[sp,#8\] - 1d4: 390043e7 strb w7, \[sp,#16\] - 1d8: 390157e7 strb w7, \[sp,#85\] - 1dc: 3903ffe7 strb w7, \[sp,#255\] - 1e0: 393fffe7 strb w7, \[sp,#4095\] - 1e4: 781003e7 sturh w7, \[sp,#-256\] - 1e8: 781553e7 sturh w7, \[sp,#-171\] + 1c8: 39000be7 strb w7, \[sp, #2\] + 1cc: 390013e7 strb w7, \[sp, #4\] + 1d0: 390023e7 strb w7, \[sp, #8\] + 1d4: 390043e7 strb w7, \[sp, #16\] + 1d8: 390157e7 strb w7, \[sp, #85\] + 1dc: 3903ffe7 strb w7, \[sp, #255\] + 1e0: 393fffe7 strb w7, \[sp, #4095\] + 1e4: 781003e7 sturh w7, \[sp, #-256\] + 1e8: 781553e7 sturh w7, \[sp, #-171\] 1ec: 790003e7 strh w7, \[sp\] 1f0: 790003e7 strh w7, \[sp\] - 1f4: 790007e7 strh w7, \[sp,#2\] - 1f8: 79000be7 strh w7, \[sp,#4\] - 1fc: 790013e7 strh w7, \[sp,#8\] - 200: 790023e7 strh w7, \[sp,#16\] - 204: 780553e7 sturh w7, \[sp,#85\] - 208: 780ff3e7 sturh w7, \[sp,#255\] - 20c: 793fffe7 strh w7, \[sp,#8190\] - 210: b81003e7 stur w7, \[sp,#-256\] - 214: b81553e7 stur w7, \[sp,#-171\] + 1f4: 790007e7 strh w7, \[sp, #2\] + 1f8: 79000be7 strh w7, \[sp, #4\] + 1fc: 790013e7 strh w7, \[sp, #8\] + 200: 790023e7 strh w7, \[sp, #16\] + 204: 780553e7 sturh w7, \[sp, #85\] + 208: 780ff3e7 sturh w7, \[sp, #255\] + 20c: 793fffe7 strh w7, \[sp, #8190\] + 210: b81003e7 stur w7, \[sp, #-256\] + 214: b81553e7 stur w7, \[sp, #-171\] 218: b90003e7 str w7, \[sp\] 21c: b90003e7 str w7, \[sp\] - 220: b80023e7 stur w7, \[sp,#2\] - 224: b90007e7 str w7, \[sp,#4\] - 228: b9000be7 str w7, \[sp,#8\] - 22c: b90013e7 str w7, \[sp,#16\] - 230: b80553e7 stur w7, \[sp,#85\] - 234: b80ff3e7 stur w7, \[sp,#255\] - 238: b93fffe7 str w7, \[sp,#16380\] - 23c: f81003e7 stur x7, \[sp,#-256\] - 240: f81553e7 stur x7, \[sp,#-171\] + 220: b80023e7 stur w7, \[sp, #2\] + 224: b90007e7 str w7, \[sp, #4\] + 228: b9000be7 str w7, \[sp, #8\] + 22c: b90013e7 str w7, \[sp, #16\] + 230: b80553e7 stur w7, \[sp, #85\] + 234: b80ff3e7 stur w7, \[sp, #255\] + 238: b93fffe7 str w7, \[sp, #16380\] + 23c: f81003e7 stur x7, \[sp, #-256\] + 240: f81553e7 stur x7, \[sp, #-171\] 244: f90003e7 str x7, \[sp\] 248: f90003e7 str x7, \[sp\] - 24c: f80023e7 stur x7, \[sp,#2\] - 250: f80043e7 stur x7, \[sp,#4\] - 254: f90007e7 str x7, \[sp,#8\] - 258: f9000be7 str x7, \[sp,#16\] - 25c: f80553e7 stur x7, \[sp,#85\] - 260: f80ff3e7 stur x7, \[sp,#255\] - 264: f93fffe7 str x7, \[sp,#32760\] - 268: 385003e7 ldurb w7, \[sp,#-256\] - 26c: 385553e7 ldurb w7, \[sp,#-171\] + 24c: f80023e7 stur x7, \[sp, #2\] + 250: f80043e7 stur x7, \[sp, #4\] + 254: f90007e7 str x7, \[sp, #8\] + 258: f9000be7 str x7, \[sp, #16\] + 25c: f80553e7 stur x7, \[sp, #85\] + 260: f80ff3e7 stur x7, \[sp, #255\] + 264: f93fffe7 str x7, \[sp, #32760\] + 268: 385003e7 ldurb w7, \[sp, #-256\] + 26c: 385553e7 ldurb w7, \[sp, #-171\] 270: 394003e7 ldrb w7, \[sp\] 274: 394003e7 ldrb w7, \[sp\] - 278: 39400be7 ldrb w7, \[sp,#2\] - 27c: 394013e7 ldrb w7, \[sp,#4\] - 280: 394023e7 ldrb w7, \[sp,#8\] - 284: 394043e7 ldrb w7, \[sp,#16\] - 288: 394157e7 ldrb w7, \[sp,#85\] - 28c: 3943ffe7 ldrb w7, \[sp,#255\] - 290: 397fffe7 ldrb w7, \[sp,#4095\] - 294: 785003e7 ldurh w7, \[sp,#-256\] - 298: 785553e7 ldurh w7, \[sp,#-171\] + 278: 39400be7 ldrb w7, \[sp, #2\] + 27c: 394013e7 ldrb w7, \[sp, #4\] + 280: 394023e7 ldrb w7, \[sp, #8\] + 284: 394043e7 ldrb w7, \[sp, #16\] + 288: 394157e7 ldrb w7, \[sp, #85\] + 28c: 3943ffe7 ldrb w7, \[sp, #255\] + 290: 397fffe7 ldrb w7, \[sp, #4095\] + 294: 785003e7 ldurh w7, \[sp, #-256\] + 298: 785553e7 ldurh w7, \[sp, #-171\] 29c: 794003e7 ldrh w7, \[sp\] 2a0: 794003e7 ldrh w7, \[sp\] - 2a4: 794007e7 ldrh w7, \[sp,#2\] - 2a8: 79400be7 ldrh w7, \[sp,#4\] - 2ac: 794013e7 ldrh w7, \[sp,#8\] - 2b0: 794023e7 ldrh w7, \[sp,#16\] - 2b4: 784553e7 ldurh w7, \[sp,#85\] - 2b8: 784ff3e7 ldurh w7, \[sp,#255\] - 2bc: 797fffe7 ldrh w7, \[sp,#8190\] - 2c0: b85003e7 ldur w7, \[sp,#-256\] - 2c4: b85553e7 ldur w7, \[sp,#-171\] + 2a4: 794007e7 ldrh w7, \[sp, #2\] + 2a8: 79400be7 ldrh w7, \[sp, #4\] + 2ac: 794013e7 ldrh w7, \[sp, #8\] + 2b0: 794023e7 ldrh w7, \[sp, #16\] + 2b4: 784553e7 ldurh w7, \[sp, #85\] + 2b8: 784ff3e7 ldurh w7, \[sp, #255\] + 2bc: 797fffe7 ldrh w7, \[sp, #8190\] + 2c0: b85003e7 ldur w7, \[sp, #-256\] + 2c4: b85553e7 ldur w7, \[sp, #-171\] 2c8: b94003e7 ldr w7, \[sp\] 2cc: b94003e7 ldr w7, \[sp\] - 2d0: b84023e7 ldur w7, \[sp,#2\] - 2d4: b94007e7 ldr w7, \[sp,#4\] - 2d8: b9400be7 ldr w7, \[sp,#8\] - 2dc: b94013e7 ldr w7, \[sp,#16\] - 2e0: b84553e7 ldur w7, \[sp,#85\] - 2e4: b84ff3e7 ldur w7, \[sp,#255\] - 2e8: b97fffe7 ldr w7, \[sp,#16380\] - 2ec: f85003e7 ldur x7, \[sp,#-256\] - 2f0: f85553e7 ldur x7, \[sp,#-171\] + 2d0: b84023e7 ldur w7, \[sp, #2\] + 2d4: b94007e7 ldr w7, \[sp, #4\] + 2d8: b9400be7 ldr w7, \[sp, #8\] + 2dc: b94013e7 ldr w7, \[sp, #16\] + 2e0: b84553e7 ldur w7, \[sp, #85\] + 2e4: b84ff3e7 ldur w7, \[sp, #255\] + 2e8: b97fffe7 ldr w7, \[sp, #16380\] + 2ec: f85003e7 ldur x7, \[sp, #-256\] + 2f0: f85553e7 ldur x7, \[sp, #-171\] 2f4: f94003e7 ldr x7, \[sp\] 2f8: f94003e7 ldr x7, \[sp\] - 2fc: f84023e7 ldur x7, \[sp,#2\] - 300: f84043e7 ldur x7, \[sp,#4\] - 304: f94007e7 ldr x7, \[sp,#8\] - 308: f9400be7 ldr x7, \[sp,#16\] - 30c: f84553e7 ldur x7, \[sp,#85\] - 310: f84ff3e7 ldur x7, \[sp,#255\] - 314: f97fffe7 ldr x7, \[sp,#32760\] - 318: 389003e7 ldursb x7, \[sp,#-256\] - 31c: 389553e7 ldursb x7, \[sp,#-171\] + 2fc: f84023e7 ldur x7, \[sp, #2\] + 300: f84043e7 ldur x7, \[sp, #4\] + 304: f94007e7 ldr x7, \[sp, #8\] + 308: f9400be7 ldr x7, \[sp, #16\] + 30c: f84553e7 ldur x7, \[sp, #85\] + 310: f84ff3e7 ldur x7, \[sp, #255\] + 314: f97fffe7 ldr x7, \[sp, #32760\] + 318: 389003e7 ldursb x7, \[sp, #-256\] + 31c: 389553e7 ldursb x7, \[sp, #-171\] 320: 398003e7 ldrsb x7, \[sp\] 324: 398003e7 ldrsb x7, \[sp\] - 328: 39800be7 ldrsb x7, \[sp,#2\] - 32c: 398013e7 ldrsb x7, \[sp,#4\] - 330: 398023e7 ldrsb x7, \[sp,#8\] - 334: 398043e7 ldrsb x7, \[sp,#16\] - 338: 398157e7 ldrsb x7, \[sp,#85\] - 33c: 3983ffe7 ldrsb x7, \[sp,#255\] - 340: 39bfffe7 ldrsb x7, \[sp,#4095\] - 344: 789003e7 ldursh x7, \[sp,#-256\] - 348: 789553e7 ldursh x7, \[sp,#-171\] + 328: 39800be7 ldrsb x7, \[sp, #2\] + 32c: 398013e7 ldrsb x7, \[sp, #4\] + 330: 398023e7 ldrsb x7, \[sp, #8\] + 334: 398043e7 ldrsb x7, \[sp, #16\] + 338: 398157e7 ldrsb x7, \[sp, #85\] + 33c: 3983ffe7 ldrsb x7, \[sp, #255\] + 340: 39bfffe7 ldrsb x7, \[sp, #4095\] + 344: 789003e7 ldursh x7, \[sp, #-256\] + 348: 789553e7 ldursh x7, \[sp, #-171\] 34c: 798003e7 ldrsh x7, \[sp\] 350: 798003e7 ldrsh x7, \[sp\] - 354: 798007e7 ldrsh x7, \[sp,#2\] - 358: 79800be7 ldrsh x7, \[sp,#4\] - 35c: 798013e7 ldrsh x7, \[sp,#8\] - 360: 798023e7 ldrsh x7, \[sp,#16\] - 364: 788553e7 ldursh x7, \[sp,#85\] - 368: 788ff3e7 ldursh x7, \[sp,#255\] - 36c: 79bfffe7 ldrsh x7, \[sp,#8190\] - 370: b89003e7 ldursw x7, \[sp,#-256\] - 374: b89553e7 ldursw x7, \[sp,#-171\] + 354: 798007e7 ldrsh x7, \[sp, #2\] + 358: 79800be7 ldrsh x7, \[sp, #4\] + 35c: 798013e7 ldrsh x7, \[sp, #8\] + 360: 798023e7 ldrsh x7, \[sp, #16\] + 364: 788553e7 ldursh x7, \[sp, #85\] + 368: 788ff3e7 ldursh x7, \[sp, #255\] + 36c: 79bfffe7 ldrsh x7, \[sp, #8190\] + 370: b89003e7 ldursw x7, \[sp, #-256\] + 374: b89553e7 ldursw x7, \[sp, #-171\] 378: b98003e7 ldrsw x7, \[sp\] 37c: b98003e7 ldrsw x7, \[sp\] - 380: b88023e7 ldursw x7, \[sp,#2\] - 384: b98007e7 ldrsw x7, \[sp,#4\] - 388: b9800be7 ldrsw x7, \[sp,#8\] - 38c: b98013e7 ldrsw x7, \[sp,#16\] - 390: b88553e7 ldursw x7, \[sp,#85\] - 394: b88ff3e7 ldursw x7, \[sp,#255\] - 398: b9bfffe7 ldrsw x7, \[sp,#16380\] - 39c: 38d003e7 ldursb w7, \[sp,#-256\] - 3a0: 38d553e7 ldursb w7, \[sp,#-171\] + 380: b88023e7 ldursw x7, \[sp, #2\] + 384: b98007e7 ldrsw x7, \[sp, #4\] + 388: b9800be7 ldrsw x7, \[sp, #8\] + 38c: b98013e7 ldrsw x7, \[sp, #16\] + 390: b88553e7 ldursw x7, \[sp, #85\] + 394: b88ff3e7 ldursw x7, \[sp, #255\] + 398: b9bfffe7 ldrsw x7, \[sp, #16380\] + 39c: 38d003e7 ldursb w7, \[sp, #-256\] + 3a0: 38d553e7 ldursb w7, \[sp, #-171\] 3a4: 39c003e7 ldrsb w7, \[sp\] 3a8: 39c003e7 ldrsb w7, \[sp\] - 3ac: 39c00be7 ldrsb w7, \[sp,#2\] - 3b0: 39c013e7 ldrsb w7, \[sp,#4\] - 3b4: 39c023e7 ldrsb w7, \[sp,#8\] - 3b8: 39c043e7 ldrsb w7, \[sp,#16\] - 3bc: 39c157e7 ldrsb w7, \[sp,#85\] - 3c0: 39c3ffe7 ldrsb w7, \[sp,#255\] - 3c4: 39ffffe7 ldrsb w7, \[sp,#4095\] - 3c8: 78d003e7 ldursh w7, \[sp,#-256\] - 3cc: 78d553e7 ldursh w7, \[sp,#-171\] + 3ac: 39c00be7 ldrsb w7, \[sp, #2\] + 3b0: 39c013e7 ldrsb w7, \[sp, #4\] + 3b4: 39c023e7 ldrsb w7, \[sp, #8\] + 3b8: 39c043e7 ldrsb w7, \[sp, #16\] + 3bc: 39c157e7 ldrsb w7, \[sp, #85\] + 3c0: 39c3ffe7 ldrsb w7, \[sp, #255\] + 3c4: 39ffffe7 ldrsb w7, \[sp, #4095\] + 3c8: 78d003e7 ldursh w7, \[sp, #-256\] + 3cc: 78d553e7 ldursh w7, \[sp, #-171\] 3d0: 79c003e7 ldrsh w7, \[sp\] 3d4: 79c003e7 ldrsh w7, \[sp\] - 3d8: 79c007e7 ldrsh w7, \[sp,#2\] - 3dc: 79c00be7 ldrsh w7, \[sp,#4\] - 3e0: 79c013e7 ldrsh w7, \[sp,#8\] - 3e4: 79c023e7 ldrsh w7, \[sp,#16\] - 3e8: 78c553e7 ldursh w7, \[sp,#85\] - 3ec: 78cff3e7 ldursh w7, \[sp,#255\] - 3f0: 79ffffe7 ldrsh w7, \[sp,#8190\] + 3d8: 79c007e7 ldrsh w7, \[sp, #2\] + 3dc: 79c00be7 ldrsh w7, \[sp, #4\] + 3e0: 79c013e7 ldrsh w7, \[sp, #8\] + 3e4: 79c023e7 ldrsh w7, \[sp, #16\] + 3e8: 78c553e7 ldursh w7, \[sp, #85\] + 3ec: 78cff3e7 ldursh w7, \[sp, #255\] + 3f0: 79ffffe7 ldrsh w7, \[sp, #8190\] diff --git a/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d b/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d index 03358e9abb4..ad72d76f5be 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d @@ -5,233 +5,233 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: 3c1003e7 stur b7, \[sp,#-256\] - 4: 3c1553e7 stur b7, \[sp,#-171\] + 0: 3c1003e7 stur b7, \[sp, #-256\] + 4: 3c1553e7 stur b7, \[sp, #-171\] 8: 3c0003e7 stur b7, \[sp\] c: 3c0003e7 stur b7, \[sp\] - 10: 3c0023e7 stur b7, \[sp,#2\] - 14: 3c0043e7 stur b7, \[sp,#4\] - 18: 3c0083e7 stur b7, \[sp,#8\] - 1c: 3c0103e7 stur b7, \[sp,#16\] - 20: 3c0553e7 stur b7, \[sp,#85\] - 24: 3c0ff3e7 stur b7, \[sp,#255\] - 28: 7c1003e7 stur h7, \[sp,#-256\] - 2c: 7c1553e7 stur h7, \[sp,#-171\] + 10: 3c0023e7 stur b7, \[sp, #2\] + 14: 3c0043e7 stur b7, \[sp, #4\] + 18: 3c0083e7 stur b7, \[sp, #8\] + 1c: 3c0103e7 stur b7, \[sp, #16\] + 20: 3c0553e7 stur b7, \[sp, #85\] + 24: 3c0ff3e7 stur b7, \[sp, #255\] + 28: 7c1003e7 stur h7, \[sp, #-256\] + 2c: 7c1553e7 stur h7, \[sp, #-171\] 30: 7c0003e7 stur h7, \[sp\] 34: 7c0003e7 stur h7, \[sp\] - 38: 7c0023e7 stur h7, \[sp,#2\] - 3c: 7c0043e7 stur h7, \[sp,#4\] - 40: 7c0083e7 stur h7, \[sp,#8\] - 44: 7c0103e7 stur h7, \[sp,#16\] - 48: 7c0553e7 stur h7, \[sp,#85\] - 4c: 7c0ff3e7 stur h7, \[sp,#255\] - 50: bc1003e7 stur s7, \[sp,#-256\] - 54: bc1553e7 stur s7, \[sp,#-171\] + 38: 7c0023e7 stur h7, \[sp, #2\] + 3c: 7c0043e7 stur h7, \[sp, #4\] + 40: 7c0083e7 stur h7, \[sp, #8\] + 44: 7c0103e7 stur h7, \[sp, #16\] + 48: 7c0553e7 stur h7, \[sp, #85\] + 4c: 7c0ff3e7 stur h7, \[sp, #255\] + 50: bc1003e7 stur s7, \[sp, #-256\] + 54: bc1553e7 stur s7, \[sp, #-171\] 58: bc0003e7 stur s7, \[sp\] 5c: bc0003e7 stur s7, \[sp\] - 60: bc0023e7 stur s7, \[sp,#2\] - 64: bc0043e7 stur s7, \[sp,#4\] - 68: bc0083e7 stur s7, \[sp,#8\] - 6c: bc0103e7 stur s7, \[sp,#16\] - 70: bc0553e7 stur s7, \[sp,#85\] - 74: bc0ff3e7 stur s7, \[sp,#255\] - 78: fc1003e7 stur d7, \[sp,#-256\] - 7c: fc1553e7 stur d7, \[sp,#-171\] + 60: bc0023e7 stur s7, \[sp, #2\] + 64: bc0043e7 stur s7, \[sp, #4\] + 68: bc0083e7 stur s7, \[sp, #8\] + 6c: bc0103e7 stur s7, \[sp, #16\] + 70: bc0553e7 stur s7, \[sp, #85\] + 74: bc0ff3e7 stur s7, \[sp, #255\] + 78: fc1003e7 stur d7, \[sp, #-256\] + 7c: fc1553e7 stur d7, \[sp, #-171\] 80: fc0003e7 stur d7, \[sp\] 84: fc0003e7 stur d7, \[sp\] - 88: fc0023e7 stur d7, \[sp,#2\] - 8c: fc0043e7 stur d7, \[sp,#4\] - 90: fc0083e7 stur d7, \[sp,#8\] - 94: fc0103e7 stur d7, \[sp,#16\] - 98: fc0553e7 stur d7, \[sp,#85\] - 9c: fc0ff3e7 stur d7, \[sp,#255\] - a0: 3c9003e7 stur q7, \[sp,#-256\] - a4: 3c9553e7 stur q7, \[sp,#-171\] + 88: fc0023e7 stur d7, \[sp, #2\] + 8c: fc0043e7 stur d7, \[sp, #4\] + 90: fc0083e7 stur d7, \[sp, #8\] + 94: fc0103e7 stur d7, \[sp, #16\] + 98: fc0553e7 stur d7, \[sp, #85\] + 9c: fc0ff3e7 stur d7, \[sp, #255\] + a0: 3c9003e7 stur q7, \[sp, #-256\] + a4: 3c9553e7 stur q7, \[sp, #-171\] a8: 3c8003e7 stur q7, \[sp\] ac: 3c8003e7 stur q7, \[sp\] - b0: 3c8023e7 stur q7, \[sp,#2\] - b4: 3c8043e7 stur q7, \[sp,#4\] - b8: 3c8083e7 stur q7, \[sp,#8\] - bc: 3c8103e7 stur q7, \[sp,#16\] - c0: 3c8553e7 stur q7, \[sp,#85\] - c4: 3c8ff3e7 stur q7, \[sp,#255\] - c8: 3c5003e7 ldur b7, \[sp,#-256\] - cc: 3c5553e7 ldur b7, \[sp,#-171\] + b0: 3c8023e7 stur q7, \[sp, #2\] + b4: 3c8043e7 stur q7, \[sp, #4\] + b8: 3c8083e7 stur q7, \[sp, #8\] + bc: 3c8103e7 stur q7, \[sp, #16\] + c0: 3c8553e7 stur q7, \[sp, #85\] + c4: 3c8ff3e7 stur q7, \[sp, #255\] + c8: 3c5003e7 ldur b7, \[sp, #-256\] + cc: 3c5553e7 ldur b7, \[sp, #-171\] d0: 3c4003e7 ldur b7, \[sp\] d4: 3c4003e7 ldur b7, \[sp\] - d8: 3c4023e7 ldur b7, \[sp,#2\] - dc: 3c4043e7 ldur b7, \[sp,#4\] - e0: 3c4083e7 ldur b7, \[sp,#8\] - e4: 3c4103e7 ldur b7, \[sp,#16\] - e8: 3c4553e7 ldur b7, \[sp,#85\] - ec: 3c4ff3e7 ldur b7, \[sp,#255\] - f0: 7c5003e7 ldur h7, \[sp,#-256\] - f4: 7c5553e7 ldur h7, \[sp,#-171\] + d8: 3c4023e7 ldur b7, \[sp, #2\] + dc: 3c4043e7 ldur b7, \[sp, #4\] + e0: 3c4083e7 ldur b7, \[sp, #8\] + e4: 3c4103e7 ldur b7, \[sp, #16\] + e8: 3c4553e7 ldur b7, \[sp, #85\] + ec: 3c4ff3e7 ldur b7, \[sp, #255\] + f0: 7c5003e7 ldur h7, \[sp, #-256\] + f4: 7c5553e7 ldur h7, \[sp, #-171\] f8: 7c4003e7 ldur h7, \[sp\] fc: 7c4003e7 ldur h7, \[sp\] - 100: 7c4023e7 ldur h7, \[sp,#2\] - 104: 7c4043e7 ldur h7, \[sp,#4\] - 108: 7c4083e7 ldur h7, \[sp,#8\] - 10c: 7c4103e7 ldur h7, \[sp,#16\] - 110: 7c4553e7 ldur h7, \[sp,#85\] - 114: 7c4ff3e7 ldur h7, \[sp,#255\] - 118: bc5003e7 ldur s7, \[sp,#-256\] - 11c: bc5553e7 ldur s7, \[sp,#-171\] + 100: 7c4023e7 ldur h7, \[sp, #2\] + 104: 7c4043e7 ldur h7, \[sp, #4\] + 108: 7c4083e7 ldur h7, \[sp, #8\] + 10c: 7c4103e7 ldur h7, \[sp, #16\] + 110: 7c4553e7 ldur h7, \[sp, #85\] + 114: 7c4ff3e7 ldur h7, \[sp, #255\] + 118: bc5003e7 ldur s7, \[sp, #-256\] + 11c: bc5553e7 ldur s7, \[sp, #-171\] 120: bc4003e7 ldur s7, \[sp\] 124: bc4003e7 ldur s7, \[sp\] - 128: bc4023e7 ldur s7, \[sp,#2\] - 12c: bc4043e7 ldur s7, \[sp,#4\] - 130: bc4083e7 ldur s7, \[sp,#8\] - 134: bc4103e7 ldur s7, \[sp,#16\] - 138: bc4553e7 ldur s7, \[sp,#85\] - 13c: bc4ff3e7 ldur s7, \[sp,#255\] - 140: fc5003e7 ldur d7, \[sp,#-256\] - 144: fc5553e7 ldur d7, \[sp,#-171\] + 128: bc4023e7 ldur s7, \[sp, #2\] + 12c: bc4043e7 ldur s7, \[sp, #4\] + 130: bc4083e7 ldur s7, \[sp, #8\] + 134: bc4103e7 ldur s7, \[sp, #16\] + 138: bc4553e7 ldur s7, \[sp, #85\] + 13c: bc4ff3e7 ldur s7, \[sp, #255\] + 140: fc5003e7 ldur d7, \[sp, #-256\] + 144: fc5553e7 ldur d7, \[sp, #-171\] 148: fc4003e7 ldur d7, \[sp\] 14c: fc4003e7 ldur d7, \[sp\] - 150: fc4023e7 ldur d7, \[sp,#2\] - 154: fc4043e7 ldur d7, \[sp,#4\] - 158: fc4083e7 ldur d7, \[sp,#8\] - 15c: fc4103e7 ldur d7, \[sp,#16\] - 160: fc4553e7 ldur d7, \[sp,#85\] - 164: fc4ff3e7 ldur d7, \[sp,#255\] - 168: 3cd003e7 ldur q7, \[sp,#-256\] - 16c: 3cd553e7 ldur q7, \[sp,#-171\] + 150: fc4023e7 ldur d7, \[sp, #2\] + 154: fc4043e7 ldur d7, \[sp, #4\] + 158: fc4083e7 ldur d7, \[sp, #8\] + 15c: fc4103e7 ldur d7, \[sp, #16\] + 160: fc4553e7 ldur d7, \[sp, #85\] + 164: fc4ff3e7 ldur d7, \[sp, #255\] + 168: 3cd003e7 ldur q7, \[sp, #-256\] + 16c: 3cd553e7 ldur q7, \[sp, #-171\] 170: 3cc003e7 ldur q7, \[sp\] 174: 3cc003e7 ldur q7, \[sp\] - 178: 3cc023e7 ldur q7, \[sp,#2\] - 17c: 3cc043e7 ldur q7, \[sp,#4\] - 180: 3cc083e7 ldur q7, \[sp,#8\] - 184: 3cc103e7 ldur q7, \[sp,#16\] - 188: 3cc553e7 ldur q7, \[sp,#85\] - 18c: 3ccff3e7 ldur q7, \[sp,#255\] - 190: 381003e7 sturb w7, \[sp,#-256\] - 194: 381553e7 sturb w7, \[sp,#-171\] + 178: 3cc023e7 ldur q7, \[sp, #2\] + 17c: 3cc043e7 ldur q7, \[sp, #4\] + 180: 3cc083e7 ldur q7, \[sp, #8\] + 184: 3cc103e7 ldur q7, \[sp, #16\] + 188: 3cc553e7 ldur q7, \[sp, #85\] + 18c: 3ccff3e7 ldur q7, \[sp, #255\] + 190: 381003e7 sturb w7, \[sp, #-256\] + 194: 381553e7 sturb w7, \[sp, #-171\] 198: 380003e7 sturb w7, \[sp\] 19c: 380003e7 sturb w7, \[sp\] - 1a0: 380023e7 sturb w7, \[sp,#2\] - 1a4: 380043e7 sturb w7, \[sp,#4\] - 1a8: 380083e7 sturb w7, \[sp,#8\] - 1ac: 380103e7 sturb w7, \[sp,#16\] - 1b0: 380553e7 sturb w7, \[sp,#85\] - 1b4: 380ff3e7 sturb w7, \[sp,#255\] - 1b8: 781003e7 sturh w7, \[sp,#-256\] - 1bc: 781553e7 sturh w7, \[sp,#-171\] + 1a0: 380023e7 sturb w7, \[sp, #2\] + 1a4: 380043e7 sturb w7, \[sp, #4\] + 1a8: 380083e7 sturb w7, \[sp, #8\] + 1ac: 380103e7 sturb w7, \[sp, #16\] + 1b0: 380553e7 sturb w7, \[sp, #85\] + 1b4: 380ff3e7 sturb w7, \[sp, #255\] + 1b8: 781003e7 sturh w7, \[sp, #-256\] + 1bc: 781553e7 sturh w7, \[sp, #-171\] 1c0: 780003e7 sturh w7, \[sp\] 1c4: 780003e7 sturh w7, \[sp\] - 1c8: 780023e7 sturh w7, \[sp,#2\] - 1cc: 780043e7 sturh w7, \[sp,#4\] - 1d0: 780083e7 sturh w7, \[sp,#8\] - 1d4: 780103e7 sturh w7, \[sp,#16\] - 1d8: 780553e7 sturh w7, \[sp,#85\] - 1dc: 780ff3e7 sturh w7, \[sp,#255\] - 1e0: b81003e7 stur w7, \[sp,#-256\] - 1e4: b81553e7 stur w7, \[sp,#-171\] + 1c8: 780023e7 sturh w7, \[sp, #2\] + 1cc: 780043e7 sturh w7, \[sp, #4\] + 1d0: 780083e7 sturh w7, \[sp, #8\] + 1d4: 780103e7 sturh w7, \[sp, #16\] + 1d8: 780553e7 sturh w7, \[sp, #85\] + 1dc: 780ff3e7 sturh w7, \[sp, #255\] + 1e0: b81003e7 stur w7, \[sp, #-256\] + 1e4: b81553e7 stur w7, \[sp, #-171\] 1e8: b80003e7 stur w7, \[sp\] 1ec: b80003e7 stur w7, \[sp\] - 1f0: b80023e7 stur w7, \[sp,#2\] - 1f4: b80043e7 stur w7, \[sp,#4\] - 1f8: b80083e7 stur w7, \[sp,#8\] - 1fc: b80103e7 stur w7, \[sp,#16\] - 200: b80553e7 stur w7, \[sp,#85\] - 204: b80ff3e7 stur w7, \[sp,#255\] - 208: f81003e7 stur x7, \[sp,#-256\] - 20c: f81553e7 stur x7, \[sp,#-171\] + 1f0: b80023e7 stur w7, \[sp, #2\] + 1f4: b80043e7 stur w7, \[sp, #4\] + 1f8: b80083e7 stur w7, \[sp, #8\] + 1fc: b80103e7 stur w7, \[sp, #16\] + 200: b80553e7 stur w7, \[sp, #85\] + 204: b80ff3e7 stur w7, \[sp, #255\] + 208: f81003e7 stur x7, \[sp, #-256\] + 20c: f81553e7 stur x7, \[sp, #-171\] 210: f80003e7 stur x7, \[sp\] 214: f80003e7 stur x7, \[sp\] - 218: f80023e7 stur x7, \[sp,#2\] - 21c: f80043e7 stur x7, \[sp,#4\] - 220: f80083e7 stur x7, \[sp,#8\] - 224: f80103e7 stur x7, \[sp,#16\] - 228: f80553e7 stur x7, \[sp,#85\] - 22c: f80ff3e7 stur x7, \[sp,#255\] - 230: 385003e7 ldurb w7, \[sp,#-256\] - 234: 385553e7 ldurb w7, \[sp,#-171\] + 218: f80023e7 stur x7, \[sp, #2\] + 21c: f80043e7 stur x7, \[sp, #4\] + 220: f80083e7 stur x7, \[sp, #8\] + 224: f80103e7 stur x7, \[sp, #16\] + 228: f80553e7 stur x7, \[sp, #85\] + 22c: f80ff3e7 stur x7, \[sp, #255\] + 230: 385003e7 ldurb w7, \[sp, #-256\] + 234: 385553e7 ldurb w7, \[sp, #-171\] 238: 384003e7 ldurb w7, \[sp\] 23c: 384003e7 ldurb w7, \[sp\] - 240: 384023e7 ldurb w7, \[sp,#2\] - 244: 384043e7 ldurb w7, \[sp,#4\] - 248: 384083e7 ldurb w7, \[sp,#8\] - 24c: 384103e7 ldurb w7, \[sp,#16\] - 250: 384553e7 ldurb w7, \[sp,#85\] - 254: 384ff3e7 ldurb w7, \[sp,#255\] - 258: 785003e7 ldurh w7, \[sp,#-256\] - 25c: 785553e7 ldurh w7, \[sp,#-171\] + 240: 384023e7 ldurb w7, \[sp, #2\] + 244: 384043e7 ldurb w7, \[sp, #4\] + 248: 384083e7 ldurb w7, \[sp, #8\] + 24c: 384103e7 ldurb w7, \[sp, #16\] + 250: 384553e7 ldurb w7, \[sp, #85\] + 254: 384ff3e7 ldurb w7, \[sp, #255\] + 258: 785003e7 ldurh w7, \[sp, #-256\] + 25c: 785553e7 ldurh w7, \[sp, #-171\] 260: 784003e7 ldurh w7, \[sp\] 264: 784003e7 ldurh w7, \[sp\] - 268: 784023e7 ldurh w7, \[sp,#2\] - 26c: 784043e7 ldurh w7, \[sp,#4\] - 270: 784083e7 ldurh w7, \[sp,#8\] - 274: 784103e7 ldurh w7, \[sp,#16\] - 278: 784553e7 ldurh w7, \[sp,#85\] - 27c: 784ff3e7 ldurh w7, \[sp,#255\] - 280: b85003e7 ldur w7, \[sp,#-256\] - 284: b85553e7 ldur w7, \[sp,#-171\] + 268: 784023e7 ldurh w7, \[sp, #2\] + 26c: 784043e7 ldurh w7, \[sp, #4\] + 270: 784083e7 ldurh w7, \[sp, #8\] + 274: 784103e7 ldurh w7, \[sp, #16\] + 278: 784553e7 ldurh w7, \[sp, #85\] + 27c: 784ff3e7 ldurh w7, \[sp, #255\] + 280: b85003e7 ldur w7, \[sp, #-256\] + 284: b85553e7 ldur w7, \[sp, #-171\] 288: b84003e7 ldur w7, \[sp\] 28c: b84003e7 ldur w7, \[sp\] - 290: b84023e7 ldur w7, \[sp,#2\] - 294: b84043e7 ldur w7, \[sp,#4\] - 298: b84083e7 ldur w7, \[sp,#8\] - 29c: b84103e7 ldur w7, \[sp,#16\] - 2a0: b84553e7 ldur w7, \[sp,#85\] - 2a4: b84ff3e7 ldur w7, \[sp,#255\] - 2a8: f85003e7 ldur x7, \[sp,#-256\] - 2ac: f85553e7 ldur x7, \[sp,#-171\] + 290: b84023e7 ldur w7, \[sp, #2\] + 294: b84043e7 ldur w7, \[sp, #4\] + 298: b84083e7 ldur w7, \[sp, #8\] + 29c: b84103e7 ldur w7, \[sp, #16\] + 2a0: b84553e7 ldur w7, \[sp, #85\] + 2a4: b84ff3e7 ldur w7, \[sp, #255\] + 2a8: f85003e7 ldur x7, \[sp, #-256\] + 2ac: f85553e7 ldur x7, \[sp, #-171\] 2b0: f84003e7 ldur x7, \[sp\] 2b4: f84003e7 ldur x7, \[sp\] - 2b8: f84023e7 ldur x7, \[sp,#2\] - 2bc: f84043e7 ldur x7, \[sp,#4\] - 2c0: f84083e7 ldur x7, \[sp,#8\] - 2c4: f84103e7 ldur x7, \[sp,#16\] - 2c8: f84553e7 ldur x7, \[sp,#85\] - 2cc: f84ff3e7 ldur x7, \[sp,#255\] - 2d0: 389003e7 ldursb x7, \[sp,#-256\] - 2d4: 389553e7 ldursb x7, \[sp,#-171\] + 2b8: f84023e7 ldur x7, \[sp, #2\] + 2bc: f84043e7 ldur x7, \[sp, #4\] + 2c0: f84083e7 ldur x7, \[sp, #8\] + 2c4: f84103e7 ldur x7, \[sp, #16\] + 2c8: f84553e7 ldur x7, \[sp, #85\] + 2cc: f84ff3e7 ldur x7, \[sp, #255\] + 2d0: 389003e7 ldursb x7, \[sp, #-256\] + 2d4: 389553e7 ldursb x7, \[sp, #-171\] 2d8: 388003e7 ldursb x7, \[sp\] 2dc: 388003e7 ldursb x7, \[sp\] - 2e0: 388023e7 ldursb x7, \[sp,#2\] - 2e4: 388043e7 ldursb x7, \[sp,#4\] - 2e8: 388083e7 ldursb x7, \[sp,#8\] - 2ec: 388103e7 ldursb x7, \[sp,#16\] - 2f0: 388553e7 ldursb x7, \[sp,#85\] - 2f4: 388ff3e7 ldursb x7, \[sp,#255\] - 2f8: 789003e7 ldursh x7, \[sp,#-256\] - 2fc: 789553e7 ldursh x7, \[sp,#-171\] + 2e0: 388023e7 ldursb x7, \[sp, #2\] + 2e4: 388043e7 ldursb x7, \[sp, #4\] + 2e8: 388083e7 ldursb x7, \[sp, #8\] + 2ec: 388103e7 ldursb x7, \[sp, #16\] + 2f0: 388553e7 ldursb x7, \[sp, #85\] + 2f4: 388ff3e7 ldursb x7, \[sp, #255\] + 2f8: 789003e7 ldursh x7, \[sp, #-256\] + 2fc: 789553e7 ldursh x7, \[sp, #-171\] 300: 788003e7 ldursh x7, \[sp\] 304: 788003e7 ldursh x7, \[sp\] - 308: 788023e7 ldursh x7, \[sp,#2\] - 30c: 788043e7 ldursh x7, \[sp,#4\] - 310: 788083e7 ldursh x7, \[sp,#8\] - 314: 788103e7 ldursh x7, \[sp,#16\] - 318: 788553e7 ldursh x7, \[sp,#85\] - 31c: 788ff3e7 ldursh x7, \[sp,#255\] - 320: b89003e7 ldursw x7, \[sp,#-256\] - 324: b89553e7 ldursw x7, \[sp,#-171\] + 308: 788023e7 ldursh x7, \[sp, #2\] + 30c: 788043e7 ldursh x7, \[sp, #4\] + 310: 788083e7 ldursh x7, \[sp, #8\] + 314: 788103e7 ldursh x7, \[sp, #16\] + 318: 788553e7 ldursh x7, \[sp, #85\] + 31c: 788ff3e7 ldursh x7, \[sp, #255\] + 320: b89003e7 ldursw x7, \[sp, #-256\] + 324: b89553e7 ldursw x7, \[sp, #-171\] 328: b88003e7 ldursw x7, \[sp\] 32c: b88003e7 ldursw x7, \[sp\] - 330: b88023e7 ldursw x7, \[sp,#2\] - 334: b88043e7 ldursw x7, \[sp,#4\] - 338: b88083e7 ldursw x7, \[sp,#8\] - 33c: b88103e7 ldursw x7, \[sp,#16\] - 340: b88553e7 ldursw x7, \[sp,#85\] - 344: b88ff3e7 ldursw x7, \[sp,#255\] - 348: 38d003e7 ldursb w7, \[sp,#-256\] - 34c: 38d553e7 ldursb w7, \[sp,#-171\] + 330: b88023e7 ldursw x7, \[sp, #2\] + 334: b88043e7 ldursw x7, \[sp, #4\] + 338: b88083e7 ldursw x7, \[sp, #8\] + 33c: b88103e7 ldursw x7, \[sp, #16\] + 340: b88553e7 ldursw x7, \[sp, #85\] + 344: b88ff3e7 ldursw x7, \[sp, #255\] + 348: 38d003e7 ldursb w7, \[sp, #-256\] + 34c: 38d553e7 ldursb w7, \[sp, #-171\] 350: 38c003e7 ldursb w7, \[sp\] 354: 38c003e7 ldursb w7, \[sp\] - 358: 38c023e7 ldursb w7, \[sp,#2\] - 35c: 38c043e7 ldursb w7, \[sp,#4\] - 360: 38c083e7 ldursb w7, \[sp,#8\] - 364: 38c103e7 ldursb w7, \[sp,#16\] - 368: 38c553e7 ldursb w7, \[sp,#85\] - 36c: 38cff3e7 ldursb w7, \[sp,#255\] - 370: 78d003e7 ldursh w7, \[sp,#-256\] - 374: 78d553e7 ldursh w7, \[sp,#-171\] + 358: 38c023e7 ldursb w7, \[sp, #2\] + 35c: 38c043e7 ldursb w7, \[sp, #4\] + 360: 38c083e7 ldursb w7, \[sp, #8\] + 364: 38c103e7 ldursb w7, \[sp, #16\] + 368: 38c553e7 ldursb w7, \[sp, #85\] + 36c: 38cff3e7 ldursb w7, \[sp, #255\] + 370: 78d003e7 ldursh w7, \[sp, #-256\] + 374: 78d553e7 ldursh w7, \[sp, #-171\] 378: 78c003e7 ldursh w7, \[sp\] 37c: 78c003e7 ldursh w7, \[sp\] - 380: 78c023e7 ldursh w7, \[sp,#2\] - 384: 78c043e7 ldursh w7, \[sp,#4\] - 388: 78c083e7 ldursh w7, \[sp,#8\] - 38c: 78c103e7 ldursh w7, \[sp,#16\] - 390: 78c553e7 ldursh w7, \[sp,#85\] - 394: 78cff3e7 ldursh w7, \[sp,#255\] + 380: 78c023e7 ldursh w7, \[sp, #2\] + 384: 78c043e7 ldursh w7, \[sp, #4\] + 388: 78c083e7 ldursh w7, \[sp, #8\] + 38c: 78c103e7 ldursh w7, \[sp, #16\] + 390: 78c553e7 ldursh w7, \[sp, #85\] + 394: 78cff3e7 ldursh w7, \[sp, #255\] diff --git a/gas/testsuite/gas/aarch64/reloc-insn.d b/gas/testsuite/gas/aarch64/reloc-insn.d index f3382fb8f42..90dae355bf7 100644 --- a/gas/testsuite/gas/aarch64/reloc-insn.d +++ b/gas/testsuite/gas/aarch64/reloc-insn.d @@ -102,7 +102,7 @@ Disassembly of section \.text: e8: R_AARCH64_LDST8_ABS_LO12_NC xdata\+0x10 ec: 394000a5 ldrb w5, \[x5\] ec: R_AARCH64_LDST8_ABS_LO12_NC xdata\+0xff8 - f0: 397ffcc6 ldrb w6, \[x6,#4095\] + f0: 397ffcc6 ldrb w6, \[x6, #4095\] f4: 36000560 tbz w0, #0, 1a0 <lab> f8: b6f80001 tbz x1, #63, 0 <xlab> f8: R_AARCH64_TSTBR14 xlab @@ -137,10 +137,10 @@ Disassembly of section \.text: 158: 91200000 add x0, x0, #0x800 15c: d13ffc00 sub x0, x0, #0xfff 160: d41fffe1 svc #0xffff - 164: f8500420 ldr x0, \[x1\],#-256 - 168: f8500c20 ldr x0, \[x1,#-256\]! - 16c: f8500020 ldur x0, \[x1,#-256\] - 170: f97ffc20 ldr x0, \[x1,#32760\] + 164: f8500420 ldr x0, \[x1\], #-256 + 168: f8500c20 ldr x0, \[x1, #-256\]! + 16c: f8500020 ldur x0, \[x1, #-256\] + 170: f97ffc20 ldr x0, \[x1, #32760\] 174: 79400000 ldrh w0, \[x0\] 174: R_AARCH64_LDST16_ABS_LO12_NC \.text\+0x19c 178: b9400021 ldr w1, \[x1\] diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l index 5ecb9932f80..58739b370da 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.l +++ b/gas/testsuite/gas/aarch64/sve-invalid.l @@ -2,228 +2,228 @@ .*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2' .*: Error: operand mismatch -- `fmov z1,#1\.0' .*: Info: did you mean this\? -.*: Info: fmov z1\.s,#1\.000000000000000000e\+00 +.*: Info: fmov z1\.s, #1\.000000000000000000e\+00 .*: Info: other valid variant\(s\): -.*: Info: fmov z1\.d,#1\.000000000000000000e\+00 +.*: Info: fmov z1\.d, #1\.000000000000000000e\+00 .*: Error: operand mismatch -- `fmov z1,#0\.0' .*: Info: did you mean this\? -.*: Info: fmov z1\.s,#0\.0 +.*: Info: fmov z1\.s, #0\.0 .*: Info: other valid variant\(s\): -.*: Info: fmov z1\.d,#0\.0 +.*: Info: fmov z1\.d, #0\.0 .*: Error: missing predication type at operand 2 -- `not z0\.s,p1/' .*: Error: missing predication type at operand 2 -- `not z0\.s,p1/,z2\.s' .*: Error: unexpected character `c' in predication type at operand 2 -- `not z0\.s,p1/c,z2\.s' .*: Error: operand mismatch -- `movprfx z0\.h,z1\.h' .*: Info: did you mean this\? -.*: Info: movprfx z0,z1 +.*: Info: movprfx z0, z1 .*: Error: operand mismatch -- `movprfx z0,z1\.h' .*: Info: did you mean this\? -.*: Info: movprfx z0,z1 +.*: Info: movprfx z0, z1 .*: Error: operand mismatch -- `movprfx z0\.h,z1' .*: Info: did you mean this\? -.*: Info: movprfx z0,z1 +.*: Info: movprfx z0, z1 .*: Error: operand mismatch -- `movprfx z0\.h,z1\.s' .*: Info: did you mean this\? -.*: Info: movprfx z0,z1 +.*: Info: movprfx z0, z1 .*: Error: operand mismatch -- `movprfx z0,p1/m,z1' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/m,z1\.b +.*: Info: movprfx z0\.b, p1/m, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/z,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/z, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0,p1/z,z1' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/z,z1\.b +.*: Info: movprfx z0\.b, p1/z, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/m,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/m, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0\.b,p1/m,z1' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/m,z1\.b +.*: Info: movprfx z0\.b, p1/m, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/z,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/z, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0\.b,p1/z,z1' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/z,z1\.b +.*: Info: movprfx z0\.b, p1/z, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/m,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/m, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0,p1/m,z1\.b' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/m,z1\.b +.*: Info: movprfx z0\.b, p1/m, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/z,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/z, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0,p1/z,z1\.b' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/z,z1\.b +.*: Info: movprfx z0\.b, p1/z, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/m,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/m, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0\.h,p1/m,z1\.b' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/m,z1\.b +.*: Info: movprfx z0\.b, p1/m, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/z,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/z, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0\.h,p1/z,z1\.b' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/z,z1\.b +.*: Info: movprfx z0\.b, p1/z, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/m,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/m, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand mismatch -- `movprfx z0\.b,p1,z1\.b' .*: Info: did you mean this\? -.*: Info: movprfx z0\.b,p1/z,z1\.b +.*: Info: movprfx z0\.b, p1/z, z1\.b .*: Info: other valid variant\(s\): -.*: Info: movprfx z0\.b,p1/m,z1\.b -.*: Info: movprfx z0\.h,p1/z,z1\.h -.*: Info: movprfx z0\.h,p1/m,z1\.h -.*: Info: movprfx z0\.s,p1/z,z1\.s -.*: Info: movprfx z0\.s,p1/m,z1\.s -.*: Info: movprfx z0\.d,p1/z,z1\.d -.*: Info: movprfx z0\.d,p1/m,z1\.d +.*: Info: movprfx z0\.b, p1/m, z1\.b +.*: Info: movprfx z0\.h, p1/z, z1\.h +.*: Info: movprfx z0\.h, p1/m, z1\.h +.*: Info: movprfx z0\.s, p1/z, z1\.s +.*: Info: movprfx z0\.s, p1/m, z1\.s +.*: Info: movprfx z0\.d, p1/z, z1\.d +.*: Info: movprfx z0\.d, p1/m, z1\.d .*: Error: operand 1 must be an SVE vector register -- `movprfx p0,p1' .*: Error: operand mismatch -- `ldr p0\.b,\[x1\]' .*: Info: did you mean this\? -.*: Info: ldr p0,\[x1\] +.*: Info: ldr p0, \[x1\] .*: Error: operand mismatch -- `ldr z0\.b,\[x1\]' .*: Info: did you mean this\? -.*: Info: ldr z0,\[x1\] +.*: Info: ldr z0, \[x1\] .*: Error: operand mismatch -- `str p0\.b,\[x1\]' .*: Info: did you mean this\? -.*: Info: str p0,\[x1\] +.*: Info: str p0, \[x1\] .*: Error: operand mismatch -- `str z0\.b,\[x1\]' .*: Info: did you mean this\? -.*: Info: str z0,\[x1\] +.*: Info: str z0, \[x1\] .*: Error: operand mismatch -- `mov z0,b0' .*: Info: did you mean this\? -.*: Info: mov z0\.b,b0 +.*: Info: mov z0\.b, b0 .*: Info: other valid variant\(s\): -.*: Info: mov z0\.h,h0 -.*: Info: mov z0\.s,s0 -.*: Info: mov z0\.d,d0 +.*: Info: mov z0\.h, h0 +.*: Info: mov z0\.s, s0 +.*: Info: mov z0\.d, d0 .*: Error: operand mismatch -- `mov z0,z1' .*: Info: did you mean this\? -.*: Info: mov z0\.d,z1\.d +.*: Info: mov z0\.d, z1\.d .*: Error: operand mismatch -- `mov p0,p1' .*: Info: did you mean this\? -.*: Info: mov p0\.b,p1\.b +.*: Info: mov p0\.b, p1\.b .*: Error: operand mismatch -- `add z0,z0,z2' .*: Info: did you mean this\? -.*: Info: add z0\.b,z0\.b,z2\.b +.*: Info: add z0\.b, z0\.b, z2\.b .*: Info: other valid variant\(s\): -.*: Info: add z0\.h,z0\.h,z2\.h -.*: Info: add z0\.s,z0\.s,z2\.s -.*: Info: add z0\.d,z0\.d,z2\.d +.*: Info: add z0\.h, z0\.h, z2\.h +.*: Info: add z0\.s, z0\.s, z2\.s +.*: Info: add z0\.d, z0\.d, z2\.d .*: Error: operand mismatch -- `add z0,z0,#2' .*: Info: did you mean this\? -.*: Info: add z0\.b,z0\.b,#2 +.*: Info: add z0\.b, z0\.b, #2 .*: Info: other valid variant\(s\): -.*: Info: add z0\.h,z0\.h,#2 -.*: Info: add z0\.s,z0\.s,#2 -.*: Info: add z0\.d,z0\.d,#2 +.*: Info: add z0\.h, z0\.h, #2 +.*: Info: add z0\.s, z0\.s, #2 +.*: Info: add z0\.d, z0\.d, #2 .*: Error: operand mismatch -- `add z0,z1,z2' .*: Info: did you mean this\? -.*: Info: add z0\.b,z1\.b,z2\.b +.*: Info: add z0\.b, z1\.b, z2\.b .*: Info: other valid variant\(s\): -.*: Info: add z0\.h,z1\.h,z2\.h -.*: Info: add z0\.s,z1\.s,z2\.s -.*: Info: add z0\.d,z1\.d,z2\.d +.*: Info: add z0\.h, z1\.h, z2\.h +.*: Info: add z0\.s, z1\.s, z2\.s +.*: Info: add z0\.d, z1\.d, z2\.d .*: Error: operand 2 must be the same register as operand 1 -- `add z0,z1,#1' .*: Error: operand 2 must be the same register as operand 1 -- `add z0\.b,z1\.b,#1' .*: Error: operand mismatch -- `add z0\.b,z0\.h,#1' .*: Info: did you mean this\? -.*: Info: add z0\.b,z0\.b,#1 +.*: Info: add z0\.b, z0\.b, #1 .*: Info: other valid variant\(s\): -.*: Info: add z0\.h,z0\.h,#1 -.*: Info: add z0\.s,z0\.s,#1 -.*: Info: add z0\.d,z0\.d,#1 +.*: Info: add z0\.h, z0\.h, #1 +.*: Info: add z0\.s, z0\.s, #1 +.*: Info: add z0\.d, z0\.d, #1 .*: Error: constant expression required at operand 2 -- `mov z0\.b,z32\.b' .*: Error: operand 2 must be an SVE predicate register -- `mov p0\.b,p16\.b' .*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p8/z,z1\.b,z2\.b' .*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p15/z,z1\.b,z2\.b' .*: Error: operand mismatch -- `ld1w z0\.s,p0,\[x0\]' .*: Info: did you mean this\? -.*: Info: ld1w \{z0\.s\},p0/z,\[x0\] +.*: Info: ld1w \{z0\.s\}, p0/z, \[x0\] .*: Error: operand mismatch -- `ld1w z0\.s,p0/m,\[x0\]' .*: Info: did you mean this\? -.*: Info: ld1w \{z0\.s\},p0/z,\[x0\] +.*: Info: ld1w \{z0\.s\}, p0/z, \[x0\] .*: Error: operand mismatch -- `cmpeq p0\.b,p0,z1\.b,z2\.b' .*: Info: did you mean this\? -.*: Info: cmpeq p0\.b,p0/z,z1\.b,z2\.b +.*: Info: cmpeq p0\.b, p0/z, z1\.b, z2\.b .*: Info: other valid variant\(s\): -.*: Info: cmpeq p0\.h,p0/z,z1\.h,z2\.h -.*: Info: cmpeq p0\.s,p0/z,z1\.s,z2\.s -.*: Info: cmpeq p0\.d,p0/z,z1\.d,z2\.d +.*: Info: cmpeq p0\.h, p0/z, z1\.h, z2\.h +.*: Info: cmpeq p0\.s, p0/z, z1\.s, z2\.s +.*: Info: cmpeq p0\.d, p0/z, z1\.d, z2\.d .*: Error: operand mismatch -- `cmpeq p0\.b,p0/m,z1\.b,z2\.b' .*: Info: did you mean this\? -.*: Info: cmpeq p0\.b,p0/z,z1\.b,z2\.b +.*: Info: cmpeq p0\.b, p0/z, z1\.b, z2\.b .*: Info: other valid variant\(s\): -.*: Info: cmpeq p0\.h,p0/z,z1\.h,z2\.h -.*: Info: cmpeq p0\.s,p0/z,z1\.s,z2\.s -.*: Info: cmpeq p0\.d,p0/z,z1\.d,z2\.d +.*: Info: cmpeq p0\.h, p0/z, z1\.h, z2\.h +.*: Info: cmpeq p0\.s, p0/z, z1\.s, z2\.s +.*: Info: cmpeq p0\.d, p0/z, z1\.d, z2\.d .*: Error: operand mismatch -- `add z0\.s,p0,z0\.s,z1\.s' .*: Info: did you mean this\? -.*: Info: add z0\.s,p0/m,z0\.s,z1\.s +.*: Info: add z0\.s, p0/m, z0\.s, z1\.s .*: Info: other valid variant\(s\): -.*: Info: add z0\.b,p0/m,z0\.b,z1\.b -.*: Info: add z0\.h,p0/m,z0\.h,z1\.h -.*: Info: add z0\.d,p0/m,z0\.d,z1\.d +.*: Info: add z0\.b, p0/m, z0\.b, z1\.b +.*: Info: add z0\.h, p0/m, z0\.h, z1\.h +.*: Info: add z0\.d, p0/m, z0\.d, z1\.d .*: Error: operand mismatch -- `add z0\.s,p0/z,z0\.s,z1\.s' .*: Info: did you mean this\? -.*: Info: add z0\.s,p0/m,z0\.s,z1\.s +.*: Info: add z0\.s, p0/m, z0\.s, z1\.s .*: Info: other valid variant\(s\): -.*: Info: add z0\.b,p0/m,z0\.b,z1\.b -.*: Info: add z0\.h,p0/m,z0\.h,z1\.h -.*: Info: add z0\.d,p0/m,z0\.d,z1\.d +.*: Info: add z0\.b, p0/m, z0\.b, z1\.b +.*: Info: add z0\.h, p0/m, z0\.h, z1\.h +.*: Info: add z0\.d, p0/m, z0\.d, z1\.d .*: Error: operand mismatch -- `st1w z0\.s,p0/z,\[x0\]' .*: Info: did you mean this\? -.*: Info: st1w \{z0\.s\},p0,\[x0\] +.*: Info: st1w \{z0\.s\}, p0, \[x0\] .*: Error: operand mismatch -- `st1w z0\.s,p0/m,\[x0\]' .*: Info: did you mean this\? -.*: Info: st1w \{z0\.s\},p0,\[x0\] +.*: Info: st1w \{z0\.s\}, p0, \[x0\] .*: Error: missing type suffix at operand 1 -- `ld1b z0,p1/z,\[x1\]' .*: Error: missing type suffix at operand 1 -- `ld1h z0,p1/z,\[x1\]' .*: Error: missing type suffix at operand 1 -- `ld1w z0,p1/z,\[x1\]' diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d index e8068c8fb73..b8492e57bf3 100644 --- a/gas/testsuite/gas/aarch64/sve.d +++ b/gas/testsuite/gas/aarch64/sve.d @@ -1421,258 +1421,258 @@ Disassembly of section .*: .*: 04205420 addvl x0, x0, #-31 .*: 042057e0 addvl x0, x0, #-1 .*: 042057e0 addvl x0, x0, #-1 -.*: 0420a000 adr z0\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a000 adr z0\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a000 adr z0\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a001 adr z1\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a001 adr z1\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a001 adr z1\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a01f adr z31\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a01f adr z31\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a01f adr z31\.d, \[z0\.d,z0\.d,sxtw\] -.*: 0420a040 adr z0\.d, \[z2\.d,z0\.d,sxtw\] -.*: 0420a040 adr z0\.d, \[z2\.d,z0\.d,sxtw\] -.*: 0420a040 adr z0\.d, \[z2\.d,z0\.d,sxtw\] -.*: 0420a3e0 adr z0\.d, \[z31\.d,z0\.d,sxtw\] -.*: 0420a3e0 adr z0\.d, \[z31\.d,z0\.d,sxtw\] -.*: 0420a3e0 adr z0\.d, \[z31\.d,z0\.d,sxtw\] -.*: 0423a000 adr z0\.d, \[z0\.d,z3\.d,sxtw\] -.*: 0423a000 adr z0\.d, \[z0\.d,z3\.d,sxtw\] -.*: 0423a000 adr z0\.d, \[z0\.d,z3\.d,sxtw\] -.*: 043fa000 adr z0\.d, \[z0\.d,z31\.d,sxtw\] -.*: 043fa000 adr z0\.d, \[z0\.d,z31\.d,sxtw\] -.*: 043fa000 adr z0\.d, \[z0\.d,z31\.d,sxtw\] -.*: 0420a400 adr z0\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a400 adr z0\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a401 adr z1\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a401 adr z1\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a41f adr z31\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a41f adr z31\.d, \[z0\.d,z0\.d,sxtw #1\] -.*: 0420a440 adr z0\.d, \[z2\.d,z0\.d,sxtw #1\] -.*: 0420a440 adr z0\.d, \[z2\.d,z0\.d,sxtw #1\] -.*: 0420a7e0 adr z0\.d, \[z31\.d,z0\.d,sxtw #1\] -.*: 0420a7e0 adr z0\.d, \[z31\.d,z0\.d,sxtw #1\] -.*: 0423a400 adr z0\.d, \[z0\.d,z3\.d,sxtw #1\] -.*: 0423a400 adr z0\.d, \[z0\.d,z3\.d,sxtw #1\] -.*: 043fa400 adr z0\.d, \[z0\.d,z31\.d,sxtw #1\] -.*: 043fa400 adr z0\.d, \[z0\.d,z31\.d,sxtw #1\] -.*: 0420a800 adr z0\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a800 adr z0\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a801 adr z1\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a801 adr z1\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a81f adr z31\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a81f adr z31\.d, \[z0\.d,z0\.d,sxtw #2\] -.*: 0420a840 adr z0\.d, \[z2\.d,z0\.d,sxtw #2\] -.*: 0420a840 adr z0\.d, \[z2\.d,z0\.d,sxtw #2\] -.*: 0420abe0 adr z0\.d, \[z31\.d,z0\.d,sxtw #2\] -.*: 0420abe0 adr z0\.d, \[z31\.d,z0\.d,sxtw #2\] -.*: 0423a800 adr z0\.d, \[z0\.d,z3\.d,sxtw #2\] -.*: 0423a800 adr z0\.d, \[z0\.d,z3\.d,sxtw #2\] -.*: 043fa800 adr z0\.d, \[z0\.d,z31\.d,sxtw #2\] -.*: 043fa800 adr z0\.d, \[z0\.d,z31\.d,sxtw #2\] -.*: 0420ac00 adr z0\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac00 adr z0\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac01 adr z1\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac01 adr z1\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac1f adr z31\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac1f adr z31\.d, \[z0\.d,z0\.d,sxtw #3\] -.*: 0420ac40 adr z0\.d, \[z2\.d,z0\.d,sxtw #3\] -.*: 0420ac40 adr z0\.d, \[z2\.d,z0\.d,sxtw #3\] -.*: 0420afe0 adr z0\.d, \[z31\.d,z0\.d,sxtw #3\] -.*: 0420afe0 adr z0\.d, \[z31\.d,z0\.d,sxtw #3\] -.*: 0423ac00 adr z0\.d, \[z0\.d,z3\.d,sxtw #3\] -.*: 0423ac00 adr z0\.d, \[z0\.d,z3\.d,sxtw #3\] -.*: 043fac00 adr z0\.d, \[z0\.d,z31\.d,sxtw #3\] -.*: 043fac00 adr z0\.d, \[z0\.d,z31\.d,sxtw #3\] -.*: 0460a000 adr z0\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a000 adr z0\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a000 adr z0\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a001 adr z1\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a001 adr z1\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a001 adr z1\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a01f adr z31\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a01f adr z31\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a01f adr z31\.d, \[z0\.d,z0\.d,uxtw\] -.*: 0460a040 adr z0\.d, \[z2\.d,z0\.d,uxtw\] -.*: 0460a040 adr z0\.d, \[z2\.d,z0\.d,uxtw\] -.*: 0460a040 adr z0\.d, \[z2\.d,z0\.d,uxtw\] -.*: 0460a3e0 adr z0\.d, \[z31\.d,z0\.d,uxtw\] -.*: 0460a3e0 adr z0\.d, \[z31\.d,z0\.d,uxtw\] -.*: 0460a3e0 adr z0\.d, \[z31\.d,z0\.d,uxtw\] -.*: 0463a000 adr z0\.d, \[z0\.d,z3\.d,uxtw\] -.*: 0463a000 adr z0\.d, \[z0\.d,z3\.d,uxtw\] -.*: 0463a000 adr z0\.d, \[z0\.d,z3\.d,uxtw\] -.*: 047fa000 adr z0\.d, \[z0\.d,z31\.d,uxtw\] -.*: 047fa000 adr z0\.d, \[z0\.d,z31\.d,uxtw\] -.*: 047fa000 adr z0\.d, \[z0\.d,z31\.d,uxtw\] -.*: 0460a400 adr z0\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a400 adr z0\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a401 adr z1\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a401 adr z1\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a41f adr z31\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a41f adr z31\.d, \[z0\.d,z0\.d,uxtw #1\] -.*: 0460a440 adr z0\.d, \[z2\.d,z0\.d,uxtw #1\] -.*: 0460a440 adr z0\.d, \[z2\.d,z0\.d,uxtw #1\] -.*: 0460a7e0 adr z0\.d, \[z31\.d,z0\.d,uxtw #1\] -.*: 0460a7e0 adr z0\.d, \[z31\.d,z0\.d,uxtw #1\] -.*: 0463a400 adr z0\.d, \[z0\.d,z3\.d,uxtw #1\] -.*: 0463a400 adr z0\.d, \[z0\.d,z3\.d,uxtw #1\] -.*: 047fa400 adr z0\.d, \[z0\.d,z31\.d,uxtw #1\] -.*: 047fa400 adr z0\.d, \[z0\.d,z31\.d,uxtw #1\] -.*: 0460a800 adr z0\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a800 adr z0\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a801 adr z1\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a801 adr z1\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a81f adr z31\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a81f adr z31\.d, \[z0\.d,z0\.d,uxtw #2\] -.*: 0460a840 adr z0\.d, \[z2\.d,z0\.d,uxtw #2\] -.*: 0460a840 adr z0\.d, \[z2\.d,z0\.d,uxtw #2\] -.*: 0460abe0 adr z0\.d, \[z31\.d,z0\.d,uxtw #2\] -.*: 0460abe0 adr z0\.d, \[z31\.d,z0\.d,uxtw #2\] -.*: 0463a800 adr z0\.d, \[z0\.d,z3\.d,uxtw #2\] -.*: 0463a800 adr z0\.d, \[z0\.d,z3\.d,uxtw #2\] -.*: 047fa800 adr z0\.d, \[z0\.d,z31\.d,uxtw #2\] -.*: 047fa800 adr z0\.d, \[z0\.d,z31\.d,uxtw #2\] -.*: 0460ac00 adr z0\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac00 adr z0\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac01 adr z1\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac01 adr z1\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac1f adr z31\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac1f adr z31\.d, \[z0\.d,z0\.d,uxtw #3\] -.*: 0460ac40 adr z0\.d, \[z2\.d,z0\.d,uxtw #3\] -.*: 0460ac40 adr z0\.d, \[z2\.d,z0\.d,uxtw #3\] -.*: 0460afe0 adr z0\.d, \[z31\.d,z0\.d,uxtw #3\] -.*: 0460afe0 adr z0\.d, \[z31\.d,z0\.d,uxtw #3\] -.*: 0463ac00 adr z0\.d, \[z0\.d,z3\.d,uxtw #3\] -.*: 0463ac00 adr z0\.d, \[z0\.d,z3\.d,uxtw #3\] -.*: 047fac00 adr z0\.d, \[z0\.d,z31\.d,uxtw #3\] -.*: 047fac00 adr z0\.d, \[z0\.d,z31\.d,uxtw #3\] -.*: 04a0a000 adr z0\.s, \[z0\.s,z0\.s\] -.*: 04a0a000 adr z0\.s, \[z0\.s,z0\.s\] -.*: 04a0a000 adr z0\.s, \[z0\.s,z0\.s\] -.*: 04a0a001 adr z1\.s, \[z0\.s,z0\.s\] -.*: 04a0a001 adr z1\.s, \[z0\.s,z0\.s\] -.*: 04a0a001 adr z1\.s, \[z0\.s,z0\.s\] -.*: 04a0a01f adr z31\.s, \[z0\.s,z0\.s\] -.*: 04a0a01f adr z31\.s, \[z0\.s,z0\.s\] -.*: 04a0a01f adr z31\.s, \[z0\.s,z0\.s\] -.*: 04a0a040 adr z0\.s, \[z2\.s,z0\.s\] -.*: 04a0a040 adr z0\.s, \[z2\.s,z0\.s\] -.*: 04a0a040 adr z0\.s, \[z2\.s,z0\.s\] -.*: 04a0a3e0 adr z0\.s, \[z31\.s,z0\.s\] -.*: 04a0a3e0 adr z0\.s, \[z31\.s,z0\.s\] -.*: 04a0a3e0 adr z0\.s, \[z31\.s,z0\.s\] -.*: 04a3a000 adr z0\.s, \[z0\.s,z3\.s\] -.*: 04a3a000 adr z0\.s, \[z0\.s,z3\.s\] -.*: 04a3a000 adr z0\.s, \[z0\.s,z3\.s\] -.*: 04bfa000 adr z0\.s, \[z0\.s,z31\.s\] -.*: 04bfa000 adr z0\.s, \[z0\.s,z31\.s\] -.*: 04bfa000 adr z0\.s, \[z0\.s,z31\.s\] -.*: 04a0a400 adr z0\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a400 adr z0\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a401 adr z1\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a401 adr z1\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a41f adr z31\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a41f adr z31\.s, \[z0\.s,z0\.s,lsl #1\] -.*: 04a0a440 adr z0\.s, \[z2\.s,z0\.s,lsl #1\] -.*: 04a0a440 adr z0\.s, \[z2\.s,z0\.s,lsl #1\] -.*: 04a0a7e0 adr z0\.s, \[z31\.s,z0\.s,lsl #1\] -.*: 04a0a7e0 adr z0\.s, \[z31\.s,z0\.s,lsl #1\] -.*: 04a3a400 adr z0\.s, \[z0\.s,z3\.s,lsl #1\] -.*: 04a3a400 adr z0\.s, \[z0\.s,z3\.s,lsl #1\] -.*: 04bfa400 adr z0\.s, \[z0\.s,z31\.s,lsl #1\] -.*: 04bfa400 adr z0\.s, \[z0\.s,z31\.s,lsl #1\] -.*: 04a0a800 adr z0\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a800 adr z0\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a801 adr z1\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a801 adr z1\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a81f adr z31\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a81f adr z31\.s, \[z0\.s,z0\.s,lsl #2\] -.*: 04a0a840 adr z0\.s, \[z2\.s,z0\.s,lsl #2\] -.*: 04a0a840 adr z0\.s, \[z2\.s,z0\.s,lsl #2\] -.*: 04a0abe0 adr z0\.s, \[z31\.s,z0\.s,lsl #2\] -.*: 04a0abe0 adr z0\.s, \[z31\.s,z0\.s,lsl #2\] -.*: 04a3a800 adr z0\.s, \[z0\.s,z3\.s,lsl #2\] -.*: 04a3a800 adr z0\.s, \[z0\.s,z3\.s,lsl #2\] -.*: 04bfa800 adr z0\.s, \[z0\.s,z31\.s,lsl #2\] -.*: 04bfa800 adr z0\.s, \[z0\.s,z31\.s,lsl #2\] -.*: 04a0ac00 adr z0\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac00 adr z0\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac01 adr z1\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac01 adr z1\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac1f adr z31\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac1f adr z31\.s, \[z0\.s,z0\.s,lsl #3\] -.*: 04a0ac40 adr z0\.s, \[z2\.s,z0\.s,lsl #3\] -.*: 04a0ac40 adr z0\.s, \[z2\.s,z0\.s,lsl #3\] -.*: 04a0afe0 adr z0\.s, \[z31\.s,z0\.s,lsl #3\] -.*: 04a0afe0 adr z0\.s, \[z31\.s,z0\.s,lsl #3\] -.*: 04a3ac00 adr z0\.s, \[z0\.s,z3\.s,lsl #3\] -.*: 04a3ac00 adr z0\.s, \[z0\.s,z3\.s,lsl #3\] -.*: 04bfac00 adr z0\.s, \[z0\.s,z31\.s,lsl #3\] -.*: 04bfac00 adr z0\.s, \[z0\.s,z31\.s,lsl #3\] -.*: 04e0a000 adr z0\.d, \[z0\.d,z0\.d\] -.*: 04e0a000 adr z0\.d, \[z0\.d,z0\.d\] -.*: 04e0a000 adr z0\.d, \[z0\.d,z0\.d\] -.*: 04e0a001 adr z1\.d, \[z0\.d,z0\.d\] -.*: 04e0a001 adr z1\.d, \[z0\.d,z0\.d\] -.*: 04e0a001 adr z1\.d, \[z0\.d,z0\.d\] -.*: 04e0a01f adr z31\.d, \[z0\.d,z0\.d\] -.*: 04e0a01f adr z31\.d, \[z0\.d,z0\.d\] -.*: 04e0a01f adr z31\.d, \[z0\.d,z0\.d\] -.*: 04e0a040 adr z0\.d, \[z2\.d,z0\.d\] -.*: 04e0a040 adr z0\.d, \[z2\.d,z0\.d\] -.*: 04e0a040 adr z0\.d, \[z2\.d,z0\.d\] -.*: 04e0a3e0 adr z0\.d, \[z31\.d,z0\.d\] -.*: 04e0a3e0 adr z0\.d, \[z31\.d,z0\.d\] -.*: 04e0a3e0 adr z0\.d, \[z31\.d,z0\.d\] -.*: 04e3a000 adr z0\.d, \[z0\.d,z3\.d\] -.*: 04e3a000 adr z0\.d, \[z0\.d,z3\.d\] -.*: 04e3a000 adr z0\.d, \[z0\.d,z3\.d\] -.*: 04ffa000 adr z0\.d, \[z0\.d,z31\.d\] -.*: 04ffa000 adr z0\.d, \[z0\.d,z31\.d\] -.*: 04ffa000 adr z0\.d, \[z0\.d,z31\.d\] -.*: 04e0a400 adr z0\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a400 adr z0\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a401 adr z1\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a401 adr z1\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a41f adr z31\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a41f adr z31\.d, \[z0\.d,z0\.d,lsl #1\] -.*: 04e0a440 adr z0\.d, \[z2\.d,z0\.d,lsl #1\] -.*: 04e0a440 adr z0\.d, \[z2\.d,z0\.d,lsl #1\] -.*: 04e0a7e0 adr z0\.d, \[z31\.d,z0\.d,lsl #1\] -.*: 04e0a7e0 adr z0\.d, \[z31\.d,z0\.d,lsl #1\] -.*: 04e3a400 adr z0\.d, \[z0\.d,z3\.d,lsl #1\] -.*: 04e3a400 adr z0\.d, \[z0\.d,z3\.d,lsl #1\] -.*: 04ffa400 adr z0\.d, \[z0\.d,z31\.d,lsl #1\] -.*: 04ffa400 adr z0\.d, \[z0\.d,z31\.d,lsl #1\] -.*: 04e0a800 adr z0\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a800 adr z0\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a801 adr z1\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a801 adr z1\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a81f adr z31\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a81f adr z31\.d, \[z0\.d,z0\.d,lsl #2\] -.*: 04e0a840 adr z0\.d, \[z2\.d,z0\.d,lsl #2\] -.*: 04e0a840 adr z0\.d, \[z2\.d,z0\.d,lsl #2\] -.*: 04e0abe0 adr z0\.d, \[z31\.d,z0\.d,lsl #2\] -.*: 04e0abe0 adr z0\.d, \[z31\.d,z0\.d,lsl #2\] -.*: 04e3a800 adr z0\.d, \[z0\.d,z3\.d,lsl #2\] -.*: 04e3a800 adr z0\.d, \[z0\.d,z3\.d,lsl #2\] -.*: 04ffa800 adr z0\.d, \[z0\.d,z31\.d,lsl #2\] -.*: 04ffa800 adr z0\.d, \[z0\.d,z31\.d,lsl #2\] -.*: 04e0ac00 adr z0\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac00 adr z0\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac01 adr z1\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac01 adr z1\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac1f adr z31\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac1f adr z31\.d, \[z0\.d,z0\.d,lsl #3\] -.*: 04e0ac40 adr z0\.d, \[z2\.d,z0\.d,lsl #3\] -.*: 04e0ac40 adr z0\.d, \[z2\.d,z0\.d,lsl #3\] -.*: 04e0afe0 adr z0\.d, \[z31\.d,z0\.d,lsl #3\] -.*: 04e0afe0 adr z0\.d, \[z31\.d,z0\.d,lsl #3\] -.*: 04e3ac00 adr z0\.d, \[z0\.d,z3\.d,lsl #3\] -.*: 04e3ac00 adr z0\.d, \[z0\.d,z3\.d,lsl #3\] -.*: 04ffac00 adr z0\.d, \[z0\.d,z31\.d,lsl #3\] -.*: 04ffac00 adr z0\.d, \[z0\.d,z31\.d,lsl #3\] +.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\] +.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\] +.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\] +.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\] +.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\] +.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\] +.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\] +.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\] +.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\] +.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\] +.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\] +.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\] +.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\] +.*: 0420a400 adr z0\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a400 adr z0\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a401 adr z1\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a401 adr z1\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a41f adr z31\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a41f adr z31\.d, \[z0\.d, z0\.d, sxtw #1\] +.*: 0420a440 adr z0\.d, \[z2\.d, z0\.d, sxtw #1\] +.*: 0420a440 adr z0\.d, \[z2\.d, z0\.d, sxtw #1\] +.*: 0420a7e0 adr z0\.d, \[z31\.d, z0\.d, sxtw #1\] +.*: 0420a7e0 adr z0\.d, \[z31\.d, z0\.d, sxtw #1\] +.*: 0423a400 adr z0\.d, \[z0\.d, z3\.d, sxtw #1\] +.*: 0423a400 adr z0\.d, \[z0\.d, z3\.d, sxtw #1\] +.*: 043fa400 adr z0\.d, \[z0\.d, z31\.d, sxtw #1\] +.*: 043fa400 adr z0\.d, \[z0\.d, z31\.d, sxtw #1\] +.*: 0420a800 adr z0\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a800 adr z0\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a801 adr z1\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a801 adr z1\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a81f adr z31\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a81f adr z31\.d, \[z0\.d, z0\.d, sxtw #2\] +.*: 0420a840 adr z0\.d, \[z2\.d, z0\.d, sxtw #2\] +.*: 0420a840 adr z0\.d, \[z2\.d, z0\.d, sxtw #2\] +.*: 0420abe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #2\] +.*: 0420abe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #2\] +.*: 0423a800 adr z0\.d, \[z0\.d, z3\.d, sxtw #2\] +.*: 0423a800 adr z0\.d, \[z0\.d, z3\.d, sxtw #2\] +.*: 043fa800 adr z0\.d, \[z0\.d, z31\.d, sxtw #2\] +.*: 043fa800 adr z0\.d, \[z0\.d, z31\.d, sxtw #2\] +.*: 0420ac00 adr z0\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac00 adr z0\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac01 adr z1\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac01 adr z1\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac1f adr z31\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac1f adr z31\.d, \[z0\.d, z0\.d, sxtw #3\] +.*: 0420ac40 adr z0\.d, \[z2\.d, z0\.d, sxtw #3\] +.*: 0420ac40 adr z0\.d, \[z2\.d, z0\.d, sxtw #3\] +.*: 0420afe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #3\] +.*: 0420afe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #3\] +.*: 0423ac00 adr z0\.d, \[z0\.d, z3\.d, sxtw #3\] +.*: 0423ac00 adr z0\.d, \[z0\.d, z3\.d, sxtw #3\] +.*: 043fac00 adr z0\.d, \[z0\.d, z31\.d, sxtw #3\] +.*: 043fac00 adr z0\.d, \[z0\.d, z31\.d, sxtw #3\] +.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\] +.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\] +.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\] +.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\] +.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\] +.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\] +.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\] +.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\] +.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\] +.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\] +.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\] +.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\] +.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\] +.*: 0460a400 adr z0\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a400 adr z0\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a401 adr z1\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a401 adr z1\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a41f adr z31\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a41f adr z31\.d, \[z0\.d, z0\.d, uxtw #1\] +.*: 0460a440 adr z0\.d, \[z2\.d, z0\.d, uxtw #1\] +.*: 0460a440 adr z0\.d, \[z2\.d, z0\.d, uxtw #1\] +.*: 0460a7e0 adr z0\.d, \[z31\.d, z0\.d, uxtw #1\] +.*: 0460a7e0 adr z0\.d, \[z31\.d, z0\.d, uxtw #1\] +.*: 0463a400 adr z0\.d, \[z0\.d, z3\.d, uxtw #1\] +.*: 0463a400 adr z0\.d, \[z0\.d, z3\.d, uxtw #1\] +.*: 047fa400 adr z0\.d, \[z0\.d, z31\.d, uxtw #1\] +.*: 047fa400 adr z0\.d, \[z0\.d, z31\.d, uxtw #1\] +.*: 0460a800 adr z0\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a800 adr z0\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a801 adr z1\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a801 adr z1\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a81f adr z31\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a81f adr z31\.d, \[z0\.d, z0\.d, uxtw #2\] +.*: 0460a840 adr z0\.d, \[z2\.d, z0\.d, uxtw #2\] +.*: 0460a840 adr z0\.d, \[z2\.d, z0\.d, uxtw #2\] +.*: 0460abe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #2\] +.*: 0460abe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #2\] +.*: 0463a800 adr z0\.d, \[z0\.d, z3\.d, uxtw #2\] +.*: 0463a800 adr z0\.d, \[z0\.d, z3\.d, uxtw #2\] +.*: 047fa800 adr z0\.d, \[z0\.d, z31\.d, uxtw #2\] +.*: 047fa800 adr z0\.d, \[z0\.d, z31\.d, uxtw #2\] +.*: 0460ac00 adr z0\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac00 adr z0\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac01 adr z1\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac01 adr z1\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac1f adr z31\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac1f adr z31\.d, \[z0\.d, z0\.d, uxtw #3\] +.*: 0460ac40 adr z0\.d, \[z2\.d, z0\.d, uxtw #3\] +.*: 0460ac40 adr z0\.d, \[z2\.d, z0\.d, uxtw #3\] +.*: 0460afe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #3\] +.*: 0460afe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #3\] +.*: 0463ac00 adr z0\.d, \[z0\.d, z3\.d, uxtw #3\] +.*: 0463ac00 adr z0\.d, \[z0\.d, z3\.d, uxtw #3\] +.*: 047fac00 adr z0\.d, \[z0\.d, z31\.d, uxtw #3\] +.*: 047fac00 adr z0\.d, \[z0\.d, z31\.d, uxtw #3\] +.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\] +.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\] +.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\] +.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\] +.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\] +.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\] +.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\] +.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\] +.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\] +.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\] +.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\] +.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\] +.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\] +.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\] +.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\] +.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\] +.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\] +.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\] +.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\] +.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\] +.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\] +.*: 04a0a400 adr z0\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a400 adr z0\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a401 adr z1\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a401 adr z1\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a41f adr z31\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a41f adr z31\.s, \[z0\.s, z0\.s, lsl #1\] +.*: 04a0a440 adr z0\.s, \[z2\.s, z0\.s, lsl #1\] +.*: 04a0a440 adr z0\.s, \[z2\.s, z0\.s, lsl #1\] +.*: 04a0a7e0 adr z0\.s, \[z31\.s, z0\.s, lsl #1\] +.*: 04a0a7e0 adr z0\.s, \[z31\.s, z0\.s, lsl #1\] +.*: 04a3a400 adr z0\.s, \[z0\.s, z3\.s, lsl #1\] +.*: 04a3a400 adr z0\.s, \[z0\.s, z3\.s, lsl #1\] +.*: 04bfa400 adr z0\.s, \[z0\.s, z31\.s, lsl #1\] +.*: 04bfa400 adr z0\.s, \[z0\.s, z31\.s, lsl #1\] +.*: 04a0a800 adr z0\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a800 adr z0\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a801 adr z1\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a801 adr z1\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a81f adr z31\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a81f adr z31\.s, \[z0\.s, z0\.s, lsl #2\] +.*: 04a0a840 adr z0\.s, \[z2\.s, z0\.s, lsl #2\] +.*: 04a0a840 adr z0\.s, \[z2\.s, z0\.s, lsl #2\] +.*: 04a0abe0 adr z0\.s, \[z31\.s, z0\.s, lsl #2\] +.*: 04a0abe0 adr z0\.s, \[z31\.s, z0\.s, lsl #2\] +.*: 04a3a800 adr z0\.s, \[z0\.s, z3\.s, lsl #2\] +.*: 04a3a800 adr z0\.s, \[z0\.s, z3\.s, lsl #2\] +.*: 04bfa800 adr z0\.s, \[z0\.s, z31\.s, lsl #2\] +.*: 04bfa800 adr z0\.s, \[z0\.s, z31\.s, lsl #2\] +.*: 04a0ac00 adr z0\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac00 adr z0\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac01 adr z1\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac01 adr z1\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac1f adr z31\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac1f adr z31\.s, \[z0\.s, z0\.s, lsl #3\] +.*: 04a0ac40 adr z0\.s, \[z2\.s, z0\.s, lsl #3\] +.*: 04a0ac40 adr z0\.s, \[z2\.s, z0\.s, lsl #3\] +.*: 04a0afe0 adr z0\.s, \[z31\.s, z0\.s, lsl #3\] +.*: 04a0afe0 adr z0\.s, \[z31\.s, z0\.s, lsl #3\] +.*: 04a3ac00 adr z0\.s, \[z0\.s, z3\.s, lsl #3\] +.*: 04a3ac00 adr z0\.s, \[z0\.s, z3\.s, lsl #3\] +.*: 04bfac00 adr z0\.s, \[z0\.s, z31\.s, lsl #3\] +.*: 04bfac00 adr z0\.s, \[z0\.s, z31\.s, lsl #3\] +.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\] +.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\] +.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\] +.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\] +.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\] +.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\] +.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\] +.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\] +.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\] +.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\] +.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\] +.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\] +.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\] +.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\] +.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\] +.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\] +.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\] +.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\] +.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\] +.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\] +.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\] +.*: 04e0a400 adr z0\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a400 adr z0\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a401 adr z1\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a401 adr z1\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a41f adr z31\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a41f adr z31\.d, \[z0\.d, z0\.d, lsl #1\] +.*: 04e0a440 adr z0\.d, \[z2\.d, z0\.d, lsl #1\] +.*: 04e0a440 adr z0\.d, \[z2\.d, z0\.d, lsl #1\] +.*: 04e0a7e0 adr z0\.d, \[z31\.d, z0\.d, lsl #1\] +.*: 04e0a7e0 adr z0\.d, \[z31\.d, z0\.d, lsl #1\] +.*: 04e3a400 adr z0\.d, \[z0\.d, z3\.d, lsl #1\] +.*: 04e3a400 adr z0\.d, \[z0\.d, z3\.d, lsl #1\] +.*: 04ffa400 adr z0\.d, \[z0\.d, z31\.d, lsl #1\] +.*: 04ffa400 adr z0\.d, \[z0\.d, z31\.d, lsl #1\] +.*: 04e0a800 adr z0\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a800 adr z0\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a801 adr z1\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a801 adr z1\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a81f adr z31\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a81f adr z31\.d, \[z0\.d, z0\.d, lsl #2\] +.*: 04e0a840 adr z0\.d, \[z2\.d, z0\.d, lsl #2\] +.*: 04e0a840 adr z0\.d, \[z2\.d, z0\.d, lsl #2\] +.*: 04e0abe0 adr z0\.d, \[z31\.d, z0\.d, lsl #2\] +.*: 04e0abe0 adr z0\.d, \[z31\.d, z0\.d, lsl #2\] +.*: 04e3a800 adr z0\.d, \[z0\.d, z3\.d, lsl #2\] +.*: 04e3a800 adr z0\.d, \[z0\.d, z3\.d, lsl #2\] +.*: 04ffa800 adr z0\.d, \[z0\.d, z31\.d, lsl #2\] +.*: 04ffa800 adr z0\.d, \[z0\.d, z31\.d, lsl #2\] +.*: 04e0ac00 adr z0\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac00 adr z0\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac01 adr z1\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac01 adr z1\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac1f adr z31\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac1f adr z31\.d, \[z0\.d, z0\.d, lsl #3\] +.*: 04e0ac40 adr z0\.d, \[z2\.d, z0\.d, lsl #3\] +.*: 04e0ac40 adr z0\.d, \[z2\.d, z0\.d, lsl #3\] +.*: 04e0afe0 adr z0\.d, \[z31\.d, z0\.d, lsl #3\] +.*: 04e0afe0 adr z0\.d, \[z31\.d, z0\.d, lsl #3\] +.*: 04e3ac00 adr z0\.d, \[z0\.d, z3\.d, lsl #3\] +.*: 04e3ac00 adr z0\.d, \[z0\.d, z3\.d, lsl #3\] +.*: 04ffac00 adr z0\.d, \[z0\.d, z31\.d, lsl #3\] +.*: 04ffac00 adr z0\.d, \[z0\.d, z31\.d, lsl #3\] .*: 04203000 and z0\.d, z0\.d, z0\.d .*: 04203000 and z0\.d, z0\.d, z0\.d .*: 04203001 and z1\.d, z0\.d, z0\.d @@ -12155,276 +12155,276 @@ Disassembly of section .*: .*: 05e38060 lastb d0, p0, z3\.d .*: 05e383e0 lastb d0, p0, z31\.d .*: 05e383e0 lastb d0, p0, z31\.d -.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0,x30\] -.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0,x30\] -.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0,x30\] -.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0,x30\] -.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0,x30\] -.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0,x30\] -.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0,x30\] -.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0,x30\] -.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0,x30\] -.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0,x30\] -.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0,x30\] -.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0,x30\] -.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0,z31\.d\] +.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\] +.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\] +.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\] +.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\] +.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\] +.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\] +.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\] +.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\] +.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\] +.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\] +.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\] +.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\] +.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\] .*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\] @@ -12449,14 +12449,14 @@ Disassembly of section .*: .*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\] -.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#31\] -.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s,#31\] +.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #31\] +.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #31\] .*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\] .*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\] .*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\] @@ -12488,14 +12488,14 @@ Disassembly of section .*: .*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\] .*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\] .*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\] -.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] -.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] +.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] +.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] .*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\] .*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\] .*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\] @@ -12527,14 +12527,14 @@ Disassembly of section .*: .*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\] .*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\] .*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\] -.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\] .*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\] .*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\] @@ -12566,14 +12566,14 @@ Disassembly of section .*: .*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\] .*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\] .*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\] -.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\] .*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\] .*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\] @@ -12605,14 +12605,14 @@ Disassembly of section .*: .*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\] .*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\] .*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\] -.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\] .*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\] .*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\] @@ -12637,188 +12637,188 @@ Disassembly of section .*: .*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\] .*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\] .*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\] -.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\] -.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\] -.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\] -.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\] -.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\] -.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\] -.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\] -.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\] -.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\] -.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\] -.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\] -.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\] -.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\] -.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\] -.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\] -.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\] -.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\] -.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\] -.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\] -.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\] -.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\] -.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\] -.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\] -.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\] -.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\] -.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\] -.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\] -.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\] -.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\] -.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\] -.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\] -.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\] -.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\] +.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\] +.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\] +.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\] +.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\] +.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\] +.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\] +.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\] +.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\] +.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\] +.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\] +.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\] +.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\] +.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\] +.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\] +.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\] +.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\] +.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\] +.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\] +.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\] +.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\] +.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\] +.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\] +.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\] +.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\] +.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\] +.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\] +.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\] +.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\] +.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\] +.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\] +.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\] +.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\] +.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\] .*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\] .*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\] .*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\] @@ -12850,14 +12850,14 @@ Disassembly of section .*: .*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\] .*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\] .*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\] -.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\] .*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\] .*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\] @@ -12882,332 +12882,332 @@ Disassembly of section .*: .*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\] .*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\] .*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\] -.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#120\] -.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#120\] -.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#128\] -.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#128\] -.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#136\] -.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#136\] -.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#248\] -.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d,#248\] -.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0,x30,lsl #1\] -.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0,x30,lsl #1\] -.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0,x30,lsl #1\] -.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0,x30,lsl #1\] -.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] -.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] +.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #120\] +.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #120\] +.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #128\] +.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #128\] +.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #136\] +.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #136\] +.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #248\] +.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #248\] +.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0, x30, lsl #1\] +.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0, x30, lsl #1\] +.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0, x30, lsl #1\] +.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0, x30, lsl #1\] +.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] +.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] .*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\] @@ -13232,14 +13232,14 @@ Disassembly of section .*: .*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\] -.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#62\] -.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s,#62\] +.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #62\] +.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #62\] .*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\] .*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\] .*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\] @@ -13271,14 +13271,14 @@ Disassembly of section .*: .*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\] .*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\] .*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\] -.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\] .*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\] .*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\] @@ -13310,14 +13310,14 @@ Disassembly of section .*: .*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\] .*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\] .*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\] -.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\] .*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\] .*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\] @@ -13349,14 +13349,14 @@ Disassembly of section .*: .*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\] .*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\] .*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\] -.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\] @@ -13381,14 +13381,14 @@ Disassembly of section .*: .*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\] -.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d,#62\] +.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #62\] .*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\] .*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\] .*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\] @@ -13413,14 +13413,14 @@ Disassembly of section .*: .*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\] .*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\] .*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\] -.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0,#31\] -.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0,#31\] -.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0,#32\] -.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0,#32\] -.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0,#33\] -.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0,#33\] -.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0,#63\] -.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0,#63\] +.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #31\] +.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #31\] +.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0, #32\] +.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0, #32\] +.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0, #33\] +.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0, #33\] +.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #63\] +.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #63\] .*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\] .*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\] .*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\] @@ -13445,14 +13445,14 @@ Disassembly of section .*: .*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\] .*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\] .*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\] -.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0,#31\] -.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0,#31\] -.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0,#32\] -.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0,#32\] -.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0,#33\] -.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0,#33\] -.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0,#63\] -.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0,#63\] +.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #31\] +.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #31\] +.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0, #32\] +.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0, #32\] +.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0, #33\] +.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0, #33\] +.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #63\] +.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #63\] .*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\] .*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\] .*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\] @@ -13477,14 +13477,14 @@ Disassembly of section .*: .*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\] .*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\] .*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\] -.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0,#31\] -.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0,#31\] -.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0,#32\] -.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0,#32\] -.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0,#33\] -.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0,#33\] -.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0,#63\] -.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0,#63\] +.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #31\] +.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #31\] +.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0, #32\] +.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0, #32\] +.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0, #33\] +.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0, #33\] +.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #63\] +.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #63\] .*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\] .*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\] .*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\] @@ -13509,14 +13509,14 @@ Disassembly of section .*: .*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\] .*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\] .*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\] -.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0,#31\] -.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0,#31\] -.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0,#32\] -.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0,#32\] -.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0,#33\] -.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0,#33\] -.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0,#63\] -.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0,#63\] +.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #31\] +.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #31\] +.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0, #32\] +.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0, #32\] +.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0, #33\] +.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0, #33\] +.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #63\] +.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #63\] .*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\] .*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\] .*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\] @@ -13541,14 +13541,14 @@ Disassembly of section .*: .*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\] .*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\] .*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\] -.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0,#248\] -.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0,#248\] -.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0,#256\] -.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0,#256\] -.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0,#264\] -.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0,#264\] -.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0,#504\] -.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0,#504\] +.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0, #248\] +.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0, #248\] +.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0, #256\] +.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0, #256\] +.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0, #264\] +.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0, #264\] +.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0, #504\] +.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0, #504\] .*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\] .*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\] .*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\] @@ -13573,14 +13573,14 @@ Disassembly of section .*: .*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\] .*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\] .*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\] -.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0,#62\] -.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0,#62\] -.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0,#64\] -.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0,#64\] -.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0,#66\] -.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0,#66\] -.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0,#126\] -.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0,#126\] +.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0, #62\] +.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0, #62\] +.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0, #64\] +.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0, #64\] +.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0, #66\] +.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0, #66\] +.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0, #126\] +.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0, #126\] .*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\] .*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\] .*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\] @@ -13605,14 +13605,14 @@ Disassembly of section .*: .*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\] .*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\] .*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\] -.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0,#62\] -.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0,#62\] -.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0,#64\] -.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0,#64\] -.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0,#66\] -.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0,#66\] -.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0,#126\] -.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0,#126\] +.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0, #62\] +.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0, #62\] +.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0, #64\] +.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0, #64\] +.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0, #66\] +.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0, #66\] +.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0, #126\] +.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0, #126\] .*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\] .*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\] .*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\] @@ -13637,14 +13637,14 @@ Disassembly of section .*: .*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\] .*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\] .*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\] -.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0,#62\] -.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0,#62\] -.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0,#64\] -.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0,#64\] -.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0,#66\] -.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0,#66\] -.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0,#126\] -.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0,#126\] +.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0, #62\] +.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0, #62\] +.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0, #64\] +.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0, #64\] +.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0, #66\] +.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0, #66\] +.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0, #126\] +.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0, #126\] .*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\] .*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\] .*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\] @@ -13669,14 +13669,14 @@ Disassembly of section .*: .*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\] .*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\] .*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\] -.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0,#31\] -.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0,#31\] -.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0,#32\] -.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0,#32\] -.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0,#33\] -.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0,#33\] -.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0,#63\] -.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0,#63\] +.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #31\] +.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #31\] +.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0, #32\] +.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0, #32\] +.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0, #33\] +.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0, #33\] +.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #63\] +.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #63\] .*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\] .*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\] .*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\] @@ -13701,14 +13701,14 @@ Disassembly of section .*: .*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\] .*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\] .*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\] -.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0,#31\] -.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0,#31\] -.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0,#32\] -.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0,#32\] -.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0,#33\] -.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0,#33\] -.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0,#63\] -.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0,#63\] +.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #31\] +.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #31\] +.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #32\] +.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #32\] +.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #33\] +.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #33\] +.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #63\] +.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #63\] .*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\] .*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\] .*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\] @@ -13733,14 +13733,14 @@ Disassembly of section .*: .*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\] .*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\] .*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\] -.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0,#31\] -.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0,#31\] -.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0,#32\] -.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0,#32\] -.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0,#33\] -.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0,#33\] -.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0,#63\] -.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0,#63\] +.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #31\] +.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #31\] +.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #32\] +.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #32\] +.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #33\] +.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #33\] +.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #63\] +.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #63\] .*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\] .*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\] .*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\] @@ -13765,14 +13765,14 @@ Disassembly of section .*: .*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\] .*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\] .*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\] -.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0,#62\] -.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0,#62\] -.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0,#64\] -.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0,#64\] -.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0,#66\] -.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0,#66\] -.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0,#126\] -.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0,#126\] +.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #62\] +.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #62\] +.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0, #64\] +.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0, #64\] +.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0, #66\] +.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0, #66\] +.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #126\] +.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #126\] .*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\] .*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\] .*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\] @@ -13797,14 +13797,14 @@ Disassembly of section .*: .*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\] .*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\] .*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\] -.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0,#62\] -.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0,#62\] -.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0,#64\] -.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0,#64\] -.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0,#66\] -.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0,#66\] -.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0,#126\] -.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0,#126\] +.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #62\] +.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #62\] +.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #64\] +.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #64\] +.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #66\] +.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #66\] +.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #126\] +.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #126\] .*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\] .*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\] .*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\] @@ -13829,14 +13829,14 @@ Disassembly of section .*: .*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\] .*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\] .*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\] -.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0,#124\] -.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0,#124\] -.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0,#128\] -.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0,#128\] -.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0,#132\] -.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0,#132\] -.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0,#252\] -.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0,#252\] +.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #124\] +.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #124\] +.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0, #128\] +.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0, #128\] +.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0, #132\] +.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0, #132\] +.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\] +.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\] .*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\] .*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\] .*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\] @@ -13861,14 +13861,14 @@ Disassembly of section .*: .*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\] .*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\] .*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\] -.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0,#124\] -.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0,#124\] -.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0,#128\] -.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0,#128\] -.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0,#132\] -.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0,#132\] -.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0,#252\] -.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0,#252\] +.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #124\] +.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #124\] +.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0, #128\] +.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0, #128\] +.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0, #132\] +.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0, #132\] +.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #252\] +.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #252\] .*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\] .*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\] .*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\] @@ -13893,254 +13893,254 @@ Disassembly of section .*: .*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\] .*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\] .*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\] -.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0,#124\] -.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0,#124\] -.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0,#128\] -.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0,#128\] -.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0,#132\] -.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0,#132\] -.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0,#252\] -.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0,#252\] -.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0,x30\] -.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0,x30\] -.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0,x30\] -.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0,x30\] -.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0,x30\] -.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0,x30\] -.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0,x30\] -.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0,x30\] -.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0,x30\] -.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] +.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #124\] +.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #124\] +.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0, #128\] +.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0, #128\] +.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0, #132\] +.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0, #132\] +.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #252\] +.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #252\] +.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\] +.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\] +.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\] +.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\] +.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\] +.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\] +.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\] +.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\] +.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\] +.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] .*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\] .*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\] .*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\] @@ -14165,14 +14165,14 @@ Disassembly of section .*: .*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\] .*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\] .*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\] -.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#31\] -.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s,#31\] +.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #31\] +.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #31\] .*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\] .*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\] .*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\] @@ -14204,14 +14204,14 @@ Disassembly of section .*: .*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\] .*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\] .*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\] -.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\] .*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\] .*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\] @@ -14243,14 +14243,14 @@ Disassembly of section .*: .*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\] .*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\] .*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\] -.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\] .*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\] .*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\] @@ -14282,14 +14282,14 @@ Disassembly of section .*: .*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\] .*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\] .*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\] -.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\] .*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\] .*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\] @@ -14314,311 +14314,311 @@ Disassembly of section .*: .*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\] .*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\] .*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\] -.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0,x30,lsl #1\] -.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0,x30,lsl #1\] -.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0,x30,lsl #1\] -.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0,x30,lsl #1\] -.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] -.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] +.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0, x30, lsl #1\] +.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0, x30, lsl #1\] +.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0, x30, lsl #1\] +.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0, x30, lsl #1\] +.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] +.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] .*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\] @@ -14643,14 +14643,14 @@ Disassembly of section .*: .*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\] -.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#62\] -.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s,#62\] +.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #62\] +.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #62\] .*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\] .*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\] .*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\] @@ -14682,14 +14682,14 @@ Disassembly of section .*: .*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\] .*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\] .*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\] -.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\] .*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\] .*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\] @@ -14721,14 +14721,14 @@ Disassembly of section .*: .*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\] .*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\] .*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\] -.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\] @@ -14753,188 +14753,188 @@ Disassembly of section .*: .*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\] -.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0,x30,lsl #2\] -.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0,x30,lsl #2\] -.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] -.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] +.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0, x30, lsl #2\] +.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0, x30, lsl #2\] +.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] +.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] .*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\] .*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\] .*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\] @@ -14966,14 +14966,14 @@ Disassembly of section .*: .*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\] .*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\] .*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\] -.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\] .*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\] .*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\] @@ -14998,311 +14998,311 @@ Disassembly of section .*: .*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\] .*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\] .*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\] -.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\] -.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\] -.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\] -.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\] -.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\] -.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\] -.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\] -.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\] -.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\] -.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\] -.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\] -.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\] -.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\] -.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\] -.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\] -.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\] -.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\] -.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\] -.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\] -.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\] -.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\] -.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\] -.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\] -.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\] -.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0,x30,lsl #2\] -.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0,x30,lsl #2\] -.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] -.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] +.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\] +.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\] +.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\] +.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\] +.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\] +.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\] +.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\] +.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\] +.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\] +.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\] +.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\] +.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\] +.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\] +.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\] +.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\] +.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\] +.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\] +.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\] +.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\] +.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\] +.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\] +.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\] +.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\] +.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\] +.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0, x30, lsl #2\] +.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0, x30, lsl #2\] +.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] +.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] .*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\] .*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\] .*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\] @@ -15327,14 +15327,14 @@ Disassembly of section .*: .*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\] .*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\] .*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\] -.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#60\] -.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#60\] -.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#64\] -.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#64\] -.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#68\] -.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#68\] -.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#124\] -.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s,#124\] +.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #60\] +.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #60\] +.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #64\] +.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #64\] +.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #68\] +.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #68\] +.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #124\] +.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #124\] .*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\] .*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\] .*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\] @@ -15366,14 +15366,14 @@ Disassembly of section .*: .*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\] .*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\] .*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\] -.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\] .*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\] .*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\] @@ -15405,14 +15405,14 @@ Disassembly of section .*: .*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\] .*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\] .*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\] -.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\] .*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\] .*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\] @@ -15437,57 +15437,57 @@ Disassembly of section .*: .*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\] .*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\] .*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\] -.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0,x0\] -.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0,x0\] -.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0,x0\] -.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0,x0\] -.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0,x0\] -.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0,x0\] -.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0,x0\] -.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0,x0\] -.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0,x0\] -.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0,x0\] -.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0,x0\] -.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0,x0\] -.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0,x0\] -.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3,x0\] -.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3,x0\] -.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3,x0\] -.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3,x0\] -.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3,x0\] -.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp,x0\] -.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp,x0\] -.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp,x0\] -.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp,x0\] -.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp,x0\] -.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x4\] -.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x4\] -.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x4\] -.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x4\] -.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x4\] -.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x30\] -.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x30\] -.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x30\] -.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x30\] -.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,x30\] +.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\] +.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\] +.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\] +.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\] +.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\] +.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\] +.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\] +.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\] +.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\] +.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\] +.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\] +.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\] +.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\] +.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\] +.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\] +.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\] +.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\] +.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\] +.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\] +.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\] +.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\] +.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\] +.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\] +.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\] +.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\] +.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\] +.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\] +.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\] +.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\] +.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\] +.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\] +.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\] +.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\] .*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\] .*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\] .*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\] @@ -15534,44 +15534,44 @@ Disassembly of section .*: .*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\] .*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\] .*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\] -.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\] -.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\] -.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\] -.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\] -.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\] -.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\] -.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\] -.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\] -.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\] -.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\] -.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\] -.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\] -.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\] +.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\] +.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\] +.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\] +.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\] +.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\] +.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\] +.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\] +.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\] +.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\] +.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\] +.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\] +.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\] +.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\] .*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\] .*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\] .*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\] @@ -15618,44 +15618,44 @@ Disassembly of section .*: .*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\] .*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\] .*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\] -.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\] -.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\] -.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\] -.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\] -.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\] -.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\] -.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\] -.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\] -.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\] -.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\] -.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\] -.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\] -.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\] +.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\] +.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\] +.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\] +.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\] +.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\] +.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\] +.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\] +.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\] +.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\] +.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\] +.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\] +.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\] +.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\] .*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\] .*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\] .*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\] @@ -15702,44 +15702,44 @@ Disassembly of section .*: .*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\] .*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\] .*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\] -.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\] -.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\] -.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\] -.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\] -.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\] -.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\] -.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\] -.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\] -.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\] -.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\] -.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\] -.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\] -.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\] +.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\] +.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\] +.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\] +.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\] +.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\] +.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\] +.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\] +.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\] +.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\] +.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\] +.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\] +.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\] +.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\] .*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\] .*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\] .*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\] @@ -15786,61 +15786,61 @@ Disassembly of section .*: .*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\] .*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\] .*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\] -.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\] -.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\] -.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\] -.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\] -.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\] -.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\] -.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\] -.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\] -.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\] -.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\] -.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\] -.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\] -.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x0\] -.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x0\] -.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x0\] -.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x0\] -.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x0\] -.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\] -.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0,x0\] -.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0,x0\] -.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0,x0\] -.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0,x0\] -.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0,x0\] -.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0,x0\] -.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0,x0\] -.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0,x0\] -.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0,x0\] -.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0,x0\] -.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3,x0\] -.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3,x0\] -.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3,x0\] -.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3,x0\] -.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3,x0\] -.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp,x0\] -.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp,x0\] -.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp,x0\] -.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp,x0\] -.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp,x0\] -.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x4\] -.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x4\] -.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x4\] -.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x4\] -.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x4\] -.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x30\] -.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x30\] -.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x30\] -.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x30\] -.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,x30\] +.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\] +.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\] +.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\] +.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\] +.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\] +.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\] +.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\] +.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\] +.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\] +.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\] +.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\] +.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\] +.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\] +.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\] +.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\] +.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\] +.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\] +.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\] +.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\] +.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\] +.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\] +.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\] +.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\] +.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\] +.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\] +.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\] +.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\] +.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\] +.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\] +.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\] +.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\] +.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\] +.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\] +.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\] +.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\] +.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\] +.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\] +.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\] +.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\] +.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\] +.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\] +.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\] +.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\] +.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\] +.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\] +.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\] +.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\] +.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\] .*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\] .*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\] .*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\] @@ -15887,44 +15887,44 @@ Disassembly of section .*: .*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\] .*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\] .*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\] -.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\] -.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\] -.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\] -.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\] -.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\] -.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\] -.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\] -.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\] -.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\] -.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\] -.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\] -.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\] -.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\] +.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\] +.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\] +.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\] +.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\] +.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\] +.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\] +.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\] +.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\] +.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\] +.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\] +.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\] +.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\] +.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\] .*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\] .*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\] .*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\] @@ -15971,44 +15971,44 @@ Disassembly of section .*: .*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\] .*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\] .*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\] -.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\] -.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\] -.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\] -.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\] -.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\] -.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\] -.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\] -.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\] -.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\] -.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\] -.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\] -.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\] -.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\] +.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\] +.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\] +.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\] +.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\] +.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\] +.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\] +.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\] +.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\] +.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\] +.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\] +.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\] +.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\] +.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\] .*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\] .*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\] .*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\] @@ -16055,44 +16055,44 @@ Disassembly of section .*: .*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\] .*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\] .*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\] -.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\] -.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\] -.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\] -.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\] -.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\] -.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\] -.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\] -.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\] -.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\] -.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\] -.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\] -.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\] -.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\] +.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\] +.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\] +.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\] +.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\] +.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\] +.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\] +.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\] +.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\] +.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\] +.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\] +.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\] +.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\] +.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\] .*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\] .*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\] .*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\] @@ -16139,61 +16139,61 @@ Disassembly of section .*: .*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\] .*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\] .*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\] -.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\] -.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\] -.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\] -.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\] -.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\] -.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\] -.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\] -.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\] -.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\] -.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\] -.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\] -.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\] -.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x0\] -.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0,x0\] -.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0,x0\] -.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0,x0\] -.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0,x0\] -.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0,x0\] -.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\] -.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0,x0\] -.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0,x0\] -.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0,x0\] -.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0,x0\] -.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0,x0\] -.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0,x0\] -.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0,x0\] -.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0,x0\] -.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0,x0\] -.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0,x0\] -.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3,x0\] -.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3,x0\] -.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3,x0\] -.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3,x0\] -.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3,x0\] -.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp,x0\] -.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp,x0\] -.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp,x0\] -.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp,x0\] -.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp,x0\] -.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x4\] -.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x4\] -.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x4\] -.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x4\] -.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x4\] -.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x30\] -.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x30\] -.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x30\] -.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x30\] -.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,x30\] +.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\] +.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\] +.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\] +.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\] +.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\] +.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\] +.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\] +.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\] +.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\] +.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\] +.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\] +.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\] +.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\] +.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\] +.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\] +.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\] +.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\] +.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\] +.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\] +.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\] +.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\] +.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\] +.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\] +.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\] +.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\] +.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\] +.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\] +.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\] +.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\] +.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\] +.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\] +.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\] +.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\] +.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\] +.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\] +.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\] +.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\] +.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\] +.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\] +.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\] +.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\] +.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\] +.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\] +.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\] +.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\] +.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\] +.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\] +.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\] +.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\] .*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\] .*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\] .*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\] @@ -16240,44 +16240,44 @@ Disassembly of section .*: .*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\] .*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\] .*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\] -.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\] -.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\] -.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\] -.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\] -.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\] -.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\] -.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\] -.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\] -.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\] -.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\] -.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\] -.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\] -.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\] +.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\] +.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\] +.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\] +.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\] +.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\] +.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\] +.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\] +.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\] +.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\] +.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\] +.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\] +.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\] +.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\] .*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\] .*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\] .*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\] @@ -16324,44 +16324,44 @@ Disassembly of section .*: .*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\] .*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\] .*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\] -.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\] -.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\] -.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\] -.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\] -.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\] -.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\] -.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\] -.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\] -.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\] -.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\] -.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\] -.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\] -.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\] +.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\] +.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\] +.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\] +.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\] +.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\] +.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\] +.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\] +.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\] +.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\] +.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\] +.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\] +.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\] +.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\] .*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\] .*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\] .*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\] @@ -16408,44 +16408,44 @@ Disassembly of section .*: .*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\] .*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\] .*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\] -.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\] -.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\] -.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\] -.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\] -.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\] -.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\] -.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\] -.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\] -.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\] -.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\] -.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\] -.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\] -.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\] +.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\] +.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\] +.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\] +.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\] +.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\] +.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\] +.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\] +.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\] +.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\] +.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\] +.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\] +.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\] +.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\] .*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\] .*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\] .*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\] @@ -16492,288 +16492,288 @@ Disassembly of section .*: .*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\] .*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\] .*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\] -.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\] -.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\] -.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\] -.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\] -.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\] -.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\] -.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\] -.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\] -.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\] -.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\] -.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\] -.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\] -.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0,xzr\] -.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0,xzr\] -.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0,xzr\] -.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0,x0\] -.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0,x0\] -.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0,x0\] -.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0,x0\] -.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0,x0\] -.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3,x0\] -.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp,x0\] -.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0,x4\] -.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0,xzr\] -.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0,xzr\] -.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0,xzr\] -.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0,x0\] -.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0,x0\] -.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0,x0\] -.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0,x0\] -.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0,x0\] -.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3,x0\] -.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp,x0\] -.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0,x4\] -.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0,x0\] -.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0,x0\] -.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0,x0\] -.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0,x0\] -.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0,x0\] -.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3,x0\] -.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp,x0\] -.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0,x4\] -.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0,xzr\] -.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0,xzr\] -.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0,xzr\] -.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0,z31\.d\] +.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\] +.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\] +.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\] +.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\] +.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\] +.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\] +.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\] +.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\] +.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\] +.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\] +.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\] +.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\] +.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\] +.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\] +.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\] +.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\] +.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\] +.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\] +.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\] +.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\] +.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\] +.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\] +.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\] +.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\] +.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\] +.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\] +.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\] +.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\] +.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\] +.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\] +.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\] +.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\] +.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\] +.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\] +.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\] +.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\] +.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\] +.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\] +.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\] +.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\] +.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\] +.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\] +.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\] +.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\] +.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\] +.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\] .*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\] @@ -16798,14 +16798,14 @@ Disassembly of section .*: .*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\] -.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#31\] -.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s,#31\] +.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #31\] +.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #31\] .*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\] .*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\] .*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\] @@ -16830,188 +16830,188 @@ Disassembly of section .*: .*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\] .*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\] .*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\] -.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0,xzr,lsl #3\] -.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0,xzr,lsl #3\] -.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\] -.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\] -.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\] -.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\] -.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\] -.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\] -.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\] -.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\] -.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\] -.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\] -.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\] -.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\] -.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\] -.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\] -.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\] -.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\] -.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\] -.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\] -.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\] -.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\] -.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\] -.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\] -.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\] -.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\] -.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\] -.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\] -.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\] -.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\] -.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\] -.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\] -.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\] -.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\] -.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\] +.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\] +.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\] +.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\] +.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\] +.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\] +.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\] +.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\] +.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\] +.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\] +.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\] +.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\] +.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\] +.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\] +.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\] +.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\] +.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\] +.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\] +.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\] +.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\] +.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\] +.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\] +.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\] +.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\] +.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\] +.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\] +.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\] +.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\] +.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\] +.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\] +.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\] +.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\] +.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\] +.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\] +.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\] +.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\] .*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\] .*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\] .*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\] @@ -17036,332 +17036,332 @@ Disassembly of section .*: .*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\] .*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\] .*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\] -.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#120\] -.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#120\] -.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#128\] -.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#128\] -.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#136\] -.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#136\] -.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#248\] -.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d,#248\] -.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0,xzr,lsl #1\] -.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0,xzr,lsl #1\] -.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\] -.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\] -.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\] -.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\] -.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] -.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] +.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #120\] +.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #120\] +.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #128\] +.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #128\] +.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #136\] +.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #136\] +.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #248\] +.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #248\] +.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\] +.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\] +.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\] +.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\] +.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\] +.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\] +.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] +.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] .*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\] @@ -17386,14 +17386,14 @@ Disassembly of section .*: .*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\] -.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#62\] -.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s,#62\] +.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #62\] +.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #62\] .*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\] @@ -17418,254 +17418,254 @@ Disassembly of section .*: .*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\] -.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0,x0\] -.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0,x0\] -.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0,x0\] -.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0,x0\] -.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0,x0\] -.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3,x0\] -.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp,x0\] -.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0,x4\] -.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\] -.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\] -.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\] -.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0,x0\] -.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0,x0\] -.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0,x0\] -.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0,x0\] -.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0,x0\] -.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3,x0\] -.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp,x0\] -.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0,x4\] -.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\] -.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0,x0\] -.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0,x0\] -.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0,x0\] -.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0,x0\] -.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0,x0\] -.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3,x0\] -.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp,x0\] -.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0,x4\] -.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\] -.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\] -.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\] -.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\] +.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\] +.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\] +.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\] +.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\] +.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\] +.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\] +.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\] +.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\] +.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\] +.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\] +.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\] +.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\] +.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\] +.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\] +.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\] +.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\] +.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\] +.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\] +.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\] +.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\] +.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\] +.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\] +.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\] +.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\] +.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\] +.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\] +.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\] +.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\] +.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\] +.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\] +.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\] +.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\] .*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\] .*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\] @@ -17690,14 +17690,14 @@ Disassembly of section .*: .*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\] .*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\] -.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#15\] -.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#16\] -.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#17\] -.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#31\] -.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#31\] +.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\] +.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\] +.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\] +.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\] +.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\] .*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\] .*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\] .*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\] @@ -17722,311 +17722,311 @@ Disassembly of section .*: .*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\] .*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\] .*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\] -.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#15\] -.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#16\] -.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#17\] -.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#31\] -.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\] -.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\] -.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\] -.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\] -.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\] -.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\] -.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\] -.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\] -.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\] -.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\] -.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\] -.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\] -.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\] -.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\] -.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\] -.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\] -.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\] -.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\] -.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\] -.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\] -.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\] -.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\] -.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\] -.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\] -.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\] -.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\] -.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\] -.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\] -.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\] -.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\] -.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\] -.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\] -.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\] -.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\] -.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\] -.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\] -.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\] -.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\] -.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\] -.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\] -.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\] -.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\] -.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\] -.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\] -.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\] -.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] -.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\] +.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\] +.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\] +.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\] +.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\] +.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\] +.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\] +.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\] +.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\] +.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\] +.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\] +.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\] +.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\] +.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\] +.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\] +.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\] +.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\] +.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\] +.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\] +.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\] +.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\] +.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\] +.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\] +.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\] +.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\] +.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\] +.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\] +.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\] +.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\] +.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\] +.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\] +.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\] +.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\] +.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\] +.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\] +.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\] +.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\] +.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\] +.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\] +.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\] +.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\] +.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\] +.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\] +.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\] +.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\] +.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\] +.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\] +.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\] +.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\] +.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\] +.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] +.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\] .*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\] .*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\] @@ -18051,14 +18051,14 @@ Disassembly of section .*: .*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\] .*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\] -.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#30\] -.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#32\] -.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#34\] -.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#62\] -.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#62\] +.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\] +.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\] +.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\] +.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\] +.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\] .*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\] .*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\] @@ -18083,188 +18083,188 @@ Disassembly of section .*: .*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\] .*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\] -.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#30\] -.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#32\] -.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#34\] -.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#62\] -.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\] -.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\] -.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] -.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] +.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\] +.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\] +.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\] +.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\] +.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\] +.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\] +.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] +.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] .*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\] .*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\] .*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\] @@ -18289,311 +18289,311 @@ Disassembly of section .*: .*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\] .*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\] .*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\] -.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\] -.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\] -.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\] -.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\] -.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\] -.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\] -.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\] -.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\] -.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\] -.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\] -.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\] -.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\] -.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\] -.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\] -.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\] -.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\] -.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\] -.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\] -.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\] -.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\] -.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\] -.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\] -.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\] -.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\] -.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\] -.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\] -.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\] -.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\] -.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\] -.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\] -.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\] -.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\] -.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\] -.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\] -.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\] -.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\] -.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\] -.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\] -.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\] -.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\] -.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0,xzr,lsl #2\] -.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0,xzr,lsl #2\] -.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0,x0,lsl #2\] -.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0,x0,lsl #2\] -.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0,x0,lsl #2\] -.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3,x0,lsl #2\] -.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp,x0,lsl #2\] -.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0,x4,lsl #2\] -.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\] -.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\] -.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\] -.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\] -.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\] -.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\] -.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\] -.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\] -.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\] -.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\] -.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\] -.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\] -.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\] -.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\] -.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\] -.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\] -.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\] -.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\] -.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\] -.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\] -.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\] -.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\] -.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\] -.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\] -.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\] -.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\] -.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\] -.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\] -.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\] -.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\] -.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d\] -.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d\] -.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d\] -.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d\] -.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d\] -.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d\] -.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d\] -.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\] -.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\] -.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\] -.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\] -.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\] -.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\] -.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] -.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\] +.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\] +.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\] +.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\] +.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\] +.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\] +.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\] +.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\] +.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\] +.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\] +.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\] +.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\] +.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\] +.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\] +.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\] +.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\] +.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\] +.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\] +.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\] +.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\] +.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\] +.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\] +.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\] +.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\] +.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\] +.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\] +.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\] +.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\] +.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\] +.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\] +.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\] +.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\] +.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\] +.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\] +.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\] +.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\] +.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\] +.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\] +.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\] +.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\] +.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\] +.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\] +.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\] +.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\] +.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\] +.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\] +.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\] +.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\] +.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\] +.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\] +.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\] +.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\] +.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\] +.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\] +.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\] +.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\] +.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\] +.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\] +.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\] +.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\] +.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\] +.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\] +.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\] +.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\] +.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\] +.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\] +.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\] +.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\] +.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\] +.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\] +.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\] +.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\] +.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\] +.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\] +.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\] +.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\] +.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\] +.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\] +.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\] +.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\] +.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\] +.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\] +.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\] +.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\] +.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\] +.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\] +.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\] +.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\] +.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\] +.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\] +.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\] +.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\] +.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] +.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\] .*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\] .*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\] .*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\] @@ -18618,14 +18618,14 @@ Disassembly of section .*: .*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\] .*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\] .*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\] -.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#60\] -.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#60\] -.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#64\] -.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#64\] -.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#68\] -.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#68\] -.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#124\] -.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s,#124\] +.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #60\] +.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #60\] +.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #64\] +.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #64\] +.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #68\] +.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #68\] +.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #124\] +.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #124\] .*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\] .*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\] .*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\] @@ -18650,14 +18650,14 @@ Disassembly of section .*: .*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\] .*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\] .*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\] -.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#60\] -.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#64\] -.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#68\] -.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#124\] -.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d,#124\] +.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #60\] +.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #64\] +.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #68\] +.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #124\] +.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #124\] .*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\] .*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\] .*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\] @@ -18689,14 +18689,14 @@ Disassembly of section .*: .*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\] .*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\] .*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\] -.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] -.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] +.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] +.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] .*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\] .*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\] .*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\] @@ -18728,14 +18728,14 @@ Disassembly of section .*: .*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\] .*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\] .*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\] -.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\] .*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\] .*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\] @@ -18767,14 +18767,14 @@ Disassembly of section .*: .*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\] .*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\] .*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\] -.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\] .*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\] .*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\] @@ -18806,14 +18806,14 @@ Disassembly of section .*: .*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\] .*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\] .*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\] -.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\] .*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\] .*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\] @@ -18845,14 +18845,14 @@ Disassembly of section .*: .*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\] .*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\] .*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\] -.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\] .*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\] .*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\] @@ -18884,14 +18884,14 @@ Disassembly of section .*: .*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\] .*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\] .*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\] -.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\] .*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\] .*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\] @@ -18923,14 +18923,14 @@ Disassembly of section .*: .*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\] .*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\] .*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\] -.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\] .*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\] .*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\] @@ -18962,14 +18962,14 @@ Disassembly of section .*: .*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\] .*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\] .*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\] -.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\] .*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\] .*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\] @@ -19001,14 +19001,14 @@ Disassembly of section .*: .*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\] .*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\] .*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\] -.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\] .*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\] .*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\] @@ -19040,14 +19040,14 @@ Disassembly of section .*: .*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\] .*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\] .*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\] -.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\] .*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\] .*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\] @@ -19079,14 +19079,14 @@ Disassembly of section .*: .*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\] .*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\] .*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\] -.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] +.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] .*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\] .*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\] .*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\] @@ -19118,14 +19118,14 @@ Disassembly of section .*: .*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\] .*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\] .*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\] -.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\] .*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\] .*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\] @@ -19157,14 +19157,14 @@ Disassembly of section .*: .*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\] .*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\] .*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\] -.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\] .*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\] .*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\] @@ -19196,14 +19196,14 @@ Disassembly of section .*: .*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\] .*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\] .*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\] -.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] +.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] .*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\] .*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\] .*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\] @@ -19235,14 +19235,14 @@ Disassembly of section .*: .*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\] .*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\] .*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\] -.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\] .*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\] .*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\] @@ -19274,44 +19274,44 @@ Disassembly of section .*: .*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\] .*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\] .*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\] -.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x0\] -.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0,x0\] -.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0,x0\] -.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0,x0\] -.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0,x0\] -.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3,x0\] -.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp,x0\] -.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0,x4\] -.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0,x30\] -.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0,x30\] -.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0,x30\] +.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\] +.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\] +.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\] +.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\] +.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\] +.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\] +.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\] +.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\] +.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\] +.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\] +.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\] .*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\] .*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\] .*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\] @@ -19343,35 +19343,35 @@ Disassembly of section .*: .*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\] .*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\] .*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\] -.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#7,mul vl\] -.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-8,mul vl\] -.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-7,mul vl\] -.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] -.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0,#-1,mul vl\] -.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0,x0,lsl #3\] -.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0,x0,lsl #3\] -.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0,x0,lsl #3\] -.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3,x0,lsl #3\] -.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp,x0,lsl #3\] -.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0,x4,lsl #3\] -.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0,x30,lsl #3\] -.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0,x30,lsl #3\] +.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\] +.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\] +.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\] +.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] +.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\] +.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\] +.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\] +.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\] +.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\] +.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\] +.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\] +.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\] +.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\] .*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\] .*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\] .*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\] @@ -19403,35 +19403,35 @@ Disassembly of section .*: .*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\] .*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\] .*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\] -.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#7,mul vl\] -.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-8,mul vl\] -.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-7,mul vl\] -.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0,#-1,mul vl\] -.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0,x0,lsl #1\] -.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0,x0,lsl #1\] -.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0,x0,lsl #1\] -.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3,x0,lsl #1\] -.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp,x0,lsl #1\] -.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0,x4,lsl #1\] -.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0,x30,lsl #1\] -.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0,x30,lsl #1\] +.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\] +.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\] +.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\] +.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\] +.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\] +.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\] +.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\] +.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\] +.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\] +.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\] +.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\] +.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\] .*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\] .*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\] .*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\] @@ -19463,35 +19463,35 @@ Disassembly of section .*: .*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\] .*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\] .*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\] -.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#7,mul vl\] -.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-8,mul vl\] -.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-7,mul vl\] -.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0,#-1,mul vl\] -.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0,x0,lsl #2\] -.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0,x0,lsl #2\] -.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0,x0,lsl #2\] -.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3,x0,lsl #2\] -.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp,x0,lsl #2\] -.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0,x4,lsl #2\] -.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0,x30,lsl #2\] -.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0,x30,lsl #2\] +.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\] +.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\] +.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\] +.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\] +.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\] +.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\] +.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\] +.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\] +.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\] +.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\] +.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\] +.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\] .*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\] .*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\] .*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\] @@ -19523,14 +19523,14 @@ Disassembly of section .*: .*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\] .*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\] .*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\] -.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#7,mul vl\] -.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-8,mul vl\] -.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-7,mul vl\] -.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] -.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0,#-1,mul vl\] +.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\] +.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\] +.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\] +.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] +.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\] .*: 85800000 ldr p0, \[x0\] .*: 85800000 ldr p0, \[x0\] .*: 85800000 ldr p0, \[x0\] @@ -19551,14 +19551,14 @@ Disassembly of section .*: .*: 858003e0 ldr p0, \[sp\] .*: 858003e0 ldr p0, \[sp\] .*: 858003e0 ldr p0, \[sp\] -.*: 859f1c00 ldr p0, \[x0,#255,mul vl\] -.*: 859f1c00 ldr p0, \[x0,#255,mul vl\] -.*: 85a00000 ldr p0, \[x0,#-256,mul vl\] -.*: 85a00000 ldr p0, \[x0,#-256,mul vl\] -.*: 85a00400 ldr p0, \[x0,#-255,mul vl\] -.*: 85a00400 ldr p0, \[x0,#-255,mul vl\] -.*: 85bf1c00 ldr p0, \[x0,#-1,mul vl\] -.*: 85bf1c00 ldr p0, \[x0,#-1,mul vl\] +.*: 859f1c00 ldr p0, \[x0, #255, mul vl\] +.*: 859f1c00 ldr p0, \[x0, #255, mul vl\] +.*: 85a00000 ldr p0, \[x0, #-256, mul vl\] +.*: 85a00000 ldr p0, \[x0, #-256, mul vl\] +.*: 85a00400 ldr p0, \[x0, #-255, mul vl\] +.*: 85a00400 ldr p0, \[x0, #-255, mul vl\] +.*: 85bf1c00 ldr p0, \[x0, #-1, mul vl\] +.*: 85bf1c00 ldr p0, \[x0, #-1, mul vl\] .*: 85804000 ldr z0, \[x0\] .*: 85804000 ldr z0, \[x0\] .*: 85804000 ldr z0, \[x0\] @@ -19579,14 +19579,14 @@ Disassembly of section .*: .*: 858043e0 ldr z0, \[sp\] .*: 858043e0 ldr z0, \[sp\] .*: 858043e0 ldr z0, \[sp\] -.*: 859f5c00 ldr z0, \[x0,#255,mul vl\] -.*: 859f5c00 ldr z0, \[x0,#255,mul vl\] -.*: 85a04000 ldr z0, \[x0,#-256,mul vl\] -.*: 85a04000 ldr z0, \[x0,#-256,mul vl\] -.*: 85a04400 ldr z0, \[x0,#-255,mul vl\] -.*: 85a04400 ldr z0, \[x0,#-255,mul vl\] -.*: 85bf5c00 ldr z0, \[x0,#-1,mul vl\] -.*: 85bf5c00 ldr z0, \[x0,#-1,mul vl\] +.*: 859f5c00 ldr z0, \[x0, #255, mul vl\] +.*: 859f5c00 ldr z0, \[x0, #255, mul vl\] +.*: 85a04000 ldr z0, \[x0, #-256, mul vl\] +.*: 85a04000 ldr z0, \[x0, #-256, mul vl\] +.*: 85a04400 ldr z0, \[x0, #-255, mul vl\] +.*: 85a04400 ldr z0, \[x0, #-255, mul vl\] +.*: 85bf5c00 ldr z0, \[x0, #-1, mul vl\] +.*: 85bf5c00 ldr z0, \[x0, #-1, mul vl\] .*: 04208c00 lsl z0\.b, z0\.b, z0\.d .*: 04208c00 lsl z0\.b, z0\.b, z0\.d .*: 04208c01 lsl z1\.b, z0\.b, z0\.d @@ -21986,402 +21986,402 @@ Disassembly of section .*: .*: 25d9c5e0 pnext p0\.d, p15, p0\.d .*: 25d9c403 pnext p3\.d, p0, p3\.d .*: 25d9c403 pnext p3\.d, p0, p3\.d -.*: 8400c000 prfb pldl1keep, p0, \[x0,x0\] -.*: 8400c000 prfb pldl1keep, p0, \[x0,x0\] -.*: 8400c000 prfb pldl1keep, p0, \[x0,x0\] -.*: 8400c001 prfb pldl1strm, p0, \[x0,x0\] -.*: 8400c001 prfb pldl1strm, p0, \[x0,x0\] -.*: 8400c001 prfb pldl1strm, p0, \[x0,x0\] -.*: 8400c002 prfb pldl2keep, p0, \[x0,x0\] -.*: 8400c002 prfb pldl2keep, p0, \[x0,x0\] -.*: 8400c002 prfb pldl2keep, p0, \[x0,x0\] -.*: 8400c003 prfb pldl2strm, p0, \[x0,x0\] -.*: 8400c003 prfb pldl2strm, p0, \[x0,x0\] -.*: 8400c003 prfb pldl2strm, p0, \[x0,x0\] -.*: 8400c004 prfb pldl3keep, p0, \[x0,x0\] -.*: 8400c004 prfb pldl3keep, p0, \[x0,x0\] -.*: 8400c004 prfb pldl3keep, p0, \[x0,x0\] -.*: 8400c005 prfb pldl3strm, p0, \[x0,x0\] -.*: 8400c005 prfb pldl3strm, p0, \[x0,x0\] -.*: 8400c005 prfb pldl3strm, p0, \[x0,x0\] -.*: 8400c006 prfb #6, p0, \[x0,x0\] -.*: 8400c006 prfb #6, p0, \[x0,x0\] -.*: 8400c006 prfb #6, p0, \[x0,x0\] -.*: 8400c007 prfb #7, p0, \[x0,x0\] -.*: 8400c007 prfb #7, p0, \[x0,x0\] -.*: 8400c007 prfb #7, p0, \[x0,x0\] -.*: 8400c008 prfb pstl1keep, p0, \[x0,x0\] -.*: 8400c008 prfb pstl1keep, p0, \[x0,x0\] -.*: 8400c008 prfb pstl1keep, p0, \[x0,x0\] -.*: 8400c009 prfb pstl1strm, p0, \[x0,x0\] -.*: 8400c009 prfb pstl1strm, p0, \[x0,x0\] -.*: 8400c009 prfb pstl1strm, p0, \[x0,x0\] -.*: 8400c00a prfb pstl2keep, p0, \[x0,x0\] -.*: 8400c00a prfb pstl2keep, p0, \[x0,x0\] -.*: 8400c00a prfb pstl2keep, p0, \[x0,x0\] -.*: 8400c00b prfb pstl2strm, p0, \[x0,x0\] -.*: 8400c00b prfb pstl2strm, p0, \[x0,x0\] -.*: 8400c00b prfb pstl2strm, p0, \[x0,x0\] -.*: 8400c00c prfb pstl3keep, p0, \[x0,x0\] -.*: 8400c00c prfb pstl3keep, p0, \[x0,x0\] -.*: 8400c00c prfb pstl3keep, p0, \[x0,x0\] -.*: 8400c00d prfb pstl3strm, p0, \[x0,x0\] -.*: 8400c00d prfb pstl3strm, p0, \[x0,x0\] -.*: 8400c00d prfb pstl3strm, p0, \[x0,x0\] -.*: 8400c00e prfb #14, p0, \[x0,x0\] -.*: 8400c00e prfb #14, p0, \[x0,x0\] -.*: 8400c00e prfb #14, p0, \[x0,x0\] -.*: 8400c00f prfb #15, p0, \[x0,x0\] -.*: 8400c00f prfb #15, p0, \[x0,x0\] -.*: 8400c00f prfb #15, p0, \[x0,x0\] -.*: 8400c800 prfb pldl1keep, p2, \[x0,x0\] -.*: 8400c800 prfb pldl1keep, p2, \[x0,x0\] -.*: 8400c800 prfb pldl1keep, p2, \[x0,x0\] -.*: 8400dc00 prfb pldl1keep, p7, \[x0,x0\] -.*: 8400dc00 prfb pldl1keep, p7, \[x0,x0\] -.*: 8400dc00 prfb pldl1keep, p7, \[x0,x0\] -.*: 8400c060 prfb pldl1keep, p0, \[x3,x0\] -.*: 8400c060 prfb pldl1keep, p0, \[x3,x0\] -.*: 8400c060 prfb pldl1keep, p0, \[x3,x0\] -.*: 8400c3e0 prfb pldl1keep, p0, \[sp,x0\] -.*: 8400c3e0 prfb pldl1keep, p0, \[sp,x0\] -.*: 8400c3e0 prfb pldl1keep, p0, \[sp,x0\] -.*: 8404c000 prfb pldl1keep, p0, \[x0,x4\] -.*: 8404c000 prfb pldl1keep, p0, \[x0,x4\] -.*: 8404c000 prfb pldl1keep, p0, \[x0,x4\] -.*: 841ec000 prfb pldl1keep, p0, \[x0,x30\] -.*: 841ec000 prfb pldl1keep, p0, \[x0,x30\] -.*: 841ec000 prfb pldl1keep, p0, \[x0,x30\] -.*: 84200000 prfb pldl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200000 prfb pldl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200000 prfb pldl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200001 prfb pldl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200001 prfb pldl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200001 prfb pldl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200002 prfb pldl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200002 prfb pldl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200002 prfb pldl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200003 prfb pldl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200003 prfb pldl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200003 prfb pldl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200004 prfb pldl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200004 prfb pldl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200004 prfb pldl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200005 prfb pldl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200005 prfb pldl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200005 prfb pldl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200006 prfb #6, p0, \[x0,z0\.s,uxtw\] -.*: 84200006 prfb #6, p0, \[x0,z0\.s,uxtw\] -.*: 84200006 prfb #6, p0, \[x0,z0\.s,uxtw\] -.*: 84200007 prfb #7, p0, \[x0,z0\.s,uxtw\] -.*: 84200007 prfb #7, p0, \[x0,z0\.s,uxtw\] -.*: 84200007 prfb #7, p0, \[x0,z0\.s,uxtw\] -.*: 84200008 prfb pstl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200008 prfb pstl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200008 prfb pstl1keep, p0, \[x0,z0\.s,uxtw\] -.*: 84200009 prfb pstl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200009 prfb pstl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 84200009 prfb pstl1strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000a prfb pstl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000a prfb pstl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000a prfb pstl2keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000b prfb pstl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000b prfb pstl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000b prfb pstl2strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000c prfb pstl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000c prfb pstl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000c prfb pstl3keep, p0, \[x0,z0\.s,uxtw\] -.*: 8420000d prfb pstl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000d prfb pstl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000d prfb pstl3strm, p0, \[x0,z0\.s,uxtw\] -.*: 8420000e prfb #14, p0, \[x0,z0\.s,uxtw\] -.*: 8420000e prfb #14, p0, \[x0,z0\.s,uxtw\] -.*: 8420000e prfb #14, p0, \[x0,z0\.s,uxtw\] -.*: 8420000f prfb #15, p0, \[x0,z0\.s,uxtw\] -.*: 8420000f prfb #15, p0, \[x0,z0\.s,uxtw\] -.*: 8420000f prfb #15, p0, \[x0,z0\.s,uxtw\] -.*: 84200800 prfb pldl1keep, p2, \[x0,z0\.s,uxtw\] -.*: 84200800 prfb pldl1keep, p2, \[x0,z0\.s,uxtw\] -.*: 84200800 prfb pldl1keep, p2, \[x0,z0\.s,uxtw\] -.*: 84201c00 prfb pldl1keep, p7, \[x0,z0\.s,uxtw\] -.*: 84201c00 prfb pldl1keep, p7, \[x0,z0\.s,uxtw\] -.*: 84201c00 prfb pldl1keep, p7, \[x0,z0\.s,uxtw\] -.*: 84200060 prfb pldl1keep, p0, \[x3,z0\.s,uxtw\] -.*: 84200060 prfb pldl1keep, p0, \[x3,z0\.s,uxtw\] -.*: 84200060 prfb pldl1keep, p0, \[x3,z0\.s,uxtw\] -.*: 842003e0 prfb pldl1keep, p0, \[sp,z0\.s,uxtw\] -.*: 842003e0 prfb pldl1keep, p0, \[sp,z0\.s,uxtw\] -.*: 842003e0 prfb pldl1keep, p0, \[sp,z0\.s,uxtw\] -.*: 84240000 prfb pldl1keep, p0, \[x0,z4\.s,uxtw\] -.*: 84240000 prfb pldl1keep, p0, \[x0,z4\.s,uxtw\] -.*: 84240000 prfb pldl1keep, p0, \[x0,z4\.s,uxtw\] -.*: 843f0000 prfb pldl1keep, p0, \[x0,z31\.s,uxtw\] -.*: 843f0000 prfb pldl1keep, p0, \[x0,z31\.s,uxtw\] -.*: 843f0000 prfb pldl1keep, p0, \[x0,z31\.s,uxtw\] -.*: 84600000 prfb pldl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600000 prfb pldl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600000 prfb pldl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600001 prfb pldl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600001 prfb pldl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600001 prfb pldl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600002 prfb pldl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600002 prfb pldl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600002 prfb pldl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600003 prfb pldl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600003 prfb pldl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600003 prfb pldl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600004 prfb pldl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600004 prfb pldl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600004 prfb pldl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600005 prfb pldl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600005 prfb pldl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600005 prfb pldl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600006 prfb #6, p0, \[x0,z0\.s,sxtw\] -.*: 84600006 prfb #6, p0, \[x0,z0\.s,sxtw\] -.*: 84600006 prfb #6, p0, \[x0,z0\.s,sxtw\] -.*: 84600007 prfb #7, p0, \[x0,z0\.s,sxtw\] -.*: 84600007 prfb #7, p0, \[x0,z0\.s,sxtw\] -.*: 84600007 prfb #7, p0, \[x0,z0\.s,sxtw\] -.*: 84600008 prfb pstl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600008 prfb pstl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600008 prfb pstl1keep, p0, \[x0,z0\.s,sxtw\] -.*: 84600009 prfb pstl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600009 prfb pstl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 84600009 prfb pstl1strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000a prfb pstl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000a prfb pstl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000a prfb pstl2keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000b prfb pstl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000b prfb pstl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000b prfb pstl2strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000c prfb pstl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000c prfb pstl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000c prfb pstl3keep, p0, \[x0,z0\.s,sxtw\] -.*: 8460000d prfb pstl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000d prfb pstl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000d prfb pstl3strm, p0, \[x0,z0\.s,sxtw\] -.*: 8460000e prfb #14, p0, \[x0,z0\.s,sxtw\] -.*: 8460000e prfb #14, p0, \[x0,z0\.s,sxtw\] -.*: 8460000e prfb #14, p0, \[x0,z0\.s,sxtw\] -.*: 8460000f prfb #15, p0, \[x0,z0\.s,sxtw\] -.*: 8460000f prfb #15, p0, \[x0,z0\.s,sxtw\] -.*: 8460000f prfb #15, p0, \[x0,z0\.s,sxtw\] -.*: 84600800 prfb pldl1keep, p2, \[x0,z0\.s,sxtw\] -.*: 84600800 prfb pldl1keep, p2, \[x0,z0\.s,sxtw\] -.*: 84600800 prfb pldl1keep, p2, \[x0,z0\.s,sxtw\] -.*: 84601c00 prfb pldl1keep, p7, \[x0,z0\.s,sxtw\] -.*: 84601c00 prfb pldl1keep, p7, \[x0,z0\.s,sxtw\] -.*: 84601c00 prfb pldl1keep, p7, \[x0,z0\.s,sxtw\] -.*: 84600060 prfb pldl1keep, p0, \[x3,z0\.s,sxtw\] -.*: 84600060 prfb pldl1keep, p0, \[x3,z0\.s,sxtw\] -.*: 84600060 prfb pldl1keep, p0, \[x3,z0\.s,sxtw\] -.*: 846003e0 prfb pldl1keep, p0, \[sp,z0\.s,sxtw\] -.*: 846003e0 prfb pldl1keep, p0, \[sp,z0\.s,sxtw\] -.*: 846003e0 prfb pldl1keep, p0, \[sp,z0\.s,sxtw\] -.*: 84640000 prfb pldl1keep, p0, \[x0,z4\.s,sxtw\] -.*: 84640000 prfb pldl1keep, p0, \[x0,z4\.s,sxtw\] -.*: 84640000 prfb pldl1keep, p0, \[x0,z4\.s,sxtw\] -.*: 847f0000 prfb pldl1keep, p0, \[x0,z31\.s,sxtw\] -.*: 847f0000 prfb pldl1keep, p0, \[x0,z31\.s,sxtw\] -.*: 847f0000 prfb pldl1keep, p0, \[x0,z31\.s,sxtw\] -.*: c4200000 prfb pldl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200000 prfb pldl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200000 prfb pldl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200001 prfb pldl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200001 prfb pldl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200001 prfb pldl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200002 prfb pldl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200002 prfb pldl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200002 prfb pldl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200003 prfb pldl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200003 prfb pldl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200003 prfb pldl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200004 prfb pldl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200004 prfb pldl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200004 prfb pldl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200005 prfb pldl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200005 prfb pldl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200005 prfb pldl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200006 prfb #6, p0, \[x0,z0\.d,uxtw\] -.*: c4200006 prfb #6, p0, \[x0,z0\.d,uxtw\] -.*: c4200006 prfb #6, p0, \[x0,z0\.d,uxtw\] -.*: c4200007 prfb #7, p0, \[x0,z0\.d,uxtw\] -.*: c4200007 prfb #7, p0, \[x0,z0\.d,uxtw\] -.*: c4200007 prfb #7, p0, \[x0,z0\.d,uxtw\] -.*: c4200008 prfb pstl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200008 prfb pstl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200008 prfb pstl1keep, p0, \[x0,z0\.d,uxtw\] -.*: c4200009 prfb pstl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200009 prfb pstl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c4200009 prfb pstl1strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000a prfb pstl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000a prfb pstl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000a prfb pstl2keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000b prfb pstl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000b prfb pstl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000b prfb pstl2strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000c prfb pstl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000c prfb pstl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000c prfb pstl3keep, p0, \[x0,z0\.d,uxtw\] -.*: c420000d prfb pstl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000d prfb pstl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000d prfb pstl3strm, p0, \[x0,z0\.d,uxtw\] -.*: c420000e prfb #14, p0, \[x0,z0\.d,uxtw\] -.*: c420000e prfb #14, p0, \[x0,z0\.d,uxtw\] -.*: c420000e prfb #14, p0, \[x0,z0\.d,uxtw\] -.*: c420000f prfb #15, p0, \[x0,z0\.d,uxtw\] -.*: c420000f prfb #15, p0, \[x0,z0\.d,uxtw\] -.*: c420000f prfb #15, p0, \[x0,z0\.d,uxtw\] -.*: c4200800 prfb pldl1keep, p2, \[x0,z0\.d,uxtw\] -.*: c4200800 prfb pldl1keep, p2, \[x0,z0\.d,uxtw\] -.*: c4200800 prfb pldl1keep, p2, \[x0,z0\.d,uxtw\] -.*: c4201c00 prfb pldl1keep, p7, \[x0,z0\.d,uxtw\] -.*: c4201c00 prfb pldl1keep, p7, \[x0,z0\.d,uxtw\] -.*: c4201c00 prfb pldl1keep, p7, \[x0,z0\.d,uxtw\] -.*: c4200060 prfb pldl1keep, p0, \[x3,z0\.d,uxtw\] -.*: c4200060 prfb pldl1keep, p0, \[x3,z0\.d,uxtw\] -.*: c4200060 prfb pldl1keep, p0, \[x3,z0\.d,uxtw\] -.*: c42003e0 prfb pldl1keep, p0, \[sp,z0\.d,uxtw\] -.*: c42003e0 prfb pldl1keep, p0, \[sp,z0\.d,uxtw\] -.*: c42003e0 prfb pldl1keep, p0, \[sp,z0\.d,uxtw\] -.*: c4240000 prfb pldl1keep, p0, \[x0,z4\.d,uxtw\] -.*: c4240000 prfb pldl1keep, p0, \[x0,z4\.d,uxtw\] -.*: c4240000 prfb pldl1keep, p0, \[x0,z4\.d,uxtw\] -.*: c43f0000 prfb pldl1keep, p0, \[x0,z31\.d,uxtw\] -.*: c43f0000 prfb pldl1keep, p0, \[x0,z31\.d,uxtw\] -.*: c43f0000 prfb pldl1keep, p0, \[x0,z31\.d,uxtw\] -.*: c4600000 prfb pldl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600000 prfb pldl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600000 prfb pldl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600001 prfb pldl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600001 prfb pldl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600001 prfb pldl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600002 prfb pldl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600002 prfb pldl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600002 prfb pldl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600003 prfb pldl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600003 prfb pldl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600003 prfb pldl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600004 prfb pldl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600004 prfb pldl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600004 prfb pldl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600005 prfb pldl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600005 prfb pldl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600005 prfb pldl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600006 prfb #6, p0, \[x0,z0\.d,sxtw\] -.*: c4600006 prfb #6, p0, \[x0,z0\.d,sxtw\] -.*: c4600006 prfb #6, p0, \[x0,z0\.d,sxtw\] -.*: c4600007 prfb #7, p0, \[x0,z0\.d,sxtw\] -.*: c4600007 prfb #7, p0, \[x0,z0\.d,sxtw\] -.*: c4600007 prfb #7, p0, \[x0,z0\.d,sxtw\] -.*: c4600008 prfb pstl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600008 prfb pstl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600008 prfb pstl1keep, p0, \[x0,z0\.d,sxtw\] -.*: c4600009 prfb pstl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600009 prfb pstl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c4600009 prfb pstl1strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000a prfb pstl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000a prfb pstl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000a prfb pstl2keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000b prfb pstl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000b prfb pstl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000b prfb pstl2strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000c prfb pstl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000c prfb pstl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000c prfb pstl3keep, p0, \[x0,z0\.d,sxtw\] -.*: c460000d prfb pstl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000d prfb pstl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000d prfb pstl3strm, p0, \[x0,z0\.d,sxtw\] -.*: c460000e prfb #14, p0, \[x0,z0\.d,sxtw\] -.*: c460000e prfb #14, p0, \[x0,z0\.d,sxtw\] -.*: c460000e prfb #14, p0, \[x0,z0\.d,sxtw\] -.*: c460000f prfb #15, p0, \[x0,z0\.d,sxtw\] -.*: c460000f prfb #15, p0, \[x0,z0\.d,sxtw\] -.*: c460000f prfb #15, p0, \[x0,z0\.d,sxtw\] -.*: c4600800 prfb pldl1keep, p2, \[x0,z0\.d,sxtw\] -.*: c4600800 prfb pldl1keep, p2, \[x0,z0\.d,sxtw\] -.*: c4600800 prfb pldl1keep, p2, \[x0,z0\.d,sxtw\] -.*: c4601c00 prfb pldl1keep, p7, \[x0,z0\.d,sxtw\] -.*: c4601c00 prfb pldl1keep, p7, \[x0,z0\.d,sxtw\] -.*: c4601c00 prfb pldl1keep, p7, \[x0,z0\.d,sxtw\] -.*: c4600060 prfb pldl1keep, p0, \[x3,z0\.d,sxtw\] -.*: c4600060 prfb pldl1keep, p0, \[x3,z0\.d,sxtw\] -.*: c4600060 prfb pldl1keep, p0, \[x3,z0\.d,sxtw\] -.*: c46003e0 prfb pldl1keep, p0, \[sp,z0\.d,sxtw\] -.*: c46003e0 prfb pldl1keep, p0, \[sp,z0\.d,sxtw\] -.*: c46003e0 prfb pldl1keep, p0, \[sp,z0\.d,sxtw\] -.*: c4640000 prfb pldl1keep, p0, \[x0,z4\.d,sxtw\] -.*: c4640000 prfb pldl1keep, p0, \[x0,z4\.d,sxtw\] -.*: c4640000 prfb pldl1keep, p0, \[x0,z4\.d,sxtw\] -.*: c47f0000 prfb pldl1keep, p0, \[x0,z31\.d,sxtw\] -.*: c47f0000 prfb pldl1keep, p0, \[x0,z31\.d,sxtw\] -.*: c47f0000 prfb pldl1keep, p0, \[x0,z31\.d,sxtw\] -.*: c4608000 prfb pldl1keep, p0, \[x0,z0\.d\] -.*: c4608000 prfb pldl1keep, p0, \[x0,z0\.d\] -.*: c4608000 prfb pldl1keep, p0, \[x0,z0\.d\] -.*: c4608001 prfb pldl1strm, p0, \[x0,z0\.d\] -.*: c4608001 prfb pldl1strm, p0, \[x0,z0\.d\] -.*: c4608001 prfb pldl1strm, p0, \[x0,z0\.d\] -.*: c4608002 prfb pldl2keep, p0, \[x0,z0\.d\] -.*: c4608002 prfb pldl2keep, p0, \[x0,z0\.d\] -.*: c4608002 prfb pldl2keep, p0, \[x0,z0\.d\] -.*: c4608003 prfb pldl2strm, p0, \[x0,z0\.d\] -.*: c4608003 prfb pldl2strm, p0, \[x0,z0\.d\] -.*: c4608003 prfb pldl2strm, p0, \[x0,z0\.d\] -.*: c4608004 prfb pldl3keep, p0, \[x0,z0\.d\] -.*: c4608004 prfb pldl3keep, p0, \[x0,z0\.d\] -.*: c4608004 prfb pldl3keep, p0, \[x0,z0\.d\] -.*: c4608005 prfb pldl3strm, p0, \[x0,z0\.d\] -.*: c4608005 prfb pldl3strm, p0, \[x0,z0\.d\] -.*: c4608005 prfb pldl3strm, p0, \[x0,z0\.d\] -.*: c4608006 prfb #6, p0, \[x0,z0\.d\] -.*: c4608006 prfb #6, p0, \[x0,z0\.d\] -.*: c4608006 prfb #6, p0, \[x0,z0\.d\] -.*: c4608007 prfb #7, p0, \[x0,z0\.d\] -.*: c4608007 prfb #7, p0, \[x0,z0\.d\] -.*: c4608007 prfb #7, p0, \[x0,z0\.d\] -.*: c4608008 prfb pstl1keep, p0, \[x0,z0\.d\] -.*: c4608008 prfb pstl1keep, p0, \[x0,z0\.d\] -.*: c4608008 prfb pstl1keep, p0, \[x0,z0\.d\] -.*: c4608009 prfb pstl1strm, p0, \[x0,z0\.d\] -.*: c4608009 prfb pstl1strm, p0, \[x0,z0\.d\] -.*: c4608009 prfb pstl1strm, p0, \[x0,z0\.d\] -.*: c460800a prfb pstl2keep, p0, \[x0,z0\.d\] -.*: c460800a prfb pstl2keep, p0, \[x0,z0\.d\] -.*: c460800a prfb pstl2keep, p0, \[x0,z0\.d\] -.*: c460800b prfb pstl2strm, p0, \[x0,z0\.d\] -.*: c460800b prfb pstl2strm, p0, \[x0,z0\.d\] -.*: c460800b prfb pstl2strm, p0, \[x0,z0\.d\] -.*: c460800c prfb pstl3keep, p0, \[x0,z0\.d\] -.*: c460800c prfb pstl3keep, p0, \[x0,z0\.d\] -.*: c460800c prfb pstl3keep, p0, \[x0,z0\.d\] -.*: c460800d prfb pstl3strm, p0, \[x0,z0\.d\] -.*: c460800d prfb pstl3strm, p0, \[x0,z0\.d\] -.*: c460800d prfb pstl3strm, p0, \[x0,z0\.d\] -.*: c460800e prfb #14, p0, \[x0,z0\.d\] -.*: c460800e prfb #14, p0, \[x0,z0\.d\] -.*: c460800e prfb #14, p0, \[x0,z0\.d\] -.*: c460800f prfb #15, p0, \[x0,z0\.d\] -.*: c460800f prfb #15, p0, \[x0,z0\.d\] -.*: c460800f prfb #15, p0, \[x0,z0\.d\] -.*: c4608800 prfb pldl1keep, p2, \[x0,z0\.d\] -.*: c4608800 prfb pldl1keep, p2, \[x0,z0\.d\] -.*: c4608800 prfb pldl1keep, p2, \[x0,z0\.d\] -.*: c4609c00 prfb pldl1keep, p7, \[x0,z0\.d\] -.*: c4609c00 prfb pldl1keep, p7, \[x0,z0\.d\] -.*: c4609c00 prfb pldl1keep, p7, \[x0,z0\.d\] -.*: c4608060 prfb pldl1keep, p0, \[x3,z0\.d\] -.*: c4608060 prfb pldl1keep, p0, \[x3,z0\.d\] -.*: c4608060 prfb pldl1keep, p0, \[x3,z0\.d\] -.*: c46083e0 prfb pldl1keep, p0, \[sp,z0\.d\] -.*: c46083e0 prfb pldl1keep, p0, \[sp,z0\.d\] -.*: c46083e0 prfb pldl1keep, p0, \[sp,z0\.d\] -.*: c4648000 prfb pldl1keep, p0, \[x0,z4\.d\] -.*: c4648000 prfb pldl1keep, p0, \[x0,z4\.d\] -.*: c4648000 prfb pldl1keep, p0, \[x0,z4\.d\] -.*: c47f8000 prfb pldl1keep, p0, \[x0,z31\.d\] -.*: c47f8000 prfb pldl1keep, p0, \[x0,z31\.d\] -.*: c47f8000 prfb pldl1keep, p0, \[x0,z31\.d\] +.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\] +.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\] +.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\] +.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\] +.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\] +.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\] +.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\] +.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\] +.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\] +.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\] +.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\] +.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\] +.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\] +.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\] +.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\] +.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\] +.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\] +.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\] +.*: 8400c006 prfb #6, p0, \[x0, x0\] +.*: 8400c006 prfb #6, p0, \[x0, x0\] +.*: 8400c006 prfb #6, p0, \[x0, x0\] +.*: 8400c007 prfb #7, p0, \[x0, x0\] +.*: 8400c007 prfb #7, p0, \[x0, x0\] +.*: 8400c007 prfb #7, p0, \[x0, x0\] +.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\] +.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\] +.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\] +.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\] +.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\] +.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\] +.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\] +.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\] +.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\] +.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\] +.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\] +.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\] +.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\] +.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\] +.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\] +.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\] +.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\] +.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\] +.*: 8400c00e prfb #14, p0, \[x0, x0\] +.*: 8400c00e prfb #14, p0, \[x0, x0\] +.*: 8400c00e prfb #14, p0, \[x0, x0\] +.*: 8400c00f prfb #15, p0, \[x0, x0\] +.*: 8400c00f prfb #15, p0, \[x0, x0\] +.*: 8400c00f prfb #15, p0, \[x0, x0\] +.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\] +.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\] +.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\] +.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\] +.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\] +.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\] +.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\] +.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\] +.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\] +.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\] +.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\] +.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\] +.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\] +.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\] +.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\] +.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\] +.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\] +.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\] +.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\] +.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\] +.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\] +.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\] +.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\] +.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\] +.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\] +.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\] +.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\] +.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\] +.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\] +.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\] +.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\] +.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\] +.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\] +.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\] +.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\] +.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\] +.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\] +.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\] +.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\] +.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\] +.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\] +.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\] +.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\] +.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\] +.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\] +.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\] +.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\] +.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\] +.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\] +.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\] +.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\] +.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\] +.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\] +.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\] +.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\] +.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\] +.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\] +.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\] +.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\] +.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\] +.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\] +.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\] +.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\] +.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\] +.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\] +.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\] +.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\] +.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\] +.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\] +.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\] +.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\] +.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\] +.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\] +.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\] +.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\] +.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\] +.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\] +.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\] +.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\] +.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\] +.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\] +.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\] +.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\] +.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\] +.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\] +.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\] +.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\] +.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\] +.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\] +.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\] +.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\] +.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\] +.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\] +.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\] +.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\] +.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\] +.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\] +.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\] +.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\] +.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\] +.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\] +.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\] +.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\] +.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\] +.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\] +.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\] +.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\] +.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\] +.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\] +.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\] +.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\] +.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\] +.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\] +.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\] +.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\] +.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\] +.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\] +.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\] +.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\] +.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\] +.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\] +.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\] +.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\] +.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\] +.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\] +.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\] +.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\] +.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\] +.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\] +.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\] +.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\] +.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\] +.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\] +.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\] +.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\] +.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\] +.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\] +.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\] +.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\] +.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\] +.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\] +.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\] +.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\] +.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\] +.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\] +.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\] +.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\] +.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\] +.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\] +.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\] +.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\] +.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\] +.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\] +.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\] +.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\] +.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\] +.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\] +.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\] +.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\] +.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\] +.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\] +.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\] +.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\] +.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\] +.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\] +.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\] +.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\] +.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\] +.*: c4608006 prfb #6, p0, \[x0, z0\.d\] +.*: c4608006 prfb #6, p0, \[x0, z0\.d\] +.*: c4608006 prfb #6, p0, \[x0, z0\.d\] +.*: c4608007 prfb #7, p0, \[x0, z0\.d\] +.*: c4608007 prfb #7, p0, \[x0, z0\.d\] +.*: c4608007 prfb #7, p0, \[x0, z0\.d\] +.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\] +.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\] +.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\] +.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\] +.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\] +.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\] +.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\] +.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\] +.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\] +.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\] +.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\] +.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\] +.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\] +.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\] +.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\] +.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\] +.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\] +.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\] +.*: c460800e prfb #14, p0, \[x0, z0\.d\] +.*: c460800e prfb #14, p0, \[x0, z0\.d\] +.*: c460800e prfb #14, p0, \[x0, z0\.d\] +.*: c460800f prfb #15, p0, \[x0, z0\.d\] +.*: c460800f prfb #15, p0, \[x0, z0\.d\] +.*: c460800f prfb #15, p0, \[x0, z0\.d\] +.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\] +.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\] +.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\] +.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\] +.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\] +.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\] +.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\] +.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\] +.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\] +.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\] +.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\] +.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\] +.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\] +.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\] +.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\] +.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\] +.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\] +.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\] .*: 8400e000 prfb pldl1keep, p0, \[z0\.s\] .*: 8400e000 prfb pldl1keep, p0, \[z0\.s\] .*: 8400e000 prfb pldl1keep, p0, \[z0\.s\] @@ -22442,14 +22442,14 @@ Disassembly of section .*: .*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\] .*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\] .*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\] -.*: 840fe000 prfb pldl1keep, p0, \[z0\.s,#15\] -.*: 840fe000 prfb pldl1keep, p0, \[z0\.s,#15\] -.*: 8410e000 prfb pldl1keep, p0, \[z0\.s,#16\] -.*: 8410e000 prfb pldl1keep, p0, \[z0\.s,#16\] -.*: 8411e000 prfb pldl1keep, p0, \[z0\.s,#17\] -.*: 8411e000 prfb pldl1keep, p0, \[z0\.s,#17\] -.*: 841fe000 prfb pldl1keep, p0, \[z0\.s,#31\] -.*: 841fe000 prfb pldl1keep, p0, \[z0\.s,#31\] +.*: 840fe000 prfb pldl1keep, p0, \[z0\.s, #15\] +.*: 840fe000 prfb pldl1keep, p0, \[z0\.s, #15\] +.*: 8410e000 prfb pldl1keep, p0, \[z0\.s, #16\] +.*: 8410e000 prfb pldl1keep, p0, \[z0\.s, #16\] +.*: 8411e000 prfb pldl1keep, p0, \[z0\.s, #17\] +.*: 8411e000 prfb pldl1keep, p0, \[z0\.s, #17\] +.*: 841fe000 prfb pldl1keep, p0, \[z0\.s, #31\] +.*: 841fe000 prfb pldl1keep, p0, \[z0\.s, #31\] .*: 85c00000 prfb pldl1keep, p0, \[x0\] .*: 85c00000 prfb pldl1keep, p0, \[x0\] .*: 85c00000 prfb pldl1keep, p0, \[x0\] @@ -22530,14 +22530,14 @@ Disassembly of section .*: .*: 85c003e0 prfb pldl1keep, p0, \[sp\] .*: 85c003e0 prfb pldl1keep, p0, \[sp\] .*: 85c003e0 prfb pldl1keep, p0, \[sp\] -.*: 85df0000 prfb pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85df0000 prfb pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85e00000 prfb pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e00000 prfb pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e10000 prfb pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85e10000 prfb pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85ff0000 prfb pldl1keep, p0, \[x0,#-1,mul vl\] -.*: 85ff0000 prfb pldl1keep, p0, \[x0,#-1,mul vl\] +.*: 85df0000 prfb pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85df0000 prfb pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85e00000 prfb pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e00000 prfb pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e10000 prfb pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85e10000 prfb pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85ff0000 prfb pldl1keep, p0, \[x0, #-1, mul vl\] +.*: 85ff0000 prfb pldl1keep, p0, \[x0, #-1, mul vl\] .*: c400e000 prfb pldl1keep, p0, \[z0\.d\] .*: c400e000 prfb pldl1keep, p0, \[z0\.d\] .*: c400e000 prfb pldl1keep, p0, \[z0\.d\] @@ -22598,278 +22598,278 @@ Disassembly of section .*: .*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\] .*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\] .*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\] -.*: c40fe000 prfb pldl1keep, p0, \[z0\.d,#15\] -.*: c40fe000 prfb pldl1keep, p0, \[z0\.d,#15\] -.*: c410e000 prfb pldl1keep, p0, \[z0\.d,#16\] -.*: c410e000 prfb pldl1keep, p0, \[z0\.d,#16\] -.*: c411e000 prfb pldl1keep, p0, \[z0\.d,#17\] -.*: c411e000 prfb pldl1keep, p0, \[z0\.d,#17\] -.*: c41fe000 prfb pldl1keep, p0, \[z0\.d,#31\] -.*: c41fe000 prfb pldl1keep, p0, \[z0\.d,#31\] -.*: 84206000 prfd pldl1keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206000 prfd pldl1keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206001 prfd pldl1strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206001 prfd pldl1strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206002 prfd pldl2keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206002 prfd pldl2keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206003 prfd pldl2strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206003 prfd pldl2strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206004 prfd pldl3keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206004 prfd pldl3keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206005 prfd pldl3strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206005 prfd pldl3strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206006 prfd #6, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206006 prfd #6, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206007 prfd #7, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206007 prfd #7, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206008 prfd pstl1keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206008 prfd pstl1keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206009 prfd pstl1strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206009 prfd pstl1strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600a prfd pstl2keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600a prfd pstl2keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600b prfd pstl2strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600b prfd pstl2strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600c prfd pstl3keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600c prfd pstl3keep, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600d prfd pstl3strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600d prfd pstl3strm, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600e prfd #14, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600e prfd #14, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600f prfd #15, p0, \[x0,z0\.s,uxtw #3\] -.*: 8420600f prfd #15, p0, \[x0,z0\.s,uxtw #3\] -.*: 84206800 prfd pldl1keep, p2, \[x0,z0\.s,uxtw #3\] -.*: 84206800 prfd pldl1keep, p2, \[x0,z0\.s,uxtw #3\] -.*: 84207c00 prfd pldl1keep, p7, \[x0,z0\.s,uxtw #3\] -.*: 84207c00 prfd pldl1keep, p7, \[x0,z0\.s,uxtw #3\] -.*: 84206060 prfd pldl1keep, p0, \[x3,z0\.s,uxtw #3\] -.*: 84206060 prfd pldl1keep, p0, \[x3,z0\.s,uxtw #3\] -.*: 842063e0 prfd pldl1keep, p0, \[sp,z0\.s,uxtw #3\] -.*: 842063e0 prfd pldl1keep, p0, \[sp,z0\.s,uxtw #3\] -.*: 84246000 prfd pldl1keep, p0, \[x0,z4\.s,uxtw #3\] -.*: 84246000 prfd pldl1keep, p0, \[x0,z4\.s,uxtw #3\] -.*: 843f6000 prfd pldl1keep, p0, \[x0,z31\.s,uxtw #3\] -.*: 843f6000 prfd pldl1keep, p0, \[x0,z31\.s,uxtw #3\] -.*: 84606000 prfd pldl1keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606000 prfd pldl1keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606001 prfd pldl1strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606001 prfd pldl1strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606002 prfd pldl2keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606002 prfd pldl2keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606003 prfd pldl2strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606003 prfd pldl2strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606004 prfd pldl3keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606004 prfd pldl3keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606005 prfd pldl3strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606005 prfd pldl3strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606006 prfd #6, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606006 prfd #6, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606007 prfd #7, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606007 prfd #7, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606008 prfd pstl1keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606008 prfd pstl1keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606009 prfd pstl1strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606009 prfd pstl1strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600a prfd pstl2keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600a prfd pstl2keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600b prfd pstl2strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600b prfd pstl2strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600c prfd pstl3keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600c prfd pstl3keep, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600d prfd pstl3strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600d prfd pstl3strm, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600e prfd #14, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600e prfd #14, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600f prfd #15, p0, \[x0,z0\.s,sxtw #3\] -.*: 8460600f prfd #15, p0, \[x0,z0\.s,sxtw #3\] -.*: 84606800 prfd pldl1keep, p2, \[x0,z0\.s,sxtw #3\] -.*: 84606800 prfd pldl1keep, p2, \[x0,z0\.s,sxtw #3\] -.*: 84607c00 prfd pldl1keep, p7, \[x0,z0\.s,sxtw #3\] -.*: 84607c00 prfd pldl1keep, p7, \[x0,z0\.s,sxtw #3\] -.*: 84606060 prfd pldl1keep, p0, \[x3,z0\.s,sxtw #3\] -.*: 84606060 prfd pldl1keep, p0, \[x3,z0\.s,sxtw #3\] -.*: 846063e0 prfd pldl1keep, p0, \[sp,z0\.s,sxtw #3\] -.*: 846063e0 prfd pldl1keep, p0, \[sp,z0\.s,sxtw #3\] -.*: 84646000 prfd pldl1keep, p0, \[x0,z4\.s,sxtw #3\] -.*: 84646000 prfd pldl1keep, p0, \[x0,z4\.s,sxtw #3\] -.*: 847f6000 prfd pldl1keep, p0, \[x0,z31\.s,sxtw #3\] -.*: 847f6000 prfd pldl1keep, p0, \[x0,z31\.s,sxtw #3\] -.*: 8580c000 prfd pldl1keep, p0, \[x0,x0,lsl #3\] -.*: 8580c000 prfd pldl1keep, p0, \[x0,x0,lsl #3\] -.*: 8580c001 prfd pldl1strm, p0, \[x0,x0,lsl #3\] -.*: 8580c001 prfd pldl1strm, p0, \[x0,x0,lsl #3\] -.*: 8580c002 prfd pldl2keep, p0, \[x0,x0,lsl #3\] -.*: 8580c002 prfd pldl2keep, p0, \[x0,x0,lsl #3\] -.*: 8580c003 prfd pldl2strm, p0, \[x0,x0,lsl #3\] -.*: 8580c003 prfd pldl2strm, p0, \[x0,x0,lsl #3\] -.*: 8580c004 prfd pldl3keep, p0, \[x0,x0,lsl #3\] -.*: 8580c004 prfd pldl3keep, p0, \[x0,x0,lsl #3\] -.*: 8580c005 prfd pldl3strm, p0, \[x0,x0,lsl #3\] -.*: 8580c005 prfd pldl3strm, p0, \[x0,x0,lsl #3\] -.*: 8580c006 prfd #6, p0, \[x0,x0,lsl #3\] -.*: 8580c006 prfd #6, p0, \[x0,x0,lsl #3\] -.*: 8580c007 prfd #7, p0, \[x0,x0,lsl #3\] -.*: 8580c007 prfd #7, p0, \[x0,x0,lsl #3\] -.*: 8580c008 prfd pstl1keep, p0, \[x0,x0,lsl #3\] -.*: 8580c008 prfd pstl1keep, p0, \[x0,x0,lsl #3\] -.*: 8580c009 prfd pstl1strm, p0, \[x0,x0,lsl #3\] -.*: 8580c009 prfd pstl1strm, p0, \[x0,x0,lsl #3\] -.*: 8580c00a prfd pstl2keep, p0, \[x0,x0,lsl #3\] -.*: 8580c00a prfd pstl2keep, p0, \[x0,x0,lsl #3\] -.*: 8580c00b prfd pstl2strm, p0, \[x0,x0,lsl #3\] -.*: 8580c00b prfd pstl2strm, p0, \[x0,x0,lsl #3\] -.*: 8580c00c prfd pstl3keep, p0, \[x0,x0,lsl #3\] -.*: 8580c00c prfd pstl3keep, p0, \[x0,x0,lsl #3\] -.*: 8580c00d prfd pstl3strm, p0, \[x0,x0,lsl #3\] -.*: 8580c00d prfd pstl3strm, p0, \[x0,x0,lsl #3\] -.*: 8580c00e prfd #14, p0, \[x0,x0,lsl #3\] -.*: 8580c00e prfd #14, p0, \[x0,x0,lsl #3\] -.*: 8580c00f prfd #15, p0, \[x0,x0,lsl #3\] -.*: 8580c00f prfd #15, p0, \[x0,x0,lsl #3\] -.*: 8580c800 prfd pldl1keep, p2, \[x0,x0,lsl #3\] -.*: 8580c800 prfd pldl1keep, p2, \[x0,x0,lsl #3\] -.*: 8580dc00 prfd pldl1keep, p7, \[x0,x0,lsl #3\] -.*: 8580dc00 prfd pldl1keep, p7, \[x0,x0,lsl #3\] -.*: 8580c060 prfd pldl1keep, p0, \[x3,x0,lsl #3\] -.*: 8580c060 prfd pldl1keep, p0, \[x3,x0,lsl #3\] -.*: 8580c3e0 prfd pldl1keep, p0, \[sp,x0,lsl #3\] -.*: 8580c3e0 prfd pldl1keep, p0, \[sp,x0,lsl #3\] -.*: 8584c000 prfd pldl1keep, p0, \[x0,x4,lsl #3\] -.*: 8584c000 prfd pldl1keep, p0, \[x0,x4,lsl #3\] -.*: 859ec000 prfd pldl1keep, p0, \[x0,x30,lsl #3\] -.*: 859ec000 prfd pldl1keep, p0, \[x0,x30,lsl #3\] -.*: c4206000 prfd pldl1keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206000 prfd pldl1keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206001 prfd pldl1strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206001 prfd pldl1strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206002 prfd pldl2keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206002 prfd pldl2keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206003 prfd pldl2strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206003 prfd pldl2strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206004 prfd pldl3keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206004 prfd pldl3keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206005 prfd pldl3strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206005 prfd pldl3strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206006 prfd #6, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206006 prfd #6, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206007 prfd #7, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206007 prfd #7, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206008 prfd pstl1keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206008 prfd pstl1keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206009 prfd pstl1strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206009 prfd pstl1strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600a prfd pstl2keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600a prfd pstl2keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600b prfd pstl2strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600b prfd pstl2strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600c prfd pstl3keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600c prfd pstl3keep, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600d prfd pstl3strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600d prfd pstl3strm, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600e prfd #14, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600e prfd #14, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600f prfd #15, p0, \[x0,z0\.d,uxtw #3\] -.*: c420600f prfd #15, p0, \[x0,z0\.d,uxtw #3\] -.*: c4206800 prfd pldl1keep, p2, \[x0,z0\.d,uxtw #3\] -.*: c4206800 prfd pldl1keep, p2, \[x0,z0\.d,uxtw #3\] -.*: c4207c00 prfd pldl1keep, p7, \[x0,z0\.d,uxtw #3\] -.*: c4207c00 prfd pldl1keep, p7, \[x0,z0\.d,uxtw #3\] -.*: c4206060 prfd pldl1keep, p0, \[x3,z0\.d,uxtw #3\] -.*: c4206060 prfd pldl1keep, p0, \[x3,z0\.d,uxtw #3\] -.*: c42063e0 prfd pldl1keep, p0, \[sp,z0\.d,uxtw #3\] -.*: c42063e0 prfd pldl1keep, p0, \[sp,z0\.d,uxtw #3\] -.*: c4246000 prfd pldl1keep, p0, \[x0,z4\.d,uxtw #3\] -.*: c4246000 prfd pldl1keep, p0, \[x0,z4\.d,uxtw #3\] -.*: c43f6000 prfd pldl1keep, p0, \[x0,z31\.d,uxtw #3\] -.*: c43f6000 prfd pldl1keep, p0, \[x0,z31\.d,uxtw #3\] -.*: c4606000 prfd pldl1keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606000 prfd pldl1keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606001 prfd pldl1strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606001 prfd pldl1strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606002 prfd pldl2keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606002 prfd pldl2keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606003 prfd pldl2strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606003 prfd pldl2strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606004 prfd pldl3keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606004 prfd pldl3keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606005 prfd pldl3strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606005 prfd pldl3strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606006 prfd #6, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606006 prfd #6, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606007 prfd #7, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606007 prfd #7, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606008 prfd pstl1keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606008 prfd pstl1keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606009 prfd pstl1strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606009 prfd pstl1strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600a prfd pstl2keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600a prfd pstl2keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600b prfd pstl2strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600b prfd pstl2strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600c prfd pstl3keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600c prfd pstl3keep, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600d prfd pstl3strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600d prfd pstl3strm, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600e prfd #14, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600e prfd #14, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600f prfd #15, p0, \[x0,z0\.d,sxtw #3\] -.*: c460600f prfd #15, p0, \[x0,z0\.d,sxtw #3\] -.*: c4606800 prfd pldl1keep, p2, \[x0,z0\.d,sxtw #3\] -.*: c4606800 prfd pldl1keep, p2, \[x0,z0\.d,sxtw #3\] -.*: c4607c00 prfd pldl1keep, p7, \[x0,z0\.d,sxtw #3\] -.*: c4607c00 prfd pldl1keep, p7, \[x0,z0\.d,sxtw #3\] -.*: c4606060 prfd pldl1keep, p0, \[x3,z0\.d,sxtw #3\] -.*: c4606060 prfd pldl1keep, p0, \[x3,z0\.d,sxtw #3\] -.*: c46063e0 prfd pldl1keep, p0, \[sp,z0\.d,sxtw #3\] -.*: c46063e0 prfd pldl1keep, p0, \[sp,z0\.d,sxtw #3\] -.*: c4646000 prfd pldl1keep, p0, \[x0,z4\.d,sxtw #3\] -.*: c4646000 prfd pldl1keep, p0, \[x0,z4\.d,sxtw #3\] -.*: c47f6000 prfd pldl1keep, p0, \[x0,z31\.d,sxtw #3\] -.*: c47f6000 prfd pldl1keep, p0, \[x0,z31\.d,sxtw #3\] -.*: c460e000 prfd pldl1keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e000 prfd pldl1keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e001 prfd pldl1strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e001 prfd pldl1strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e002 prfd pldl2keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e002 prfd pldl2keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e003 prfd pldl2strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e003 prfd pldl2strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e004 prfd pldl3keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e004 prfd pldl3keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e005 prfd pldl3strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e005 prfd pldl3strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e006 prfd #6, p0, \[x0,z0\.d,lsl #3\] -.*: c460e006 prfd #6, p0, \[x0,z0\.d,lsl #3\] -.*: c460e007 prfd #7, p0, \[x0,z0\.d,lsl #3\] -.*: c460e007 prfd #7, p0, \[x0,z0\.d,lsl #3\] -.*: c460e008 prfd pstl1keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e008 prfd pstl1keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e009 prfd pstl1strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e009 prfd pstl1strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00a prfd pstl2keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00a prfd pstl2keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00b prfd pstl2strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00b prfd pstl2strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00c prfd pstl3keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00c prfd pstl3keep, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00d prfd pstl3strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00d prfd pstl3strm, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00e prfd #14, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00e prfd #14, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00f prfd #15, p0, \[x0,z0\.d,lsl #3\] -.*: c460e00f prfd #15, p0, \[x0,z0\.d,lsl #3\] -.*: c460e800 prfd pldl1keep, p2, \[x0,z0\.d,lsl #3\] -.*: c460e800 prfd pldl1keep, p2, \[x0,z0\.d,lsl #3\] -.*: c460fc00 prfd pldl1keep, p7, \[x0,z0\.d,lsl #3\] -.*: c460fc00 prfd pldl1keep, p7, \[x0,z0\.d,lsl #3\] -.*: c460e060 prfd pldl1keep, p0, \[x3,z0\.d,lsl #3\] -.*: c460e060 prfd pldl1keep, p0, \[x3,z0\.d,lsl #3\] -.*: c460e3e0 prfd pldl1keep, p0, \[sp,z0\.d,lsl #3\] -.*: c460e3e0 prfd pldl1keep, p0, \[sp,z0\.d,lsl #3\] -.*: c464e000 prfd pldl1keep, p0, \[x0,z4\.d,lsl #3\] -.*: c464e000 prfd pldl1keep, p0, \[x0,z4\.d,lsl #3\] -.*: c47fe000 prfd pldl1keep, p0, \[x0,z31\.d,lsl #3\] -.*: c47fe000 prfd pldl1keep, p0, \[x0,z31\.d,lsl #3\] +.*: c40fe000 prfb pldl1keep, p0, \[z0\.d, #15\] +.*: c40fe000 prfb pldl1keep, p0, \[z0\.d, #15\] +.*: c410e000 prfb pldl1keep, p0, \[z0\.d, #16\] +.*: c410e000 prfb pldl1keep, p0, \[z0\.d, #16\] +.*: c411e000 prfb pldl1keep, p0, \[z0\.d, #17\] +.*: c411e000 prfb pldl1keep, p0, \[z0\.d, #17\] +.*: c41fe000 prfb pldl1keep, p0, \[z0\.d, #31\] +.*: c41fe000 prfb pldl1keep, p0, \[z0\.d, #31\] +.*: 84206000 prfd pldl1keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206000 prfd pldl1keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206001 prfd pldl1strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206001 prfd pldl1strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206002 prfd pldl2keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206002 prfd pldl2keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206003 prfd pldl2strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206003 prfd pldl2strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206004 prfd pldl3keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206004 prfd pldl3keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206005 prfd pldl3strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206005 prfd pldl3strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206006 prfd #6, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206006 prfd #6, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206007 prfd #7, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206007 prfd #7, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206008 prfd pstl1keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206008 prfd pstl1keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206009 prfd pstl1strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206009 prfd pstl1strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600a prfd pstl2keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600a prfd pstl2keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600b prfd pstl2strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600b prfd pstl2strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600c prfd pstl3keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600c prfd pstl3keep, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600d prfd pstl3strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600d prfd pstl3strm, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600e prfd #14, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600e prfd #14, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600f prfd #15, p0, \[x0, z0\.s, uxtw #3\] +.*: 8420600f prfd #15, p0, \[x0, z0\.s, uxtw #3\] +.*: 84206800 prfd pldl1keep, p2, \[x0, z0\.s, uxtw #3\] +.*: 84206800 prfd pldl1keep, p2, \[x0, z0\.s, uxtw #3\] +.*: 84207c00 prfd pldl1keep, p7, \[x0, z0\.s, uxtw #3\] +.*: 84207c00 prfd pldl1keep, p7, \[x0, z0\.s, uxtw #3\] +.*: 84206060 prfd pldl1keep, p0, \[x3, z0\.s, uxtw #3\] +.*: 84206060 prfd pldl1keep, p0, \[x3, z0\.s, uxtw #3\] +.*: 842063e0 prfd pldl1keep, p0, \[sp, z0\.s, uxtw #3\] +.*: 842063e0 prfd pldl1keep, p0, \[sp, z0\.s, uxtw #3\] +.*: 84246000 prfd pldl1keep, p0, \[x0, z4\.s, uxtw #3\] +.*: 84246000 prfd pldl1keep, p0, \[x0, z4\.s, uxtw #3\] +.*: 843f6000 prfd pldl1keep, p0, \[x0, z31\.s, uxtw #3\] +.*: 843f6000 prfd pldl1keep, p0, \[x0, z31\.s, uxtw #3\] +.*: 84606000 prfd pldl1keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606000 prfd pldl1keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606001 prfd pldl1strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606001 prfd pldl1strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606002 prfd pldl2keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606002 prfd pldl2keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606003 prfd pldl2strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606003 prfd pldl2strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606004 prfd pldl3keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606004 prfd pldl3keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606005 prfd pldl3strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606005 prfd pldl3strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606006 prfd #6, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606006 prfd #6, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606007 prfd #7, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606007 prfd #7, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606008 prfd pstl1keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606008 prfd pstl1keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606009 prfd pstl1strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606009 prfd pstl1strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600a prfd pstl2keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600a prfd pstl2keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600b prfd pstl2strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600b prfd pstl2strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600c prfd pstl3keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600c prfd pstl3keep, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600d prfd pstl3strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600d prfd pstl3strm, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600e prfd #14, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600e prfd #14, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600f prfd #15, p0, \[x0, z0\.s, sxtw #3\] +.*: 8460600f prfd #15, p0, \[x0, z0\.s, sxtw #3\] +.*: 84606800 prfd pldl1keep, p2, \[x0, z0\.s, sxtw #3\] +.*: 84606800 prfd pldl1keep, p2, \[x0, z0\.s, sxtw #3\] +.*: 84607c00 prfd pldl1keep, p7, \[x0, z0\.s, sxtw #3\] +.*: 84607c00 prfd pldl1keep, p7, \[x0, z0\.s, sxtw #3\] +.*: 84606060 prfd pldl1keep, p0, \[x3, z0\.s, sxtw #3\] +.*: 84606060 prfd pldl1keep, p0, \[x3, z0\.s, sxtw #3\] +.*: 846063e0 prfd pldl1keep, p0, \[sp, z0\.s, sxtw #3\] +.*: 846063e0 prfd pldl1keep, p0, \[sp, z0\.s, sxtw #3\] +.*: 84646000 prfd pldl1keep, p0, \[x0, z4\.s, sxtw #3\] +.*: 84646000 prfd pldl1keep, p0, \[x0, z4\.s, sxtw #3\] +.*: 847f6000 prfd pldl1keep, p0, \[x0, z31\.s, sxtw #3\] +.*: 847f6000 prfd pldl1keep, p0, \[x0, z31\.s, sxtw #3\] +.*: 8580c000 prfd pldl1keep, p0, \[x0, x0, lsl #3\] +.*: 8580c000 prfd pldl1keep, p0, \[x0, x0, lsl #3\] +.*: 8580c001 prfd pldl1strm, p0, \[x0, x0, lsl #3\] +.*: 8580c001 prfd pldl1strm, p0, \[x0, x0, lsl #3\] +.*: 8580c002 prfd pldl2keep, p0, \[x0, x0, lsl #3\] +.*: 8580c002 prfd pldl2keep, p0, \[x0, x0, lsl #3\] +.*: 8580c003 prfd pldl2strm, p0, \[x0, x0, lsl #3\] +.*: 8580c003 prfd pldl2strm, p0, \[x0, x0, lsl #3\] +.*: 8580c004 prfd pldl3keep, p0, \[x0, x0, lsl #3\] +.*: 8580c004 prfd pldl3keep, p0, \[x0, x0, lsl #3\] +.*: 8580c005 prfd pldl3strm, p0, \[x0, x0, lsl #3\] +.*: 8580c005 prfd pldl3strm, p0, \[x0, x0, lsl #3\] +.*: 8580c006 prfd #6, p0, \[x0, x0, lsl #3\] +.*: 8580c006 prfd #6, p0, \[x0, x0, lsl #3\] +.*: 8580c007 prfd #7, p0, \[x0, x0, lsl #3\] +.*: 8580c007 prfd #7, p0, \[x0, x0, lsl #3\] +.*: 8580c008 prfd pstl1keep, p0, \[x0, x0, lsl #3\] +.*: 8580c008 prfd pstl1keep, p0, \[x0, x0, lsl #3\] +.*: 8580c009 prfd pstl1strm, p0, \[x0, x0, lsl #3\] +.*: 8580c009 prfd pstl1strm, p0, \[x0, x0, lsl #3\] +.*: 8580c00a prfd pstl2keep, p0, \[x0, x0, lsl #3\] +.*: 8580c00a prfd pstl2keep, p0, \[x0, x0, lsl #3\] +.*: 8580c00b prfd pstl2strm, p0, \[x0, x0, lsl #3\] +.*: 8580c00b prfd pstl2strm, p0, \[x0, x0, lsl #3\] +.*: 8580c00c prfd pstl3keep, p0, \[x0, x0, lsl #3\] +.*: 8580c00c prfd pstl3keep, p0, \[x0, x0, lsl #3\] +.*: 8580c00d prfd pstl3strm, p0, \[x0, x0, lsl #3\] +.*: 8580c00d prfd pstl3strm, p0, \[x0, x0, lsl #3\] +.*: 8580c00e prfd #14, p0, \[x0, x0, lsl #3\] +.*: 8580c00e prfd #14, p0, \[x0, x0, lsl #3\] +.*: 8580c00f prfd #15, p0, \[x0, x0, lsl #3\] +.*: 8580c00f prfd #15, p0, \[x0, x0, lsl #3\] +.*: 8580c800 prfd pldl1keep, p2, \[x0, x0, lsl #3\] +.*: 8580c800 prfd pldl1keep, p2, \[x0, x0, lsl #3\] +.*: 8580dc00 prfd pldl1keep, p7, \[x0, x0, lsl #3\] +.*: 8580dc00 prfd pldl1keep, p7, \[x0, x0, lsl #3\] +.*: 8580c060 prfd pldl1keep, p0, \[x3, x0, lsl #3\] +.*: 8580c060 prfd pldl1keep, p0, \[x3, x0, lsl #3\] +.*: 8580c3e0 prfd pldl1keep, p0, \[sp, x0, lsl #3\] +.*: 8580c3e0 prfd pldl1keep, p0, \[sp, x0, lsl #3\] +.*: 8584c000 prfd pldl1keep, p0, \[x0, x4, lsl #3\] +.*: 8584c000 prfd pldl1keep, p0, \[x0, x4, lsl #3\] +.*: 859ec000 prfd pldl1keep, p0, \[x0, x30, lsl #3\] +.*: 859ec000 prfd pldl1keep, p0, \[x0, x30, lsl #3\] +.*: c4206000 prfd pldl1keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206000 prfd pldl1keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206001 prfd pldl1strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206001 prfd pldl1strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206002 prfd pldl2keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206002 prfd pldl2keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206003 prfd pldl2strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206003 prfd pldl2strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206004 prfd pldl3keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206004 prfd pldl3keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206005 prfd pldl3strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206005 prfd pldl3strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206006 prfd #6, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206006 prfd #6, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206007 prfd #7, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206007 prfd #7, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206008 prfd pstl1keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206008 prfd pstl1keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206009 prfd pstl1strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206009 prfd pstl1strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600a prfd pstl2keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600a prfd pstl2keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600b prfd pstl2strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600b prfd pstl2strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600c prfd pstl3keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600c prfd pstl3keep, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600d prfd pstl3strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600d prfd pstl3strm, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600e prfd #14, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600e prfd #14, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600f prfd #15, p0, \[x0, z0\.d, uxtw #3\] +.*: c420600f prfd #15, p0, \[x0, z0\.d, uxtw #3\] +.*: c4206800 prfd pldl1keep, p2, \[x0, z0\.d, uxtw #3\] +.*: c4206800 prfd pldl1keep, p2, \[x0, z0\.d, uxtw #3\] +.*: c4207c00 prfd pldl1keep, p7, \[x0, z0\.d, uxtw #3\] +.*: c4207c00 prfd pldl1keep, p7, \[x0, z0\.d, uxtw #3\] +.*: c4206060 prfd pldl1keep, p0, \[x3, z0\.d, uxtw #3\] +.*: c4206060 prfd pldl1keep, p0, \[x3, z0\.d, uxtw #3\] +.*: c42063e0 prfd pldl1keep, p0, \[sp, z0\.d, uxtw #3\] +.*: c42063e0 prfd pldl1keep, p0, \[sp, z0\.d, uxtw #3\] +.*: c4246000 prfd pldl1keep, p0, \[x0, z4\.d, uxtw #3\] +.*: c4246000 prfd pldl1keep, p0, \[x0, z4\.d, uxtw #3\] +.*: c43f6000 prfd pldl1keep, p0, \[x0, z31\.d, uxtw #3\] +.*: c43f6000 prfd pldl1keep, p0, \[x0, z31\.d, uxtw #3\] +.*: c4606000 prfd pldl1keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606000 prfd pldl1keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606001 prfd pldl1strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606001 prfd pldl1strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606002 prfd pldl2keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606002 prfd pldl2keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606003 prfd pldl2strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606003 prfd pldl2strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606004 prfd pldl3keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606004 prfd pldl3keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606005 prfd pldl3strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606005 prfd pldl3strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606006 prfd #6, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606006 prfd #6, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606007 prfd #7, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606007 prfd #7, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606008 prfd pstl1keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606008 prfd pstl1keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606009 prfd pstl1strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606009 prfd pstl1strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600a prfd pstl2keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600a prfd pstl2keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600b prfd pstl2strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600b prfd pstl2strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600c prfd pstl3keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600c prfd pstl3keep, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600d prfd pstl3strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600d prfd pstl3strm, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600e prfd #14, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600e prfd #14, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600f prfd #15, p0, \[x0, z0\.d, sxtw #3\] +.*: c460600f prfd #15, p0, \[x0, z0\.d, sxtw #3\] +.*: c4606800 prfd pldl1keep, p2, \[x0, z0\.d, sxtw #3\] +.*: c4606800 prfd pldl1keep, p2, \[x0, z0\.d, sxtw #3\] +.*: c4607c00 prfd pldl1keep, p7, \[x0, z0\.d, sxtw #3\] +.*: c4607c00 prfd pldl1keep, p7, \[x0, z0\.d, sxtw #3\] +.*: c4606060 prfd pldl1keep, p0, \[x3, z0\.d, sxtw #3\] +.*: c4606060 prfd pldl1keep, p0, \[x3, z0\.d, sxtw #3\] +.*: c46063e0 prfd pldl1keep, p0, \[sp, z0\.d, sxtw #3\] +.*: c46063e0 prfd pldl1keep, p0, \[sp, z0\.d, sxtw #3\] +.*: c4646000 prfd pldl1keep, p0, \[x0, z4\.d, sxtw #3\] +.*: c4646000 prfd pldl1keep, p0, \[x0, z4\.d, sxtw #3\] +.*: c47f6000 prfd pldl1keep, p0, \[x0, z31\.d, sxtw #3\] +.*: c47f6000 prfd pldl1keep, p0, \[x0, z31\.d, sxtw #3\] +.*: c460e000 prfd pldl1keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e000 prfd pldl1keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e001 prfd pldl1strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e001 prfd pldl1strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e002 prfd pldl2keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e002 prfd pldl2keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e003 prfd pldl2strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e003 prfd pldl2strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e004 prfd pldl3keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e004 prfd pldl3keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e005 prfd pldl3strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e005 prfd pldl3strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e006 prfd #6, p0, \[x0, z0\.d, lsl #3\] +.*: c460e006 prfd #6, p0, \[x0, z0\.d, lsl #3\] +.*: c460e007 prfd #7, p0, \[x0, z0\.d, lsl #3\] +.*: c460e007 prfd #7, p0, \[x0, z0\.d, lsl #3\] +.*: c460e008 prfd pstl1keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e008 prfd pstl1keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e009 prfd pstl1strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e009 prfd pstl1strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00a prfd pstl2keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00a prfd pstl2keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00b prfd pstl2strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00b prfd pstl2strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00c prfd pstl3keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00c prfd pstl3keep, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00d prfd pstl3strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00d prfd pstl3strm, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00e prfd #14, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00e prfd #14, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00f prfd #15, p0, \[x0, z0\.d, lsl #3\] +.*: c460e00f prfd #15, p0, \[x0, z0\.d, lsl #3\] +.*: c460e800 prfd pldl1keep, p2, \[x0, z0\.d, lsl #3\] +.*: c460e800 prfd pldl1keep, p2, \[x0, z0\.d, lsl #3\] +.*: c460fc00 prfd pldl1keep, p7, \[x0, z0\.d, lsl #3\] +.*: c460fc00 prfd pldl1keep, p7, \[x0, z0\.d, lsl #3\] +.*: c460e060 prfd pldl1keep, p0, \[x3, z0\.d, lsl #3\] +.*: c460e060 prfd pldl1keep, p0, \[x3, z0\.d, lsl #3\] +.*: c460e3e0 prfd pldl1keep, p0, \[sp, z0\.d, lsl #3\] +.*: c460e3e0 prfd pldl1keep, p0, \[sp, z0\.d, lsl #3\] +.*: c464e000 prfd pldl1keep, p0, \[x0, z4\.d, lsl #3\] +.*: c464e000 prfd pldl1keep, p0, \[x0, z4\.d, lsl #3\] +.*: c47fe000 prfd pldl1keep, p0, \[x0, z31\.d, lsl #3\] +.*: c47fe000 prfd pldl1keep, p0, \[x0, z31\.d, lsl #3\] .*: 8580e000 prfd pldl1keep, p0, \[z0\.s\] .*: 8580e000 prfd pldl1keep, p0, \[z0\.s\] .*: 8580e000 prfd pldl1keep, p0, \[z0\.s\] @@ -22930,14 +22930,14 @@ Disassembly of section .*: .*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\] .*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\] .*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\] -.*: 858fe000 prfd pldl1keep, p0, \[z0\.s,#120\] -.*: 858fe000 prfd pldl1keep, p0, \[z0\.s,#120\] -.*: 8590e000 prfd pldl1keep, p0, \[z0\.s,#128\] -.*: 8590e000 prfd pldl1keep, p0, \[z0\.s,#128\] -.*: 8591e000 prfd pldl1keep, p0, \[z0\.s,#136\] -.*: 8591e000 prfd pldl1keep, p0, \[z0\.s,#136\] -.*: 859fe000 prfd pldl1keep, p0, \[z0\.s,#248\] -.*: 859fe000 prfd pldl1keep, p0, \[z0\.s,#248\] +.*: 858fe000 prfd pldl1keep, p0, \[z0\.s, #120\] +.*: 858fe000 prfd pldl1keep, p0, \[z0\.s, #120\] +.*: 8590e000 prfd pldl1keep, p0, \[z0\.s, #128\] +.*: 8590e000 prfd pldl1keep, p0, \[z0\.s, #128\] +.*: 8591e000 prfd pldl1keep, p0, \[z0\.s, #136\] +.*: 8591e000 prfd pldl1keep, p0, \[z0\.s, #136\] +.*: 859fe000 prfd pldl1keep, p0, \[z0\.s, #248\] +.*: 859fe000 prfd pldl1keep, p0, \[z0\.s, #248\] .*: 85c06000 prfd pldl1keep, p0, \[x0\] .*: 85c06000 prfd pldl1keep, p0, \[x0\] .*: 85c06000 prfd pldl1keep, p0, \[x0\] @@ -23018,14 +23018,14 @@ Disassembly of section .*: .*: 85c063e0 prfd pldl1keep, p0, \[sp\] .*: 85c063e0 prfd pldl1keep, p0, \[sp\] .*: 85c063e0 prfd pldl1keep, p0, \[sp\] -.*: 85df6000 prfd pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85df6000 prfd pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85e06000 prfd pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e06000 prfd pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e16000 prfd pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85e16000 prfd pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85ff6000 prfd pldl1keep, p0, \[x0,#-1,mul vl\] -.*: 85ff6000 prfd pldl1keep, p0, \[x0,#-1,mul vl\] +.*: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\] +.*: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\] .*: c580e000 prfd pldl1keep, p0, \[z0\.d\] .*: c580e000 prfd pldl1keep, p0, \[z0\.d\] .*: c580e000 prfd pldl1keep, p0, \[z0\.d\] @@ -23086,278 +23086,278 @@ Disassembly of section .*: .*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\] .*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\] .*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\] -.*: c58fe000 prfd pldl1keep, p0, \[z0\.d,#120\] -.*: c58fe000 prfd pldl1keep, p0, \[z0\.d,#120\] -.*: c590e000 prfd pldl1keep, p0, \[z0\.d,#128\] -.*: c590e000 prfd pldl1keep, p0, \[z0\.d,#128\] -.*: c591e000 prfd pldl1keep, p0, \[z0\.d,#136\] -.*: c591e000 prfd pldl1keep, p0, \[z0\.d,#136\] -.*: c59fe000 prfd pldl1keep, p0, \[z0\.d,#248\] -.*: c59fe000 prfd pldl1keep, p0, \[z0\.d,#248\] -.*: 84202000 prfh pldl1keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202000 prfh pldl1keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202001 prfh pldl1strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202001 prfh pldl1strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202002 prfh pldl2keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202002 prfh pldl2keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202003 prfh pldl2strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202003 prfh pldl2strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202004 prfh pldl3keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202004 prfh pldl3keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202005 prfh pldl3strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202005 prfh pldl3strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202006 prfh #6, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202006 prfh #6, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202007 prfh #7, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202007 prfh #7, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202008 prfh pstl1keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202008 prfh pstl1keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202009 prfh pstl1strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202009 prfh pstl1strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200a prfh pstl2keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200a prfh pstl2keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200b prfh pstl2strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200b prfh pstl2strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200c prfh pstl3keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200c prfh pstl3keep, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200d prfh pstl3strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200d prfh pstl3strm, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200e prfh #14, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200e prfh #14, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200f prfh #15, p0, \[x0,z0\.s,uxtw #1\] -.*: 8420200f prfh #15, p0, \[x0,z0\.s,uxtw #1\] -.*: 84202800 prfh pldl1keep, p2, \[x0,z0\.s,uxtw #1\] -.*: 84202800 prfh pldl1keep, p2, \[x0,z0\.s,uxtw #1\] -.*: 84203c00 prfh pldl1keep, p7, \[x0,z0\.s,uxtw #1\] -.*: 84203c00 prfh pldl1keep, p7, \[x0,z0\.s,uxtw #1\] -.*: 84202060 prfh pldl1keep, p0, \[x3,z0\.s,uxtw #1\] -.*: 84202060 prfh pldl1keep, p0, \[x3,z0\.s,uxtw #1\] -.*: 842023e0 prfh pldl1keep, p0, \[sp,z0\.s,uxtw #1\] -.*: 842023e0 prfh pldl1keep, p0, \[sp,z0\.s,uxtw #1\] -.*: 84242000 prfh pldl1keep, p0, \[x0,z4\.s,uxtw #1\] -.*: 84242000 prfh pldl1keep, p0, \[x0,z4\.s,uxtw #1\] -.*: 843f2000 prfh pldl1keep, p0, \[x0,z31\.s,uxtw #1\] -.*: 843f2000 prfh pldl1keep, p0, \[x0,z31\.s,uxtw #1\] -.*: 84602000 prfh pldl1keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602000 prfh pldl1keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602001 prfh pldl1strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602001 prfh pldl1strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602002 prfh pldl2keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602002 prfh pldl2keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602003 prfh pldl2strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602003 prfh pldl2strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602004 prfh pldl3keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602004 prfh pldl3keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602005 prfh pldl3strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602005 prfh pldl3strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602006 prfh #6, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602006 prfh #6, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602007 prfh #7, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602007 prfh #7, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602008 prfh pstl1keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602008 prfh pstl1keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602009 prfh pstl1strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602009 prfh pstl1strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200a prfh pstl2keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200a prfh pstl2keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200b prfh pstl2strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200b prfh pstl2strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200c prfh pstl3keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200c prfh pstl3keep, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200d prfh pstl3strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200d prfh pstl3strm, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200e prfh #14, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200e prfh #14, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200f prfh #15, p0, \[x0,z0\.s,sxtw #1\] -.*: 8460200f prfh #15, p0, \[x0,z0\.s,sxtw #1\] -.*: 84602800 prfh pldl1keep, p2, \[x0,z0\.s,sxtw #1\] -.*: 84602800 prfh pldl1keep, p2, \[x0,z0\.s,sxtw #1\] -.*: 84603c00 prfh pldl1keep, p7, \[x0,z0\.s,sxtw #1\] -.*: 84603c00 prfh pldl1keep, p7, \[x0,z0\.s,sxtw #1\] -.*: 84602060 prfh pldl1keep, p0, \[x3,z0\.s,sxtw #1\] -.*: 84602060 prfh pldl1keep, p0, \[x3,z0\.s,sxtw #1\] -.*: 846023e0 prfh pldl1keep, p0, \[sp,z0\.s,sxtw #1\] -.*: 846023e0 prfh pldl1keep, p0, \[sp,z0\.s,sxtw #1\] -.*: 84642000 prfh pldl1keep, p0, \[x0,z4\.s,sxtw #1\] -.*: 84642000 prfh pldl1keep, p0, \[x0,z4\.s,sxtw #1\] -.*: 847f2000 prfh pldl1keep, p0, \[x0,z31\.s,sxtw #1\] -.*: 847f2000 prfh pldl1keep, p0, \[x0,z31\.s,sxtw #1\] -.*: 8480c000 prfh pldl1keep, p0, \[x0,x0,lsl #1\] -.*: 8480c000 prfh pldl1keep, p0, \[x0,x0,lsl #1\] -.*: 8480c001 prfh pldl1strm, p0, \[x0,x0,lsl #1\] -.*: 8480c001 prfh pldl1strm, p0, \[x0,x0,lsl #1\] -.*: 8480c002 prfh pldl2keep, p0, \[x0,x0,lsl #1\] -.*: 8480c002 prfh pldl2keep, p0, \[x0,x0,lsl #1\] -.*: 8480c003 prfh pldl2strm, p0, \[x0,x0,lsl #1\] -.*: 8480c003 prfh pldl2strm, p0, \[x0,x0,lsl #1\] -.*: 8480c004 prfh pldl3keep, p0, \[x0,x0,lsl #1\] -.*: 8480c004 prfh pldl3keep, p0, \[x0,x0,lsl #1\] -.*: 8480c005 prfh pldl3strm, p0, \[x0,x0,lsl #1\] -.*: 8480c005 prfh pldl3strm, p0, \[x0,x0,lsl #1\] -.*: 8480c006 prfh #6, p0, \[x0,x0,lsl #1\] -.*: 8480c006 prfh #6, p0, \[x0,x0,lsl #1\] -.*: 8480c007 prfh #7, p0, \[x0,x0,lsl #1\] -.*: 8480c007 prfh #7, p0, \[x0,x0,lsl #1\] -.*: 8480c008 prfh pstl1keep, p0, \[x0,x0,lsl #1\] -.*: 8480c008 prfh pstl1keep, p0, \[x0,x0,lsl #1\] -.*: 8480c009 prfh pstl1strm, p0, \[x0,x0,lsl #1\] -.*: 8480c009 prfh pstl1strm, p0, \[x0,x0,lsl #1\] -.*: 8480c00a prfh pstl2keep, p0, \[x0,x0,lsl #1\] -.*: 8480c00a prfh pstl2keep, p0, \[x0,x0,lsl #1\] -.*: 8480c00b prfh pstl2strm, p0, \[x0,x0,lsl #1\] -.*: 8480c00b prfh pstl2strm, p0, \[x0,x0,lsl #1\] -.*: 8480c00c prfh pstl3keep, p0, \[x0,x0,lsl #1\] -.*: 8480c00c prfh pstl3keep, p0, \[x0,x0,lsl #1\] -.*: 8480c00d prfh pstl3strm, p0, \[x0,x0,lsl #1\] -.*: 8480c00d prfh pstl3strm, p0, \[x0,x0,lsl #1\] -.*: 8480c00e prfh #14, p0, \[x0,x0,lsl #1\] -.*: 8480c00e prfh #14, p0, \[x0,x0,lsl #1\] -.*: 8480c00f prfh #15, p0, \[x0,x0,lsl #1\] -.*: 8480c00f prfh #15, p0, \[x0,x0,lsl #1\] -.*: 8480c800 prfh pldl1keep, p2, \[x0,x0,lsl #1\] -.*: 8480c800 prfh pldl1keep, p2, \[x0,x0,lsl #1\] -.*: 8480dc00 prfh pldl1keep, p7, \[x0,x0,lsl #1\] -.*: 8480dc00 prfh pldl1keep, p7, \[x0,x0,lsl #1\] -.*: 8480c060 prfh pldl1keep, p0, \[x3,x0,lsl #1\] -.*: 8480c060 prfh pldl1keep, p0, \[x3,x0,lsl #1\] -.*: 8480c3e0 prfh pldl1keep, p0, \[sp,x0,lsl #1\] -.*: 8480c3e0 prfh pldl1keep, p0, \[sp,x0,lsl #1\] -.*: 8484c000 prfh pldl1keep, p0, \[x0,x4,lsl #1\] -.*: 8484c000 prfh pldl1keep, p0, \[x0,x4,lsl #1\] -.*: 849ec000 prfh pldl1keep, p0, \[x0,x30,lsl #1\] -.*: 849ec000 prfh pldl1keep, p0, \[x0,x30,lsl #1\] -.*: c4202000 prfh pldl1keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202000 prfh pldl1keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202001 prfh pldl1strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202001 prfh pldl1strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202002 prfh pldl2keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202002 prfh pldl2keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202003 prfh pldl2strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202003 prfh pldl2strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202004 prfh pldl3keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202004 prfh pldl3keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202005 prfh pldl3strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202005 prfh pldl3strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202006 prfh #6, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202006 prfh #6, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202007 prfh #7, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202007 prfh #7, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202008 prfh pstl1keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202008 prfh pstl1keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202009 prfh pstl1strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202009 prfh pstl1strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200a prfh pstl2keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200a prfh pstl2keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200b prfh pstl2strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200b prfh pstl2strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200c prfh pstl3keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200c prfh pstl3keep, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200d prfh pstl3strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200d prfh pstl3strm, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200e prfh #14, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200e prfh #14, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200f prfh #15, p0, \[x0,z0\.d,uxtw #1\] -.*: c420200f prfh #15, p0, \[x0,z0\.d,uxtw #1\] -.*: c4202800 prfh pldl1keep, p2, \[x0,z0\.d,uxtw #1\] -.*: c4202800 prfh pldl1keep, p2, \[x0,z0\.d,uxtw #1\] -.*: c4203c00 prfh pldl1keep, p7, \[x0,z0\.d,uxtw #1\] -.*: c4203c00 prfh pldl1keep, p7, \[x0,z0\.d,uxtw #1\] -.*: c4202060 prfh pldl1keep, p0, \[x3,z0\.d,uxtw #1\] -.*: c4202060 prfh pldl1keep, p0, \[x3,z0\.d,uxtw #1\] -.*: c42023e0 prfh pldl1keep, p0, \[sp,z0\.d,uxtw #1\] -.*: c42023e0 prfh pldl1keep, p0, \[sp,z0\.d,uxtw #1\] -.*: c4242000 prfh pldl1keep, p0, \[x0,z4\.d,uxtw #1\] -.*: c4242000 prfh pldl1keep, p0, \[x0,z4\.d,uxtw #1\] -.*: c43f2000 prfh pldl1keep, p0, \[x0,z31\.d,uxtw #1\] -.*: c43f2000 prfh pldl1keep, p0, \[x0,z31\.d,uxtw #1\] -.*: c4602000 prfh pldl1keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602000 prfh pldl1keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602001 prfh pldl1strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602001 prfh pldl1strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602002 prfh pldl2keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602002 prfh pldl2keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602003 prfh pldl2strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602003 prfh pldl2strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602004 prfh pldl3keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602004 prfh pldl3keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602005 prfh pldl3strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602005 prfh pldl3strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602006 prfh #6, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602006 prfh #6, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602007 prfh #7, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602007 prfh #7, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602008 prfh pstl1keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602008 prfh pstl1keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602009 prfh pstl1strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602009 prfh pstl1strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200a prfh pstl2keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200a prfh pstl2keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200b prfh pstl2strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200b prfh pstl2strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200c prfh pstl3keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200c prfh pstl3keep, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200d prfh pstl3strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200d prfh pstl3strm, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200e prfh #14, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200e prfh #14, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200f prfh #15, p0, \[x0,z0\.d,sxtw #1\] -.*: c460200f prfh #15, p0, \[x0,z0\.d,sxtw #1\] -.*: c4602800 prfh pldl1keep, p2, \[x0,z0\.d,sxtw #1\] -.*: c4602800 prfh pldl1keep, p2, \[x0,z0\.d,sxtw #1\] -.*: c4603c00 prfh pldl1keep, p7, \[x0,z0\.d,sxtw #1\] -.*: c4603c00 prfh pldl1keep, p7, \[x0,z0\.d,sxtw #1\] -.*: c4602060 prfh pldl1keep, p0, \[x3,z0\.d,sxtw #1\] -.*: c4602060 prfh pldl1keep, p0, \[x3,z0\.d,sxtw #1\] -.*: c46023e0 prfh pldl1keep, p0, \[sp,z0\.d,sxtw #1\] -.*: c46023e0 prfh pldl1keep, p0, \[sp,z0\.d,sxtw #1\] -.*: c4642000 prfh pldl1keep, p0, \[x0,z4\.d,sxtw #1\] -.*: c4642000 prfh pldl1keep, p0, \[x0,z4\.d,sxtw #1\] -.*: c47f2000 prfh pldl1keep, p0, \[x0,z31\.d,sxtw #1\] -.*: c47f2000 prfh pldl1keep, p0, \[x0,z31\.d,sxtw #1\] -.*: c460a000 prfh pldl1keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a000 prfh pldl1keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a001 prfh pldl1strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a001 prfh pldl1strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a002 prfh pldl2keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a002 prfh pldl2keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a003 prfh pldl2strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a003 prfh pldl2strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a004 prfh pldl3keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a004 prfh pldl3keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a005 prfh pldl3strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a005 prfh pldl3strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a006 prfh #6, p0, \[x0,z0\.d,lsl #1\] -.*: c460a006 prfh #6, p0, \[x0,z0\.d,lsl #1\] -.*: c460a007 prfh #7, p0, \[x0,z0\.d,lsl #1\] -.*: c460a007 prfh #7, p0, \[x0,z0\.d,lsl #1\] -.*: c460a008 prfh pstl1keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a008 prfh pstl1keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a009 prfh pstl1strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a009 prfh pstl1strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00a prfh pstl2keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00a prfh pstl2keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00b prfh pstl2strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00b prfh pstl2strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00c prfh pstl3keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00c prfh pstl3keep, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00d prfh pstl3strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00d prfh pstl3strm, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00e prfh #14, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00e prfh #14, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00f prfh #15, p0, \[x0,z0\.d,lsl #1\] -.*: c460a00f prfh #15, p0, \[x0,z0\.d,lsl #1\] -.*: c460a800 prfh pldl1keep, p2, \[x0,z0\.d,lsl #1\] -.*: c460a800 prfh pldl1keep, p2, \[x0,z0\.d,lsl #1\] -.*: c460bc00 prfh pldl1keep, p7, \[x0,z0\.d,lsl #1\] -.*: c460bc00 prfh pldl1keep, p7, \[x0,z0\.d,lsl #1\] -.*: c460a060 prfh pldl1keep, p0, \[x3,z0\.d,lsl #1\] -.*: c460a060 prfh pldl1keep, p0, \[x3,z0\.d,lsl #1\] -.*: c460a3e0 prfh pldl1keep, p0, \[sp,z0\.d,lsl #1\] -.*: c460a3e0 prfh pldl1keep, p0, \[sp,z0\.d,lsl #1\] -.*: c464a000 prfh pldl1keep, p0, \[x0,z4\.d,lsl #1\] -.*: c464a000 prfh pldl1keep, p0, \[x0,z4\.d,lsl #1\] -.*: c47fa000 prfh pldl1keep, p0, \[x0,z31\.d,lsl #1\] -.*: c47fa000 prfh pldl1keep, p0, \[x0,z31\.d,lsl #1\] +.*: c58fe000 prfd pldl1keep, p0, \[z0\.d, #120\] +.*: c58fe000 prfd pldl1keep, p0, \[z0\.d, #120\] +.*: c590e000 prfd pldl1keep, p0, \[z0\.d, #128\] +.*: c590e000 prfd pldl1keep, p0, \[z0\.d, #128\] +.*: c591e000 prfd pldl1keep, p0, \[z0\.d, #136\] +.*: c591e000 prfd pldl1keep, p0, \[z0\.d, #136\] +.*: c59fe000 prfd pldl1keep, p0, \[z0\.d, #248\] +.*: c59fe000 prfd pldl1keep, p0, \[z0\.d, #248\] +.*: 84202000 prfh pldl1keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202000 prfh pldl1keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202001 prfh pldl1strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202001 prfh pldl1strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202002 prfh pldl2keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202002 prfh pldl2keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202003 prfh pldl2strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202003 prfh pldl2strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202004 prfh pldl3keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202004 prfh pldl3keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202005 prfh pldl3strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202005 prfh pldl3strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202006 prfh #6, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202006 prfh #6, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202007 prfh #7, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202007 prfh #7, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202008 prfh pstl1keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202008 prfh pstl1keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202009 prfh pstl1strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202009 prfh pstl1strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200a prfh pstl2keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200a prfh pstl2keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200b prfh pstl2strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200b prfh pstl2strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200c prfh pstl3keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200c prfh pstl3keep, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200d prfh pstl3strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200d prfh pstl3strm, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200e prfh #14, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200e prfh #14, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200f prfh #15, p0, \[x0, z0\.s, uxtw #1\] +.*: 8420200f prfh #15, p0, \[x0, z0\.s, uxtw #1\] +.*: 84202800 prfh pldl1keep, p2, \[x0, z0\.s, uxtw #1\] +.*: 84202800 prfh pldl1keep, p2, \[x0, z0\.s, uxtw #1\] +.*: 84203c00 prfh pldl1keep, p7, \[x0, z0\.s, uxtw #1\] +.*: 84203c00 prfh pldl1keep, p7, \[x0, z0\.s, uxtw #1\] +.*: 84202060 prfh pldl1keep, p0, \[x3, z0\.s, uxtw #1\] +.*: 84202060 prfh pldl1keep, p0, \[x3, z0\.s, uxtw #1\] +.*: 842023e0 prfh pldl1keep, p0, \[sp, z0\.s, uxtw #1\] +.*: 842023e0 prfh pldl1keep, p0, \[sp, z0\.s, uxtw #1\] +.*: 84242000 prfh pldl1keep, p0, \[x0, z4\.s, uxtw #1\] +.*: 84242000 prfh pldl1keep, p0, \[x0, z4\.s, uxtw #1\] +.*: 843f2000 prfh pldl1keep, p0, \[x0, z31\.s, uxtw #1\] +.*: 843f2000 prfh pldl1keep, p0, \[x0, z31\.s, uxtw #1\] +.*: 84602000 prfh pldl1keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602000 prfh pldl1keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602001 prfh pldl1strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602001 prfh pldl1strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602002 prfh pldl2keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602002 prfh pldl2keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602003 prfh pldl2strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602003 prfh pldl2strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602004 prfh pldl3keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602004 prfh pldl3keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602005 prfh pldl3strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602005 prfh pldl3strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602006 prfh #6, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602006 prfh #6, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602007 prfh #7, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602007 prfh #7, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602008 prfh pstl1keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602008 prfh pstl1keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602009 prfh pstl1strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602009 prfh pstl1strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200a prfh pstl2keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200a prfh pstl2keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200b prfh pstl2strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200b prfh pstl2strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200c prfh pstl3keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200c prfh pstl3keep, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200d prfh pstl3strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200d prfh pstl3strm, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200e prfh #14, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200e prfh #14, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200f prfh #15, p0, \[x0, z0\.s, sxtw #1\] +.*: 8460200f prfh #15, p0, \[x0, z0\.s, sxtw #1\] +.*: 84602800 prfh pldl1keep, p2, \[x0, z0\.s, sxtw #1\] +.*: 84602800 prfh pldl1keep, p2, \[x0, z0\.s, sxtw #1\] +.*: 84603c00 prfh pldl1keep, p7, \[x0, z0\.s, sxtw #1\] +.*: 84603c00 prfh pldl1keep, p7, \[x0, z0\.s, sxtw #1\] +.*: 84602060 prfh pldl1keep, p0, \[x3, z0\.s, sxtw #1\] +.*: 84602060 prfh pldl1keep, p0, \[x3, z0\.s, sxtw #1\] +.*: 846023e0 prfh pldl1keep, p0, \[sp, z0\.s, sxtw #1\] +.*: 846023e0 prfh pldl1keep, p0, \[sp, z0\.s, sxtw #1\] +.*: 84642000 prfh pldl1keep, p0, \[x0, z4\.s, sxtw #1\] +.*: 84642000 prfh pldl1keep, p0, \[x0, z4\.s, sxtw #1\] +.*: 847f2000 prfh pldl1keep, p0, \[x0, z31\.s, sxtw #1\] +.*: 847f2000 prfh pldl1keep, p0, \[x0, z31\.s, sxtw #1\] +.*: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\] +.*: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\] +.*: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\] +.*: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\] +.*: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\] +.*: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\] +.*: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\] +.*: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\] +.*: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\] +.*: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\] +.*: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\] +.*: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\] +.*: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\] +.*: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\] +.*: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\] +.*: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\] +.*: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\] +.*: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\] +.*: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\] +.*: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\] +.*: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\] +.*: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\] +.*: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\] +.*: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\] +.*: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\] +.*: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\] +.*: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\] +.*: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\] +.*: 8480c00e prfh #14, p0, \[x0, x0, lsl #1\] +.*: 8480c00e prfh #14, p0, \[x0, x0, lsl #1\] +.*: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\] +.*: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\] +.*: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\] +.*: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\] +.*: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\] +.*: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\] +.*: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\] +.*: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\] +.*: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\] +.*: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\] +.*: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\] +.*: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\] +.*: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\] +.*: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\] +.*: c4202000 prfh pldl1keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202000 prfh pldl1keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202001 prfh pldl1strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202001 prfh pldl1strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202002 prfh pldl2keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202002 prfh pldl2keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202003 prfh pldl2strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202003 prfh pldl2strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202004 prfh pldl3keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202004 prfh pldl3keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202005 prfh pldl3strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202005 prfh pldl3strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202006 prfh #6, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202006 prfh #6, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202007 prfh #7, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202007 prfh #7, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202008 prfh pstl1keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202008 prfh pstl1keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202009 prfh pstl1strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202009 prfh pstl1strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200a prfh pstl2keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200a prfh pstl2keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200b prfh pstl2strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200b prfh pstl2strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200c prfh pstl3keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200c prfh pstl3keep, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200d prfh pstl3strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200d prfh pstl3strm, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200e prfh #14, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200e prfh #14, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200f prfh #15, p0, \[x0, z0\.d, uxtw #1\] +.*: c420200f prfh #15, p0, \[x0, z0\.d, uxtw #1\] +.*: c4202800 prfh pldl1keep, p2, \[x0, z0\.d, uxtw #1\] +.*: c4202800 prfh pldl1keep, p2, \[x0, z0\.d, uxtw #1\] +.*: c4203c00 prfh pldl1keep, p7, \[x0, z0\.d, uxtw #1\] +.*: c4203c00 prfh pldl1keep, p7, \[x0, z0\.d, uxtw #1\] +.*: c4202060 prfh pldl1keep, p0, \[x3, z0\.d, uxtw #1\] +.*: c4202060 prfh pldl1keep, p0, \[x3, z0\.d, uxtw #1\] +.*: c42023e0 prfh pldl1keep, p0, \[sp, z0\.d, uxtw #1\] +.*: c42023e0 prfh pldl1keep, p0, \[sp, z0\.d, uxtw #1\] +.*: c4242000 prfh pldl1keep, p0, \[x0, z4\.d, uxtw #1\] +.*: c4242000 prfh pldl1keep, p0, \[x0, z4\.d, uxtw #1\] +.*: c43f2000 prfh pldl1keep, p0, \[x0, z31\.d, uxtw #1\] +.*: c43f2000 prfh pldl1keep, p0, \[x0, z31\.d, uxtw #1\] +.*: c4602000 prfh pldl1keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602000 prfh pldl1keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602001 prfh pldl1strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602001 prfh pldl1strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602002 prfh pldl2keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602002 prfh pldl2keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602003 prfh pldl2strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602003 prfh pldl2strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602004 prfh pldl3keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602004 prfh pldl3keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602005 prfh pldl3strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602005 prfh pldl3strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602006 prfh #6, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602006 prfh #6, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602007 prfh #7, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602007 prfh #7, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602008 prfh pstl1keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602008 prfh pstl1keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602009 prfh pstl1strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602009 prfh pstl1strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200a prfh pstl2keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200a prfh pstl2keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200b prfh pstl2strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200b prfh pstl2strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200c prfh pstl3keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200c prfh pstl3keep, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200d prfh pstl3strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200d prfh pstl3strm, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200e prfh #14, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200e prfh #14, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200f prfh #15, p0, \[x0, z0\.d, sxtw #1\] +.*: c460200f prfh #15, p0, \[x0, z0\.d, sxtw #1\] +.*: c4602800 prfh pldl1keep, p2, \[x0, z0\.d, sxtw #1\] +.*: c4602800 prfh pldl1keep, p2, \[x0, z0\.d, sxtw #1\] +.*: c4603c00 prfh pldl1keep, p7, \[x0, z0\.d, sxtw #1\] +.*: c4603c00 prfh pldl1keep, p7, \[x0, z0\.d, sxtw #1\] +.*: c4602060 prfh pldl1keep, p0, \[x3, z0\.d, sxtw #1\] +.*: c4602060 prfh pldl1keep, p0, \[x3, z0\.d, sxtw #1\] +.*: c46023e0 prfh pldl1keep, p0, \[sp, z0\.d, sxtw #1\] +.*: c46023e0 prfh pldl1keep, p0, \[sp, z0\.d, sxtw #1\] +.*: c4642000 prfh pldl1keep, p0, \[x0, z4\.d, sxtw #1\] +.*: c4642000 prfh pldl1keep, p0, \[x0, z4\.d, sxtw #1\] +.*: c47f2000 prfh pldl1keep, p0, \[x0, z31\.d, sxtw #1\] +.*: c47f2000 prfh pldl1keep, p0, \[x0, z31\.d, sxtw #1\] +.*: c460a000 prfh pldl1keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a000 prfh pldl1keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a001 prfh pldl1strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a001 prfh pldl1strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a002 prfh pldl2keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a002 prfh pldl2keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a003 prfh pldl2strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a003 prfh pldl2strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a004 prfh pldl3keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a004 prfh pldl3keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a005 prfh pldl3strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a005 prfh pldl3strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a006 prfh #6, p0, \[x0, z0\.d, lsl #1\] +.*: c460a006 prfh #6, p0, \[x0, z0\.d, lsl #1\] +.*: c460a007 prfh #7, p0, \[x0, z0\.d, lsl #1\] +.*: c460a007 prfh #7, p0, \[x0, z0\.d, lsl #1\] +.*: c460a008 prfh pstl1keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a008 prfh pstl1keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a009 prfh pstl1strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a009 prfh pstl1strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00a prfh pstl2keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00a prfh pstl2keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00b prfh pstl2strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00b prfh pstl2strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00c prfh pstl3keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00c prfh pstl3keep, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00d prfh pstl3strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00d prfh pstl3strm, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00e prfh #14, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00e prfh #14, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00f prfh #15, p0, \[x0, z0\.d, lsl #1\] +.*: c460a00f prfh #15, p0, \[x0, z0\.d, lsl #1\] +.*: c460a800 prfh pldl1keep, p2, \[x0, z0\.d, lsl #1\] +.*: c460a800 prfh pldl1keep, p2, \[x0, z0\.d, lsl #1\] +.*: c460bc00 prfh pldl1keep, p7, \[x0, z0\.d, lsl #1\] +.*: c460bc00 prfh pldl1keep, p7, \[x0, z0\.d, lsl #1\] +.*: c460a060 prfh pldl1keep, p0, \[x3, z0\.d, lsl #1\] +.*: c460a060 prfh pldl1keep, p0, \[x3, z0\.d, lsl #1\] +.*: c460a3e0 prfh pldl1keep, p0, \[sp, z0\.d, lsl #1\] +.*: c460a3e0 prfh pldl1keep, p0, \[sp, z0\.d, lsl #1\] +.*: c464a000 prfh pldl1keep, p0, \[x0, z4\.d, lsl #1\] +.*: c464a000 prfh pldl1keep, p0, \[x0, z4\.d, lsl #1\] +.*: c47fa000 prfh pldl1keep, p0, \[x0, z31\.d, lsl #1\] +.*: c47fa000 prfh pldl1keep, p0, \[x0, z31\.d, lsl #1\] .*: 8480e000 prfh pldl1keep, p0, \[z0\.s\] .*: 8480e000 prfh pldl1keep, p0, \[z0\.s\] .*: 8480e000 prfh pldl1keep, p0, \[z0\.s\] @@ -23418,14 +23418,14 @@ Disassembly of section .*: .*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\] .*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\] .*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\] -.*: 848fe000 prfh pldl1keep, p0, \[z0\.s,#30\] -.*: 848fe000 prfh pldl1keep, p0, \[z0\.s,#30\] -.*: 8490e000 prfh pldl1keep, p0, \[z0\.s,#32\] -.*: 8490e000 prfh pldl1keep, p0, \[z0\.s,#32\] -.*: 8491e000 prfh pldl1keep, p0, \[z0\.s,#34\] -.*: 8491e000 prfh pldl1keep, p0, \[z0\.s,#34\] -.*: 849fe000 prfh pldl1keep, p0, \[z0\.s,#62\] -.*: 849fe000 prfh pldl1keep, p0, \[z0\.s,#62\] +.*: 848fe000 prfh pldl1keep, p0, \[z0\.s, #30\] +.*: 848fe000 prfh pldl1keep, p0, \[z0\.s, #30\] +.*: 8490e000 prfh pldl1keep, p0, \[z0\.s, #32\] +.*: 8490e000 prfh pldl1keep, p0, \[z0\.s, #32\] +.*: 8491e000 prfh pldl1keep, p0, \[z0\.s, #34\] +.*: 8491e000 prfh pldl1keep, p0, \[z0\.s, #34\] +.*: 849fe000 prfh pldl1keep, p0, \[z0\.s, #62\] +.*: 849fe000 prfh pldl1keep, p0, \[z0\.s, #62\] .*: 85c02000 prfh pldl1keep, p0, \[x0\] .*: 85c02000 prfh pldl1keep, p0, \[x0\] .*: 85c02000 prfh pldl1keep, p0, \[x0\] @@ -23506,14 +23506,14 @@ Disassembly of section .*: .*: 85c023e0 prfh pldl1keep, p0, \[sp\] .*: 85c023e0 prfh pldl1keep, p0, \[sp\] .*: 85c023e0 prfh pldl1keep, p0, \[sp\] -.*: 85df2000 prfh pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85df2000 prfh pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85e02000 prfh pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e02000 prfh pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e12000 prfh pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85e12000 prfh pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85ff2000 prfh pldl1keep, p0, \[x0,#-1,mul vl\] -.*: 85ff2000 prfh pldl1keep, p0, \[x0,#-1,mul vl\] +.*: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\] +.*: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\] .*: c480e000 prfh pldl1keep, p0, \[z0\.d\] .*: c480e000 prfh pldl1keep, p0, \[z0\.d\] .*: c480e000 prfh pldl1keep, p0, \[z0\.d\] @@ -23574,278 +23574,278 @@ Disassembly of section .*: .*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\] .*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\] .*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\] -.*: c48fe000 prfh pldl1keep, p0, \[z0\.d,#30\] -.*: c48fe000 prfh pldl1keep, p0, \[z0\.d,#30\] -.*: c490e000 prfh pldl1keep, p0, \[z0\.d,#32\] -.*: c490e000 prfh pldl1keep, p0, \[z0\.d,#32\] -.*: c491e000 prfh pldl1keep, p0, \[z0\.d,#34\] -.*: c491e000 prfh pldl1keep, p0, \[z0\.d,#34\] -.*: c49fe000 prfh pldl1keep, p0, \[z0\.d,#62\] -.*: c49fe000 prfh pldl1keep, p0, \[z0\.d,#62\] -.*: 84204000 prfw pldl1keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204000 prfw pldl1keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204001 prfw pldl1strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204001 prfw pldl1strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204002 prfw pldl2keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204002 prfw pldl2keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204003 prfw pldl2strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204003 prfw pldl2strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204004 prfw pldl3keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204004 prfw pldl3keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204005 prfw pldl3strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204005 prfw pldl3strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204006 prfw #6, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204006 prfw #6, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204007 prfw #7, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204007 prfw #7, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204008 prfw pstl1keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204008 prfw pstl1keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204009 prfw pstl1strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204009 prfw pstl1strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400a prfw pstl2keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400a prfw pstl2keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400b prfw pstl2strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400b prfw pstl2strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400c prfw pstl3keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400c prfw pstl3keep, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400d prfw pstl3strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400d prfw pstl3strm, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400e prfw #14, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400e prfw #14, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400f prfw #15, p0, \[x0,z0\.s,uxtw #2\] -.*: 8420400f prfw #15, p0, \[x0,z0\.s,uxtw #2\] -.*: 84204800 prfw pldl1keep, p2, \[x0,z0\.s,uxtw #2\] -.*: 84204800 prfw pldl1keep, p2, \[x0,z0\.s,uxtw #2\] -.*: 84205c00 prfw pldl1keep, p7, \[x0,z0\.s,uxtw #2\] -.*: 84205c00 prfw pldl1keep, p7, \[x0,z0\.s,uxtw #2\] -.*: 84204060 prfw pldl1keep, p0, \[x3,z0\.s,uxtw #2\] -.*: 84204060 prfw pldl1keep, p0, \[x3,z0\.s,uxtw #2\] -.*: 842043e0 prfw pldl1keep, p0, \[sp,z0\.s,uxtw #2\] -.*: 842043e0 prfw pldl1keep, p0, \[sp,z0\.s,uxtw #2\] -.*: 84244000 prfw pldl1keep, p0, \[x0,z4\.s,uxtw #2\] -.*: 84244000 prfw pldl1keep, p0, \[x0,z4\.s,uxtw #2\] -.*: 843f4000 prfw pldl1keep, p0, \[x0,z31\.s,uxtw #2\] -.*: 843f4000 prfw pldl1keep, p0, \[x0,z31\.s,uxtw #2\] -.*: 84604000 prfw pldl1keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604000 prfw pldl1keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604001 prfw pldl1strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604001 prfw pldl1strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604002 prfw pldl2keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604002 prfw pldl2keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604003 prfw pldl2strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604003 prfw pldl2strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604004 prfw pldl3keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604004 prfw pldl3keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604005 prfw pldl3strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604005 prfw pldl3strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604006 prfw #6, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604006 prfw #6, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604007 prfw #7, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604007 prfw #7, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604008 prfw pstl1keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604008 prfw pstl1keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604009 prfw pstl1strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604009 prfw pstl1strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400a prfw pstl2keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400a prfw pstl2keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400b prfw pstl2strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400b prfw pstl2strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400c prfw pstl3keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400c prfw pstl3keep, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400d prfw pstl3strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400d prfw pstl3strm, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400e prfw #14, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400e prfw #14, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400f prfw #15, p0, \[x0,z0\.s,sxtw #2\] -.*: 8460400f prfw #15, p0, \[x0,z0\.s,sxtw #2\] -.*: 84604800 prfw pldl1keep, p2, \[x0,z0\.s,sxtw #2\] -.*: 84604800 prfw pldl1keep, p2, \[x0,z0\.s,sxtw #2\] -.*: 84605c00 prfw pldl1keep, p7, \[x0,z0\.s,sxtw #2\] -.*: 84605c00 prfw pldl1keep, p7, \[x0,z0\.s,sxtw #2\] -.*: 84604060 prfw pldl1keep, p0, \[x3,z0\.s,sxtw #2\] -.*: 84604060 prfw pldl1keep, p0, \[x3,z0\.s,sxtw #2\] -.*: 846043e0 prfw pldl1keep, p0, \[sp,z0\.s,sxtw #2\] -.*: 846043e0 prfw pldl1keep, p0, \[sp,z0\.s,sxtw #2\] -.*: 84644000 prfw pldl1keep, p0, \[x0,z4\.s,sxtw #2\] -.*: 84644000 prfw pldl1keep, p0, \[x0,z4\.s,sxtw #2\] -.*: 847f4000 prfw pldl1keep, p0, \[x0,z31\.s,sxtw #2\] -.*: 847f4000 prfw pldl1keep, p0, \[x0,z31\.s,sxtw #2\] -.*: 8500c000 prfw pldl1keep, p0, \[x0,x0,lsl #2\] -.*: 8500c000 prfw pldl1keep, p0, \[x0,x0,lsl #2\] -.*: 8500c001 prfw pldl1strm, p0, \[x0,x0,lsl #2\] -.*: 8500c001 prfw pldl1strm, p0, \[x0,x0,lsl #2\] -.*: 8500c002 prfw pldl2keep, p0, \[x0,x0,lsl #2\] -.*: 8500c002 prfw pldl2keep, p0, \[x0,x0,lsl #2\] -.*: 8500c003 prfw pldl2strm, p0, \[x0,x0,lsl #2\] -.*: 8500c003 prfw pldl2strm, p0, \[x0,x0,lsl #2\] -.*: 8500c004 prfw pldl3keep, p0, \[x0,x0,lsl #2\] -.*: 8500c004 prfw pldl3keep, p0, \[x0,x0,lsl #2\] -.*: 8500c005 prfw pldl3strm, p0, \[x0,x0,lsl #2\] -.*: 8500c005 prfw pldl3strm, p0, \[x0,x0,lsl #2\] -.*: 8500c006 prfw #6, p0, \[x0,x0,lsl #2\] -.*: 8500c006 prfw #6, p0, \[x0,x0,lsl #2\] -.*: 8500c007 prfw #7, p0, \[x0,x0,lsl #2\] -.*: 8500c007 prfw #7, p0, \[x0,x0,lsl #2\] -.*: 8500c008 prfw pstl1keep, p0, \[x0,x0,lsl #2\] -.*: 8500c008 prfw pstl1keep, p0, \[x0,x0,lsl #2\] -.*: 8500c009 prfw pstl1strm, p0, \[x0,x0,lsl #2\] -.*: 8500c009 prfw pstl1strm, p0, \[x0,x0,lsl #2\] -.*: 8500c00a prfw pstl2keep, p0, \[x0,x0,lsl #2\] -.*: 8500c00a prfw pstl2keep, p0, \[x0,x0,lsl #2\] -.*: 8500c00b prfw pstl2strm, p0, \[x0,x0,lsl #2\] -.*: 8500c00b prfw pstl2strm, p0, \[x0,x0,lsl #2\] -.*: 8500c00c prfw pstl3keep, p0, \[x0,x0,lsl #2\] -.*: 8500c00c prfw pstl3keep, p0, \[x0,x0,lsl #2\] -.*: 8500c00d prfw pstl3strm, p0, \[x0,x0,lsl #2\] -.*: 8500c00d prfw pstl3strm, p0, \[x0,x0,lsl #2\] -.*: 8500c00e prfw #14, p0, \[x0,x0,lsl #2\] -.*: 8500c00e prfw #14, p0, \[x0,x0,lsl #2\] -.*: 8500c00f prfw #15, p0, \[x0,x0,lsl #2\] -.*: 8500c00f prfw #15, p0, \[x0,x0,lsl #2\] -.*: 8500c800 prfw pldl1keep, p2, \[x0,x0,lsl #2\] -.*: 8500c800 prfw pldl1keep, p2, \[x0,x0,lsl #2\] -.*: 8500dc00 prfw pldl1keep, p7, \[x0,x0,lsl #2\] -.*: 8500dc00 prfw pldl1keep, p7, \[x0,x0,lsl #2\] -.*: 8500c060 prfw pldl1keep, p0, \[x3,x0,lsl #2\] -.*: 8500c060 prfw pldl1keep, p0, \[x3,x0,lsl #2\] -.*: 8500c3e0 prfw pldl1keep, p0, \[sp,x0,lsl #2\] -.*: 8500c3e0 prfw pldl1keep, p0, \[sp,x0,lsl #2\] -.*: 8504c000 prfw pldl1keep, p0, \[x0,x4,lsl #2\] -.*: 8504c000 prfw pldl1keep, p0, \[x0,x4,lsl #2\] -.*: 851ec000 prfw pldl1keep, p0, \[x0,x30,lsl #2\] -.*: 851ec000 prfw pldl1keep, p0, \[x0,x30,lsl #2\] -.*: c4204000 prfw pldl1keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204000 prfw pldl1keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204001 prfw pldl1strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204001 prfw pldl1strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204002 prfw pldl2keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204002 prfw pldl2keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204003 prfw pldl2strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204003 prfw pldl2strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204004 prfw pldl3keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204004 prfw pldl3keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204005 prfw pldl3strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204005 prfw pldl3strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204006 prfw #6, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204006 prfw #6, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204007 prfw #7, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204007 prfw #7, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204008 prfw pstl1keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204008 prfw pstl1keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204009 prfw pstl1strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204009 prfw pstl1strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400a prfw pstl2keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400a prfw pstl2keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400b prfw pstl2strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400b prfw pstl2strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400c prfw pstl3keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400c prfw pstl3keep, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400d prfw pstl3strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400d prfw pstl3strm, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400e prfw #14, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400e prfw #14, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400f prfw #15, p0, \[x0,z0\.d,uxtw #2\] -.*: c420400f prfw #15, p0, \[x0,z0\.d,uxtw #2\] -.*: c4204800 prfw pldl1keep, p2, \[x0,z0\.d,uxtw #2\] -.*: c4204800 prfw pldl1keep, p2, \[x0,z0\.d,uxtw #2\] -.*: c4205c00 prfw pldl1keep, p7, \[x0,z0\.d,uxtw #2\] -.*: c4205c00 prfw pldl1keep, p7, \[x0,z0\.d,uxtw #2\] -.*: c4204060 prfw pldl1keep, p0, \[x3,z0\.d,uxtw #2\] -.*: c4204060 prfw pldl1keep, p0, \[x3,z0\.d,uxtw #2\] -.*: c42043e0 prfw pldl1keep, p0, \[sp,z0\.d,uxtw #2\] -.*: c42043e0 prfw pldl1keep, p0, \[sp,z0\.d,uxtw #2\] -.*: c4244000 prfw pldl1keep, p0, \[x0,z4\.d,uxtw #2\] -.*: c4244000 prfw pldl1keep, p0, \[x0,z4\.d,uxtw #2\] -.*: c43f4000 prfw pldl1keep, p0, \[x0,z31\.d,uxtw #2\] -.*: c43f4000 prfw pldl1keep, p0, \[x0,z31\.d,uxtw #2\] -.*: c4604000 prfw pldl1keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604000 prfw pldl1keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604001 prfw pldl1strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604001 prfw pldl1strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604002 prfw pldl2keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604002 prfw pldl2keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604003 prfw pldl2strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604003 prfw pldl2strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604004 prfw pldl3keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604004 prfw pldl3keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604005 prfw pldl3strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604005 prfw pldl3strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604006 prfw #6, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604006 prfw #6, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604007 prfw #7, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604007 prfw #7, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604008 prfw pstl1keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604008 prfw pstl1keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604009 prfw pstl1strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604009 prfw pstl1strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400a prfw pstl2keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400a prfw pstl2keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400b prfw pstl2strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400b prfw pstl2strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400c prfw pstl3keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400c prfw pstl3keep, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400d prfw pstl3strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400d prfw pstl3strm, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400e prfw #14, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400e prfw #14, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400f prfw #15, p0, \[x0,z0\.d,sxtw #2\] -.*: c460400f prfw #15, p0, \[x0,z0\.d,sxtw #2\] -.*: c4604800 prfw pldl1keep, p2, \[x0,z0\.d,sxtw #2\] -.*: c4604800 prfw pldl1keep, p2, \[x0,z0\.d,sxtw #2\] -.*: c4605c00 prfw pldl1keep, p7, \[x0,z0\.d,sxtw #2\] -.*: c4605c00 prfw pldl1keep, p7, \[x0,z0\.d,sxtw #2\] -.*: c4604060 prfw pldl1keep, p0, \[x3,z0\.d,sxtw #2\] -.*: c4604060 prfw pldl1keep, p0, \[x3,z0\.d,sxtw #2\] -.*: c46043e0 prfw pldl1keep, p0, \[sp,z0\.d,sxtw #2\] -.*: c46043e0 prfw pldl1keep, p0, \[sp,z0\.d,sxtw #2\] -.*: c4644000 prfw pldl1keep, p0, \[x0,z4\.d,sxtw #2\] -.*: c4644000 prfw pldl1keep, p0, \[x0,z4\.d,sxtw #2\] -.*: c47f4000 prfw pldl1keep, p0, \[x0,z31\.d,sxtw #2\] -.*: c47f4000 prfw pldl1keep, p0, \[x0,z31\.d,sxtw #2\] -.*: c460c000 prfw pldl1keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c000 prfw pldl1keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c001 prfw pldl1strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c001 prfw pldl1strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c002 prfw pldl2keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c002 prfw pldl2keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c003 prfw pldl2strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c003 prfw pldl2strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c004 prfw pldl3keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c004 prfw pldl3keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c005 prfw pldl3strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c005 prfw pldl3strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c006 prfw #6, p0, \[x0,z0\.d,lsl #2\] -.*: c460c006 prfw #6, p0, \[x0,z0\.d,lsl #2\] -.*: c460c007 prfw #7, p0, \[x0,z0\.d,lsl #2\] -.*: c460c007 prfw #7, p0, \[x0,z0\.d,lsl #2\] -.*: c460c008 prfw pstl1keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c008 prfw pstl1keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c009 prfw pstl1strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c009 prfw pstl1strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00a prfw pstl2keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00a prfw pstl2keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00b prfw pstl2strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00b prfw pstl2strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00c prfw pstl3keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00c prfw pstl3keep, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00d prfw pstl3strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00d prfw pstl3strm, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00e prfw #14, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00e prfw #14, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00f prfw #15, p0, \[x0,z0\.d,lsl #2\] -.*: c460c00f prfw #15, p0, \[x0,z0\.d,lsl #2\] -.*: c460c800 prfw pldl1keep, p2, \[x0,z0\.d,lsl #2\] -.*: c460c800 prfw pldl1keep, p2, \[x0,z0\.d,lsl #2\] -.*: c460dc00 prfw pldl1keep, p7, \[x0,z0\.d,lsl #2\] -.*: c460dc00 prfw pldl1keep, p7, \[x0,z0\.d,lsl #2\] -.*: c460c060 prfw pldl1keep, p0, \[x3,z0\.d,lsl #2\] -.*: c460c060 prfw pldl1keep, p0, \[x3,z0\.d,lsl #2\] -.*: c460c3e0 prfw pldl1keep, p0, \[sp,z0\.d,lsl #2\] -.*: c460c3e0 prfw pldl1keep, p0, \[sp,z0\.d,lsl #2\] -.*: c464c000 prfw pldl1keep, p0, \[x0,z4\.d,lsl #2\] -.*: c464c000 prfw pldl1keep, p0, \[x0,z4\.d,lsl #2\] -.*: c47fc000 prfw pldl1keep, p0, \[x0,z31\.d,lsl #2\] -.*: c47fc000 prfw pldl1keep, p0, \[x0,z31\.d,lsl #2\] +.*: c48fe000 prfh pldl1keep, p0, \[z0\.d, #30\] +.*: c48fe000 prfh pldl1keep, p0, \[z0\.d, #30\] +.*: c490e000 prfh pldl1keep, p0, \[z0\.d, #32\] +.*: c490e000 prfh pldl1keep, p0, \[z0\.d, #32\] +.*: c491e000 prfh pldl1keep, p0, \[z0\.d, #34\] +.*: c491e000 prfh pldl1keep, p0, \[z0\.d, #34\] +.*: c49fe000 prfh pldl1keep, p0, \[z0\.d, #62\] +.*: c49fe000 prfh pldl1keep, p0, \[z0\.d, #62\] +.*: 84204000 prfw pldl1keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204000 prfw pldl1keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204001 prfw pldl1strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204001 prfw pldl1strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204002 prfw pldl2keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204002 prfw pldl2keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204003 prfw pldl2strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204003 prfw pldl2strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204004 prfw pldl3keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204004 prfw pldl3keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204005 prfw pldl3strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204005 prfw pldl3strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204006 prfw #6, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204006 prfw #6, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204007 prfw #7, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204007 prfw #7, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204008 prfw pstl1keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204008 prfw pstl1keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204009 prfw pstl1strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204009 prfw pstl1strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400a prfw pstl2keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400a prfw pstl2keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400b prfw pstl2strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400b prfw pstl2strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400c prfw pstl3keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400c prfw pstl3keep, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400d prfw pstl3strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400d prfw pstl3strm, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400e prfw #14, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400e prfw #14, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400f prfw #15, p0, \[x0, z0\.s, uxtw #2\] +.*: 8420400f prfw #15, p0, \[x0, z0\.s, uxtw #2\] +.*: 84204800 prfw pldl1keep, p2, \[x0, z0\.s, uxtw #2\] +.*: 84204800 prfw pldl1keep, p2, \[x0, z0\.s, uxtw #2\] +.*: 84205c00 prfw pldl1keep, p7, \[x0, z0\.s, uxtw #2\] +.*: 84205c00 prfw pldl1keep, p7, \[x0, z0\.s, uxtw #2\] +.*: 84204060 prfw pldl1keep, p0, \[x3, z0\.s, uxtw #2\] +.*: 84204060 prfw pldl1keep, p0, \[x3, z0\.s, uxtw #2\] +.*: 842043e0 prfw pldl1keep, p0, \[sp, z0\.s, uxtw #2\] +.*: 842043e0 prfw pldl1keep, p0, \[sp, z0\.s, uxtw #2\] +.*: 84244000 prfw pldl1keep, p0, \[x0, z4\.s, uxtw #2\] +.*: 84244000 prfw pldl1keep, p0, \[x0, z4\.s, uxtw #2\] +.*: 843f4000 prfw pldl1keep, p0, \[x0, z31\.s, uxtw #2\] +.*: 843f4000 prfw pldl1keep, p0, \[x0, z31\.s, uxtw #2\] +.*: 84604000 prfw pldl1keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604000 prfw pldl1keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604001 prfw pldl1strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604001 prfw pldl1strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604002 prfw pldl2keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604002 prfw pldl2keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604003 prfw pldl2strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604003 prfw pldl2strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604004 prfw pldl3keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604004 prfw pldl3keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604005 prfw pldl3strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604005 prfw pldl3strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604006 prfw #6, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604006 prfw #6, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604007 prfw #7, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604007 prfw #7, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604008 prfw pstl1keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604008 prfw pstl1keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604009 prfw pstl1strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604009 prfw pstl1strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400a prfw pstl2keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400a prfw pstl2keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400b prfw pstl2strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400b prfw pstl2strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400c prfw pstl3keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400c prfw pstl3keep, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400d prfw pstl3strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400d prfw pstl3strm, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400e prfw #14, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400e prfw #14, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400f prfw #15, p0, \[x0, z0\.s, sxtw #2\] +.*: 8460400f prfw #15, p0, \[x0, z0\.s, sxtw #2\] +.*: 84604800 prfw pldl1keep, p2, \[x0, z0\.s, sxtw #2\] +.*: 84604800 prfw pldl1keep, p2, \[x0, z0\.s, sxtw #2\] +.*: 84605c00 prfw pldl1keep, p7, \[x0, z0\.s, sxtw #2\] +.*: 84605c00 prfw pldl1keep, p7, \[x0, z0\.s, sxtw #2\] +.*: 84604060 prfw pldl1keep, p0, \[x3, z0\.s, sxtw #2\] +.*: 84604060 prfw pldl1keep, p0, \[x3, z0\.s, sxtw #2\] +.*: 846043e0 prfw pldl1keep, p0, \[sp, z0\.s, sxtw #2\] +.*: 846043e0 prfw pldl1keep, p0, \[sp, z0\.s, sxtw #2\] +.*: 84644000 prfw pldl1keep, p0, \[x0, z4\.s, sxtw #2\] +.*: 84644000 prfw pldl1keep, p0, \[x0, z4\.s, sxtw #2\] +.*: 847f4000 prfw pldl1keep, p0, \[x0, z31\.s, sxtw #2\] +.*: 847f4000 prfw pldl1keep, p0, \[x0, z31\.s, sxtw #2\] +.*: 8500c000 prfw pldl1keep, p0, \[x0, x0, lsl #2\] +.*: 8500c000 prfw pldl1keep, p0, \[x0, x0, lsl #2\] +.*: 8500c001 prfw pldl1strm, p0, \[x0, x0, lsl #2\] +.*: 8500c001 prfw pldl1strm, p0, \[x0, x0, lsl #2\] +.*: 8500c002 prfw pldl2keep, p0, \[x0, x0, lsl #2\] +.*: 8500c002 prfw pldl2keep, p0, \[x0, x0, lsl #2\] +.*: 8500c003 prfw pldl2strm, p0, \[x0, x0, lsl #2\] +.*: 8500c003 prfw pldl2strm, p0, \[x0, x0, lsl #2\] +.*: 8500c004 prfw pldl3keep, p0, \[x0, x0, lsl #2\] +.*: 8500c004 prfw pldl3keep, p0, \[x0, x0, lsl #2\] +.*: 8500c005 prfw pldl3strm, p0, \[x0, x0, lsl #2\] +.*: 8500c005 prfw pldl3strm, p0, \[x0, x0, lsl #2\] +.*: 8500c006 prfw #6, p0, \[x0, x0, lsl #2\] +.*: 8500c006 prfw #6, p0, \[x0, x0, lsl #2\] +.*: 8500c007 prfw #7, p0, \[x0, x0, lsl #2\] +.*: 8500c007 prfw #7, p0, \[x0, x0, lsl #2\] +.*: 8500c008 prfw pstl1keep, p0, \[x0, x0, lsl #2\] +.*: 8500c008 prfw pstl1keep, p0, \[x0, x0, lsl #2\] +.*: 8500c009 prfw pstl1strm, p0, \[x0, x0, lsl #2\] +.*: 8500c009 prfw pstl1strm, p0, \[x0, x0, lsl #2\] +.*: 8500c00a prfw pstl2keep, p0, \[x0, x0, lsl #2\] +.*: 8500c00a prfw pstl2keep, p0, \[x0, x0, lsl #2\] +.*: 8500c00b prfw pstl2strm, p0, \[x0, x0, lsl #2\] +.*: 8500c00b prfw pstl2strm, p0, \[x0, x0, lsl #2\] +.*: 8500c00c prfw pstl3keep, p0, \[x0, x0, lsl #2\] +.*: 8500c00c prfw pstl3keep, p0, \[x0, x0, lsl #2\] +.*: 8500c00d prfw pstl3strm, p0, \[x0, x0, lsl #2\] +.*: 8500c00d prfw pstl3strm, p0, \[x0, x0, lsl #2\] +.*: 8500c00e prfw #14, p0, \[x0, x0, lsl #2\] +.*: 8500c00e prfw #14, p0, \[x0, x0, lsl #2\] +.*: 8500c00f prfw #15, p0, \[x0, x0, lsl #2\] +.*: 8500c00f prfw #15, p0, \[x0, x0, lsl #2\] +.*: 8500c800 prfw pldl1keep, p2, \[x0, x0, lsl #2\] +.*: 8500c800 prfw pldl1keep, p2, \[x0, x0, lsl #2\] +.*: 8500dc00 prfw pldl1keep, p7, \[x0, x0, lsl #2\] +.*: 8500dc00 prfw pldl1keep, p7, \[x0, x0, lsl #2\] +.*: 8500c060 prfw pldl1keep, p0, \[x3, x0, lsl #2\] +.*: 8500c060 prfw pldl1keep, p0, \[x3, x0, lsl #2\] +.*: 8500c3e0 prfw pldl1keep, p0, \[sp, x0, lsl #2\] +.*: 8500c3e0 prfw pldl1keep, p0, \[sp, x0, lsl #2\] +.*: 8504c000 prfw pldl1keep, p0, \[x0, x4, lsl #2\] +.*: 8504c000 prfw pldl1keep, p0, \[x0, x4, lsl #2\] +.*: 851ec000 prfw pldl1keep, p0, \[x0, x30, lsl #2\] +.*: 851ec000 prfw pldl1keep, p0, \[x0, x30, lsl #2\] +.*: c4204000 prfw pldl1keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204000 prfw pldl1keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204001 prfw pldl1strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204001 prfw pldl1strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204002 prfw pldl2keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204002 prfw pldl2keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204003 prfw pldl2strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204003 prfw pldl2strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204004 prfw pldl3keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204004 prfw pldl3keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204005 prfw pldl3strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204005 prfw pldl3strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204006 prfw #6, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204006 prfw #6, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204007 prfw #7, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204007 prfw #7, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204008 prfw pstl1keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204008 prfw pstl1keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204009 prfw pstl1strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204009 prfw pstl1strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400a prfw pstl2keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400a prfw pstl2keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400b prfw pstl2strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400b prfw pstl2strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400c prfw pstl3keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400c prfw pstl3keep, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400d prfw pstl3strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400d prfw pstl3strm, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400e prfw #14, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400e prfw #14, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400f prfw #15, p0, \[x0, z0\.d, uxtw #2\] +.*: c420400f prfw #15, p0, \[x0, z0\.d, uxtw #2\] +.*: c4204800 prfw pldl1keep, p2, \[x0, z0\.d, uxtw #2\] +.*: c4204800 prfw pldl1keep, p2, \[x0, z0\.d, uxtw #2\] +.*: c4205c00 prfw pldl1keep, p7, \[x0, z0\.d, uxtw #2\] +.*: c4205c00 prfw pldl1keep, p7, \[x0, z0\.d, uxtw #2\] +.*: c4204060 prfw pldl1keep, p0, \[x3, z0\.d, uxtw #2\] +.*: c4204060 prfw pldl1keep, p0, \[x3, z0\.d, uxtw #2\] +.*: c42043e0 prfw pldl1keep, p0, \[sp, z0\.d, uxtw #2\] +.*: c42043e0 prfw pldl1keep, p0, \[sp, z0\.d, uxtw #2\] +.*: c4244000 prfw pldl1keep, p0, \[x0, z4\.d, uxtw #2\] +.*: c4244000 prfw pldl1keep, p0, \[x0, z4\.d, uxtw #2\] +.*: c43f4000 prfw pldl1keep, p0, \[x0, z31\.d, uxtw #2\] +.*: c43f4000 prfw pldl1keep, p0, \[x0, z31\.d, uxtw #2\] +.*: c4604000 prfw pldl1keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604000 prfw pldl1keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604001 prfw pldl1strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604001 prfw pldl1strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604002 prfw pldl2keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604002 prfw pldl2keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604003 prfw pldl2strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604003 prfw pldl2strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604004 prfw pldl3keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604004 prfw pldl3keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604005 prfw pldl3strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604005 prfw pldl3strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604006 prfw #6, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604006 prfw #6, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604007 prfw #7, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604007 prfw #7, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604008 prfw pstl1keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604008 prfw pstl1keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604009 prfw pstl1strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604009 prfw pstl1strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400a prfw pstl2keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400a prfw pstl2keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400b prfw pstl2strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400b prfw pstl2strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400c prfw pstl3keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400c prfw pstl3keep, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400d prfw pstl3strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400d prfw pstl3strm, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400e prfw #14, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400e prfw #14, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400f prfw #15, p0, \[x0, z0\.d, sxtw #2\] +.*: c460400f prfw #15, p0, \[x0, z0\.d, sxtw #2\] +.*: c4604800 prfw pldl1keep, p2, \[x0, z0\.d, sxtw #2\] +.*: c4604800 prfw pldl1keep, p2, \[x0, z0\.d, sxtw #2\] +.*: c4605c00 prfw pldl1keep, p7, \[x0, z0\.d, sxtw #2\] +.*: c4605c00 prfw pldl1keep, p7, \[x0, z0\.d, sxtw #2\] +.*: c4604060 prfw pldl1keep, p0, \[x3, z0\.d, sxtw #2\] +.*: c4604060 prfw pldl1keep, p0, \[x3, z0\.d, sxtw #2\] +.*: c46043e0 prfw pldl1keep, p0, \[sp, z0\.d, sxtw #2\] +.*: c46043e0 prfw pldl1keep, p0, \[sp, z0\.d, sxtw #2\] +.*: c4644000 prfw pldl1keep, p0, \[x0, z4\.d, sxtw #2\] +.*: c4644000 prfw pldl1keep, p0, \[x0, z4\.d, sxtw #2\] +.*: c47f4000 prfw pldl1keep, p0, \[x0, z31\.d, sxtw #2\] +.*: c47f4000 prfw pldl1keep, p0, \[x0, z31\.d, sxtw #2\] +.*: c460c000 prfw pldl1keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c000 prfw pldl1keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c001 prfw pldl1strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c001 prfw pldl1strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c002 prfw pldl2keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c002 prfw pldl2keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c003 prfw pldl2strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c003 prfw pldl2strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c004 prfw pldl3keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c004 prfw pldl3keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c005 prfw pldl3strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c005 prfw pldl3strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c006 prfw #6, p0, \[x0, z0\.d, lsl #2\] +.*: c460c006 prfw #6, p0, \[x0, z0\.d, lsl #2\] +.*: c460c007 prfw #7, p0, \[x0, z0\.d, lsl #2\] +.*: c460c007 prfw #7, p0, \[x0, z0\.d, lsl #2\] +.*: c460c008 prfw pstl1keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c008 prfw pstl1keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c009 prfw pstl1strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c009 prfw pstl1strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00a prfw pstl2keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00a prfw pstl2keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00b prfw pstl2strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00b prfw pstl2strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00c prfw pstl3keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00c prfw pstl3keep, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00d prfw pstl3strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00d prfw pstl3strm, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00e prfw #14, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00e prfw #14, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00f prfw #15, p0, \[x0, z0\.d, lsl #2\] +.*: c460c00f prfw #15, p0, \[x0, z0\.d, lsl #2\] +.*: c460c800 prfw pldl1keep, p2, \[x0, z0\.d, lsl #2\] +.*: c460c800 prfw pldl1keep, p2, \[x0, z0\.d, lsl #2\] +.*: c460dc00 prfw pldl1keep, p7, \[x0, z0\.d, lsl #2\] +.*: c460dc00 prfw pldl1keep, p7, \[x0, z0\.d, lsl #2\] +.*: c460c060 prfw pldl1keep, p0, \[x3, z0\.d, lsl #2\] +.*: c460c060 prfw pldl1keep, p0, \[x3, z0\.d, lsl #2\] +.*: c460c3e0 prfw pldl1keep, p0, \[sp, z0\.d, lsl #2\] +.*: c460c3e0 prfw pldl1keep, p0, \[sp, z0\.d, lsl #2\] +.*: c464c000 prfw pldl1keep, p0, \[x0, z4\.d, lsl #2\] +.*: c464c000 prfw pldl1keep, p0, \[x0, z4\.d, lsl #2\] +.*: c47fc000 prfw pldl1keep, p0, \[x0, z31\.d, lsl #2\] +.*: c47fc000 prfw pldl1keep, p0, \[x0, z31\.d, lsl #2\] .*: 8500e000 prfw pldl1keep, p0, \[z0\.s\] .*: 8500e000 prfw pldl1keep, p0, \[z0\.s\] .*: 8500e000 prfw pldl1keep, p0, \[z0\.s\] @@ -23906,14 +23906,14 @@ Disassembly of section .*: .*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\] .*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\] .*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\] -.*: 850fe000 prfw pldl1keep, p0, \[z0\.s,#60\] -.*: 850fe000 prfw pldl1keep, p0, \[z0\.s,#60\] -.*: 8510e000 prfw pldl1keep, p0, \[z0\.s,#64\] -.*: 8510e000 prfw pldl1keep, p0, \[z0\.s,#64\] -.*: 8511e000 prfw pldl1keep, p0, \[z0\.s,#68\] -.*: 8511e000 prfw pldl1keep, p0, \[z0\.s,#68\] -.*: 851fe000 prfw pldl1keep, p0, \[z0\.s,#124\] -.*: 851fe000 prfw pldl1keep, p0, \[z0\.s,#124\] +.*: 850fe000 prfw pldl1keep, p0, \[z0\.s, #60\] +.*: 850fe000 prfw pldl1keep, p0, \[z0\.s, #60\] +.*: 8510e000 prfw pldl1keep, p0, \[z0\.s, #64\] +.*: 8510e000 prfw pldl1keep, p0, \[z0\.s, #64\] +.*: 8511e000 prfw pldl1keep, p0, \[z0\.s, #68\] +.*: 8511e000 prfw pldl1keep, p0, \[z0\.s, #68\] +.*: 851fe000 prfw pldl1keep, p0, \[z0\.s, #124\] +.*: 851fe000 prfw pldl1keep, p0, \[z0\.s, #124\] .*: 85c04000 prfw pldl1keep, p0, \[x0\] .*: 85c04000 prfw pldl1keep, p0, \[x0\] .*: 85c04000 prfw pldl1keep, p0, \[x0\] @@ -23994,14 +23994,14 @@ Disassembly of section .*: .*: 85c043e0 prfw pldl1keep, p0, \[sp\] .*: 85c043e0 prfw pldl1keep, p0, \[sp\] .*: 85c043e0 prfw pldl1keep, p0, \[sp\] -.*: 85df4000 prfw pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85df4000 prfw pldl1keep, p0, \[x0,#31,mul vl\] -.*: 85e04000 prfw pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e04000 prfw pldl1keep, p0, \[x0,#-32,mul vl\] -.*: 85e14000 prfw pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85e14000 prfw pldl1keep, p0, \[x0,#-31,mul vl\] -.*: 85ff4000 prfw pldl1keep, p0, \[x0,#-1,mul vl\] -.*: 85ff4000 prfw pldl1keep, p0, \[x0,#-1,mul vl\] +.*: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\] +.*: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\] +.*: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\] +.*: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\] +.*: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\] .*: c500e000 prfw pldl1keep, p0, \[z0\.d\] .*: c500e000 prfw pldl1keep, p0, \[z0\.d\] .*: c500e000 prfw pldl1keep, p0, \[z0\.d\] @@ -24062,14 +24062,14 @@ Disassembly of section .*: .*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\] .*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\] .*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\] -.*: c50fe000 prfw pldl1keep, p0, \[z0\.d,#60\] -.*: c50fe000 prfw pldl1keep, p0, \[z0\.d,#60\] -.*: c510e000 prfw pldl1keep, p0, \[z0\.d,#64\] -.*: c510e000 prfw pldl1keep, p0, \[z0\.d,#64\] -.*: c511e000 prfw pldl1keep, p0, \[z0\.d,#68\] -.*: c511e000 prfw pldl1keep, p0, \[z0\.d,#68\] -.*: c51fe000 prfw pldl1keep, p0, \[z0\.d,#124\] -.*: c51fe000 prfw pldl1keep, p0, \[z0\.d,#124\] +.*: c50fe000 prfw pldl1keep, p0, \[z0\.d, #60\] +.*: c50fe000 prfw pldl1keep, p0, \[z0\.d, #60\] +.*: c510e000 prfw pldl1keep, p0, \[z0\.d, #64\] +.*: c510e000 prfw pldl1keep, p0, \[z0\.d, #64\] +.*: c511e000 prfw pldl1keep, p0, \[z0\.d, #68\] +.*: c511e000 prfw pldl1keep, p0, \[z0\.d, #68\] +.*: c51fe000 prfw pldl1keep, p0, \[z0\.d, #124\] +.*: c51fe000 prfw pldl1keep, p0, \[z0\.d, #124\] .*: 2550c000 ptest p0, p0\.b .*: 2550c000 ptest p0, p0\.b .*: 2550c400 ptest p1, p0\.b @@ -28840,276 +28840,276 @@ Disassembly of section .*: .*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280 .*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280 .*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280 -.*: e4004000 st1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4004000 st1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4004000 st1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4004000 st1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4004001 st1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4004001 st1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4004001 st1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4004001 st1b \{z1\.b\}, p0, \[x0,x0\] -.*: e400401f st1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400401f st1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400401f st1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400401f st1b \{z31\.b\}, p0, \[x0,x0\] -.*: e4004800 st1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4004800 st1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4004800 st1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4005c00 st1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4005c00 st1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4005c00 st1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4004060 st1b \{z0\.b\}, p0, \[x3,x0\] -.*: e4004060 st1b \{z0\.b\}, p0, \[x3,x0\] -.*: e4004060 st1b \{z0\.b\}, p0, \[x3,x0\] -.*: e40043e0 st1b \{z0\.b\}, p0, \[sp,x0\] -.*: e40043e0 st1b \{z0\.b\}, p0, \[sp,x0\] -.*: e40043e0 st1b \{z0\.b\}, p0, \[sp,x0\] -.*: e4044000 st1b \{z0\.b\}, p0, \[x0,x4\] -.*: e4044000 st1b \{z0\.b\}, p0, \[x0,x4\] -.*: e4044000 st1b \{z0\.b\}, p0, \[x0,x4\] -.*: e41e4000 st1b \{z0\.b\}, p0, \[x0,x30\] -.*: e41e4000 st1b \{z0\.b\}, p0, \[x0,x30\] -.*: e41e4000 st1b \{z0\.b\}, p0, \[x0,x30\] -.*: e4008000 st1b \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008000 st1b \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008000 st1b \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008000 st1b \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008001 st1b \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008001 st1b \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008001 st1b \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008001 st1b \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e400801f st1b \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e400801f st1b \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e400801f st1b \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e400801f st1b \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4008800 st1b \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4008800 st1b \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4008800 st1b \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4009c00 st1b \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4009c00 st1b \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4009c00 st1b \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4008060 st1b \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e4008060 st1b \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e4008060 st1b \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e40083e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e40083e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e40083e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e4048000 st1b \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e4048000 st1b \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e4048000 st1b \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e41f8000 st1b \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e41f8000 st1b \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e41f8000 st1b \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e400c000 st1b \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c000 st1b \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c000 st1b \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c000 st1b \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c001 st1b \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c001 st1b \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c001 st1b \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c001 st1b \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c01f st1b \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c01f st1b \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c01f st1b \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c01f st1b \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e400c800 st1b \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e400c800 st1b \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e400c800 st1b \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e400dc00 st1b \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e400dc00 st1b \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e400dc00 st1b \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e400c060 st1b \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e400c060 st1b \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e400c060 st1b \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e404c000 st1b \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e404c000 st1b \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e404c000 st1b \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e41fc000 st1b \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e41fc000 st1b \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e41fc000 st1b \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e400a000 st1b \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e400a000 st1b \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e400a000 st1b \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e400a000 st1b \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e400a001 st1b \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e400a001 st1b \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e400a001 st1b \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e400a001 st1b \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e400a01f st1b \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e400a01f st1b \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e400a01f st1b \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e400a01f st1b \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e400a800 st1b \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e400a800 st1b \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e400a800 st1b \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e400bc00 st1b \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e400bc00 st1b \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e400bc00 st1b \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e400a060 st1b \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e400a060 st1b \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e400a060 st1b \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e404a000 st1b \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e404a000 st1b \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e404a000 st1b \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e41fa000 st1b \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e41fa000 st1b \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e41fa000 st1b \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e4204000 st1b \{z0\.h\}, p0, \[x0,x0\] -.*: e4204000 st1b \{z0\.h\}, p0, \[x0,x0\] -.*: e4204000 st1b \{z0\.h\}, p0, \[x0,x0\] -.*: e4204000 st1b \{z0\.h\}, p0, \[x0,x0\] -.*: e4204001 st1b \{z1\.h\}, p0, \[x0,x0\] -.*: e4204001 st1b \{z1\.h\}, p0, \[x0,x0\] -.*: e4204001 st1b \{z1\.h\}, p0, \[x0,x0\] -.*: e4204001 st1b \{z1\.h\}, p0, \[x0,x0\] -.*: e420401f st1b \{z31\.h\}, p0, \[x0,x0\] -.*: e420401f st1b \{z31\.h\}, p0, \[x0,x0\] -.*: e420401f st1b \{z31\.h\}, p0, \[x0,x0\] -.*: e420401f st1b \{z31\.h\}, p0, \[x0,x0\] -.*: e4204800 st1b \{z0\.h\}, p2, \[x0,x0\] -.*: e4204800 st1b \{z0\.h\}, p2, \[x0,x0\] -.*: e4204800 st1b \{z0\.h\}, p2, \[x0,x0\] -.*: e4205c00 st1b \{z0\.h\}, p7, \[x0,x0\] -.*: e4205c00 st1b \{z0\.h\}, p7, \[x0,x0\] -.*: e4205c00 st1b \{z0\.h\}, p7, \[x0,x0\] -.*: e4204060 st1b \{z0\.h\}, p0, \[x3,x0\] -.*: e4204060 st1b \{z0\.h\}, p0, \[x3,x0\] -.*: e4204060 st1b \{z0\.h\}, p0, \[x3,x0\] -.*: e42043e0 st1b \{z0\.h\}, p0, \[sp,x0\] -.*: e42043e0 st1b \{z0\.h\}, p0, \[sp,x0\] -.*: e42043e0 st1b \{z0\.h\}, p0, \[sp,x0\] -.*: e4244000 st1b \{z0\.h\}, p0, \[x0,x4\] -.*: e4244000 st1b \{z0\.h\}, p0, \[x0,x4\] -.*: e4244000 st1b \{z0\.h\}, p0, \[x0,x4\] -.*: e43e4000 st1b \{z0\.h\}, p0, \[x0,x30\] -.*: e43e4000 st1b \{z0\.h\}, p0, \[x0,x30\] -.*: e43e4000 st1b \{z0\.h\}, p0, \[x0,x30\] -.*: e4404000 st1b \{z0\.s\}, p0, \[x0,x0\] -.*: e4404000 st1b \{z0\.s\}, p0, \[x0,x0\] -.*: e4404000 st1b \{z0\.s\}, p0, \[x0,x0\] -.*: e4404000 st1b \{z0\.s\}, p0, \[x0,x0\] -.*: e4404001 st1b \{z1\.s\}, p0, \[x0,x0\] -.*: e4404001 st1b \{z1\.s\}, p0, \[x0,x0\] -.*: e4404001 st1b \{z1\.s\}, p0, \[x0,x0\] -.*: e4404001 st1b \{z1\.s\}, p0, \[x0,x0\] -.*: e440401f st1b \{z31\.s\}, p0, \[x0,x0\] -.*: e440401f st1b \{z31\.s\}, p0, \[x0,x0\] -.*: e440401f st1b \{z31\.s\}, p0, \[x0,x0\] -.*: e440401f st1b \{z31\.s\}, p0, \[x0,x0\] -.*: e4404800 st1b \{z0\.s\}, p2, \[x0,x0\] -.*: e4404800 st1b \{z0\.s\}, p2, \[x0,x0\] -.*: e4404800 st1b \{z0\.s\}, p2, \[x0,x0\] -.*: e4405c00 st1b \{z0\.s\}, p7, \[x0,x0\] -.*: e4405c00 st1b \{z0\.s\}, p7, \[x0,x0\] -.*: e4405c00 st1b \{z0\.s\}, p7, \[x0,x0\] -.*: e4404060 st1b \{z0\.s\}, p0, \[x3,x0\] -.*: e4404060 st1b \{z0\.s\}, p0, \[x3,x0\] -.*: e4404060 st1b \{z0\.s\}, p0, \[x3,x0\] -.*: e44043e0 st1b \{z0\.s\}, p0, \[sp,x0\] -.*: e44043e0 st1b \{z0\.s\}, p0, \[sp,x0\] -.*: e44043e0 st1b \{z0\.s\}, p0, \[sp,x0\] -.*: e4444000 st1b \{z0\.s\}, p0, \[x0,x4\] -.*: e4444000 st1b \{z0\.s\}, p0, \[x0,x4\] -.*: e4444000 st1b \{z0\.s\}, p0, \[x0,x4\] -.*: e45e4000 st1b \{z0\.s\}, p0, \[x0,x30\] -.*: e45e4000 st1b \{z0\.s\}, p0, \[x0,x30\] -.*: e45e4000 st1b \{z0\.s\}, p0, \[x0,x30\] -.*: e4408000 st1b \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408000 st1b \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408000 st1b \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408000 st1b \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408001 st1b \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408001 st1b \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408001 st1b \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408001 st1b \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e440801f st1b \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e440801f st1b \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e440801f st1b \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e440801f st1b \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4408800 st1b \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4408800 st1b \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4408800 st1b \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4409c00 st1b \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4409c00 st1b \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4409c00 st1b \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4408060 st1b \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e4408060 st1b \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e4408060 st1b \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e44083e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e44083e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e44083e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e4448000 st1b \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e4448000 st1b \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e4448000 st1b \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e45f8000 st1b \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e45f8000 st1b \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e45f8000 st1b \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e440c000 st1b \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c000 st1b \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c000 st1b \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c000 st1b \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c001 st1b \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c001 st1b \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c001 st1b \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c001 st1b \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c01f st1b \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c01f st1b \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c01f st1b \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c01f st1b \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e440c800 st1b \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e440c800 st1b \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e440c800 st1b \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e440dc00 st1b \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e440dc00 st1b \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e440dc00 st1b \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e440c060 st1b \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e440c060 st1b \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e440c060 st1b \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e444c000 st1b \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e444c000 st1b \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e444c000 st1b \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e45fc000 st1b \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e45fc000 st1b \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e45fc000 st1b \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e4604000 st1b \{z0\.d\}, p0, \[x0,x0\] -.*: e4604000 st1b \{z0\.d\}, p0, \[x0,x0\] -.*: e4604000 st1b \{z0\.d\}, p0, \[x0,x0\] -.*: e4604000 st1b \{z0\.d\}, p0, \[x0,x0\] -.*: e4604001 st1b \{z1\.d\}, p0, \[x0,x0\] -.*: e4604001 st1b \{z1\.d\}, p0, \[x0,x0\] -.*: e4604001 st1b \{z1\.d\}, p0, \[x0,x0\] -.*: e4604001 st1b \{z1\.d\}, p0, \[x0,x0\] -.*: e460401f st1b \{z31\.d\}, p0, \[x0,x0\] -.*: e460401f st1b \{z31\.d\}, p0, \[x0,x0\] -.*: e460401f st1b \{z31\.d\}, p0, \[x0,x0\] -.*: e460401f st1b \{z31\.d\}, p0, \[x0,x0\] -.*: e4604800 st1b \{z0\.d\}, p2, \[x0,x0\] -.*: e4604800 st1b \{z0\.d\}, p2, \[x0,x0\] -.*: e4604800 st1b \{z0\.d\}, p2, \[x0,x0\] -.*: e4605c00 st1b \{z0\.d\}, p7, \[x0,x0\] -.*: e4605c00 st1b \{z0\.d\}, p7, \[x0,x0\] -.*: e4605c00 st1b \{z0\.d\}, p7, \[x0,x0\] -.*: e4604060 st1b \{z0\.d\}, p0, \[x3,x0\] -.*: e4604060 st1b \{z0\.d\}, p0, \[x3,x0\] -.*: e4604060 st1b \{z0\.d\}, p0, \[x3,x0\] -.*: e46043e0 st1b \{z0\.d\}, p0, \[sp,x0\] -.*: e46043e0 st1b \{z0\.d\}, p0, \[sp,x0\] -.*: e46043e0 st1b \{z0\.d\}, p0, \[sp,x0\] -.*: e4644000 st1b \{z0\.d\}, p0, \[x0,x4\] -.*: e4644000 st1b \{z0\.d\}, p0, \[x0,x4\] -.*: e4644000 st1b \{z0\.d\}, p0, \[x0,x4\] -.*: e47e4000 st1b \{z0\.d\}, p0, \[x0,x30\] -.*: e47e4000 st1b \{z0\.d\}, p0, \[x0,x30\] -.*: e47e4000 st1b \{z0\.d\}, p0, \[x0,x30\] +.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\] +.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\] +.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\] +.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\] +.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\] +.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\] +.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\] +.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\] +.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\] +.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\] +.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\] +.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\] +.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\] +.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\] +.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\] +.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\] +.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\] +.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\] +.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\] +.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\] +.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\] +.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\] +.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\] +.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\] +.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\] +.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\] +.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\] +.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\] +.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\] +.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\] +.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\] +.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\] +.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\] +.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\] +.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\] +.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\] +.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\] +.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\] +.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\] +.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\] +.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\] +.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\] +.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\] +.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\] +.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\] +.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\] +.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\] +.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\] +.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\] +.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\] +.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\] +.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\] +.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\] +.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\] +.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\] +.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\] +.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\] +.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\] +.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\] +.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\] +.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\] +.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\] +.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\] +.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\] +.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\] +.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\] +.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\] +.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\] +.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\] +.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\] +.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\] +.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\] +.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\] +.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\] +.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\] +.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\] +.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\] +.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\] +.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\] +.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\] +.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\] +.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\] +.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\] +.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\] +.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\] +.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\] +.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\] +.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\] +.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\] +.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\] +.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\] +.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\] +.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\] +.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\] +.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\] +.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\] +.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\] +.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\] +.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\] +.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\] +.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\] +.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\] +.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\] +.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\] .*: e400e000 st1b \{z0\.b\}, p0, \[x0\] .*: e400e000 st1b \{z0\.b\}, p0, \[x0\] .*: e400e000 st1b \{z0\.b\}, p0, \[x0\] @@ -29141,14 +29141,14 @@ Disassembly of section .*: .*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\] .*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\] .*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\] -.*: e407e000 st1b \{z0\.b\}, p0, \[x0,#7,mul vl\] -.*: e407e000 st1b \{z0\.b\}, p0, \[x0,#7,mul vl\] -.*: e408e000 st1b \{z0\.b\}, p0, \[x0,#-8,mul vl\] -.*: e408e000 st1b \{z0\.b\}, p0, \[x0,#-8,mul vl\] -.*: e409e000 st1b \{z0\.b\}, p0, \[x0,#-7,mul vl\] -.*: e409e000 st1b \{z0\.b\}, p0, \[x0,#-7,mul vl\] -.*: e40fe000 st1b \{z0\.b\}, p0, \[x0,#-1,mul vl\] -.*: e40fe000 st1b \{z0\.b\}, p0, \[x0,#-1,mul vl\] +.*: e407e000 st1b \{z0\.b\}, p0, \[x0, #7, mul vl\] +.*: e407e000 st1b \{z0\.b\}, p0, \[x0, #7, mul vl\] +.*: e408e000 st1b \{z0\.b\}, p0, \[x0, #-8, mul vl\] +.*: e408e000 st1b \{z0\.b\}, p0, \[x0, #-8, mul vl\] +.*: e409e000 st1b \{z0\.b\}, p0, \[x0, #-7, mul vl\] +.*: e409e000 st1b \{z0\.b\}, p0, \[x0, #-7, mul vl\] +.*: e40fe000 st1b \{z0\.b\}, p0, \[x0, #-1, mul vl\] +.*: e40fe000 st1b \{z0\.b\}, p0, \[x0, #-1, mul vl\] .*: e420e000 st1b \{z0\.h\}, p0, \[x0\] .*: e420e000 st1b \{z0\.h\}, p0, \[x0\] .*: e420e000 st1b \{z0\.h\}, p0, \[x0\] @@ -29180,14 +29180,14 @@ Disassembly of section .*: .*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\] .*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\] .*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\] -.*: e427e000 st1b \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e427e000 st1b \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e428e000 st1b \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e428e000 st1b \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e429e000 st1b \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e429e000 st1b \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e42fe000 st1b \{z0\.h\}, p0, \[x0,#-1,mul vl\] -.*: e42fe000 st1b \{z0\.h\}, p0, \[x0,#-1,mul vl\] +.*: e427e000 st1b \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e427e000 st1b \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e428e000 st1b \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e428e000 st1b \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e429e000 st1b \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e429e000 st1b \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e42fe000 st1b \{z0\.h\}, p0, \[x0, #-1, mul vl\] +.*: e42fe000 st1b \{z0\.h\}, p0, \[x0, #-1, mul vl\] .*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\] .*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\] .*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\] @@ -29212,14 +29212,14 @@ Disassembly of section .*: .*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\] .*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\] .*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\] -.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d,#15\] -.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d,#15\] -.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d,#16\] -.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d,#16\] -.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d,#17\] -.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d,#17\] -.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d,#31\] -.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d,#31\] +.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d, #15\] +.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d, #15\] +.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d, #16\] +.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d, #16\] +.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d, #17\] +.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d, #17\] +.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d, #31\] +.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d, #31\] .*: e440e000 st1b \{z0\.s\}, p0, \[x0\] .*: e440e000 st1b \{z0\.s\}, p0, \[x0\] .*: e440e000 st1b \{z0\.s\}, p0, \[x0\] @@ -29251,14 +29251,14 @@ Disassembly of section .*: .*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\] .*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\] .*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\] -.*: e447e000 st1b \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e447e000 st1b \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e448e000 st1b \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e448e000 st1b \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e449e000 st1b \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e449e000 st1b \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e44fe000 st1b \{z0\.s\}, p0, \[x0,#-1,mul vl\] -.*: e44fe000 st1b \{z0\.s\}, p0, \[x0,#-1,mul vl\] +.*: e447e000 st1b \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e447e000 st1b \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e448e000 st1b \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e448e000 st1b \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e449e000 st1b \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e449e000 st1b \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e44fe000 st1b \{z0\.s\}, p0, \[x0, #-1, mul vl\] +.*: e44fe000 st1b \{z0\.s\}, p0, \[x0, #-1, mul vl\] .*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\] .*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\] .*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\] @@ -29283,14 +29283,14 @@ Disassembly of section .*: .*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\] .*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\] .*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\] -.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s,#15\] -.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s,#15\] -.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s,#16\] -.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s,#16\] -.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s,#17\] -.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s,#17\] -.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s,#31\] -.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s,#31\] +.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s, #15\] +.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s, #15\] +.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s, #16\] +.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s, #16\] +.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s, #17\] +.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s, #17\] +.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s, #31\] +.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s, #31\] .*: e460e000 st1b \{z0\.d\}, p0, \[x0\] .*: e460e000 st1b \{z0\.d\}, p0, \[x0\] .*: e460e000 st1b \{z0\.d\}, p0, \[x0\] @@ -29322,188 +29322,188 @@ Disassembly of section .*: .*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\] .*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\] .*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\] -.*: e467e000 st1b \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e467e000 st1b \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e468e000 st1b \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e468e000 st1b \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e469e000 st1b \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e469e000 st1b \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e46fe000 st1b \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e46fe000 st1b \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e5808000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e580801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e580801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e580801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e580801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5808800 st1d \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5808800 st1d \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5808800 st1d \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5809c00 st1d \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5809c00 st1d \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5809c00 st1d \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5808060 st1d \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e5808060 st1d \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e5808060 st1d \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e58083e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e58083e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e58083e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e5848000 st1d \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e5848000 st1d \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e5848000 st1d \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e59f8000 st1d \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e59f8000 st1d \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e59f8000 st1d \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e580c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e580c800 st1d \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e580c800 st1d \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e580c800 st1d \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e580dc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e580dc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e580dc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e580c060 st1d \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e580c060 st1d \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e580c060 st1d \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e584c000 st1d \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e584c000 st1d \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e584c000 st1d \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e59fc000 st1d \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e59fc000 st1d \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e59fc000 st1d \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e580a000 st1d \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e580a000 st1d \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e580a000 st1d \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e580a000 st1d \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e580a001 st1d \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e580a001 st1d \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e580a001 st1d \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e580a001 st1d \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e580a01f st1d \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e580a01f st1d \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e580a01f st1d \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e580a01f st1d \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e580a800 st1d \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e580a800 st1d \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e580a800 st1d \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e580bc00 st1d \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e580bc00 st1d \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e580bc00 st1d \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e580a060 st1d \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e580a060 st1d \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e580a060 st1d \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e584a000 st1d \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e584a000 st1d \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e584a000 st1d \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e59fa000 st1d \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e59fa000 st1d \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e59fa000 st1d \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e5a08000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08000 st1d \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08001 st1d \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a0801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a0801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a0801f st1d \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\] -.*: e5a08800 st1d \{z0\.d\}, p2, \[x0,z0\.d,uxtw #3\] -.*: e5a08800 st1d \{z0\.d\}, p2, \[x0,z0\.d,uxtw #3\] -.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0,z0\.d,uxtw #3\] -.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0,z0\.d,uxtw #3\] -.*: e5a08060 st1d \{z0\.d\}, p0, \[x3,z0\.d,uxtw #3\] -.*: e5a08060 st1d \{z0\.d\}, p0, \[x3,z0\.d,uxtw #3\] -.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,uxtw #3\] -.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,uxtw #3\] -.*: e5a48000 st1d \{z0\.d\}, p0, \[x0,z4\.d,uxtw #3\] -.*: e5a48000 st1d \{z0\.d\}, p0, \[x0,z4\.d,uxtw #3\] -.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0,z31\.d,uxtw #3\] -.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0,z31\.d,uxtw #3\] -.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\] -.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0,z0\.d,sxtw #3\] -.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0,z0\.d,sxtw #3\] -.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,sxtw #3\] -.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,sxtw #3\] -.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3,z0\.d,sxtw #3\] -.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3,z0\.d,sxtw #3\] -.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,sxtw #3\] -.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,sxtw #3\] -.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0,z4\.d,sxtw #3\] -.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0,z4\.d,sxtw #3\] -.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0,z31\.d,sxtw #3\] -.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0,z31\.d,sxtw #3\] -.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\] -.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0,z0\.d,lsl #3\] -.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0,z0\.d,lsl #3\] -.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,lsl #3\] -.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0,z0\.d,lsl #3\] -.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3,z0\.d,lsl #3\] -.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3,z0\.d,lsl #3\] -.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,lsl #3\] -.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp,z0\.d,lsl #3\] -.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0,z4\.d,lsl #3\] -.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0,z4\.d,lsl #3\] -.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0,z31\.d,lsl #3\] -.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0,z31\.d,lsl #3\] -.*: e5e04000 st1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04000 st1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04000 st1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04001 st1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04001 st1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04001 st1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e0401f st1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e0401f st1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e0401f st1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e04800 st1d \{z0\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5e04800 st1d \{z0\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5e04060 st1d \{z0\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5e04060 st1d \{z0\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5e44000 st1d \{z0\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5e44000 st1d \{z0\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0,x30,lsl #3\] +.*: e467e000 st1b \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e467e000 st1b \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e468e000 st1b \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e468e000 st1b \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e469e000 st1b \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e469e000 st1b \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e46fe000 st1b \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e46fe000 st1b \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\] +.*: e5a08800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\] +.*: e5a08800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\] +.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\] +.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\] +.*: e5a08060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\] +.*: e5a08060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\] +.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\] +.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\] +.*: e5a48000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\] +.*: e5a48000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\] +.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\] +.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\] +.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\] +.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\] +.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\] +.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\] +.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\] +.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\] +.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\] +.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\] +.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\] +.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\] +.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\] +.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\] +.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\] +.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\] +.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\] +.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\] +.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\] +.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\] +.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\] +.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\] +.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\] +.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\] +.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\] +.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\] +.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\] +.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\] +.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e04800 st1d \{z0\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5e04800 st1d \{z0\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5e04060 st1d \{z0\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5e04060 st1d \{z0\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5e44000 st1d \{z0\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5e44000 st1d \{z0\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0, x30, lsl #3\] .*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\] .*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\] .*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\] @@ -29528,14 +29528,14 @@ Disassembly of section .*: .*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\] .*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\] .*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\] -.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d,#120\] -.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d,#120\] -.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d,#128\] -.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d,#128\] -.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d,#136\] -.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d,#136\] -.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d,#248\] -.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d,#248\] +.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d, #120\] +.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d, #120\] +.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d, #128\] +.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d, #128\] +.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d, #136\] +.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d, #136\] +.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d, #248\] +.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d, #248\] .*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\] .*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\] .*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\] @@ -29567,332 +29567,332 @@ Disassembly of section .*: .*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\] .*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\] .*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\] -.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e5efe000 st1d \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e5efe000 st1d \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e4808000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e480801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e480801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e480801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e480801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e4808800 st1h \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4808800 st1h \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4808800 st1h \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e4809c00 st1h \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4809c00 st1h \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4809c00 st1h \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e4808060 st1h \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e4808060 st1h \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e4808060 st1h \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e48083e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e48083e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e48083e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e4848000 st1h \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e4848000 st1h \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e4848000 st1h \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e49f8000 st1h \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e49f8000 st1h \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e49f8000 st1h \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e480c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e480c800 st1h \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e480c800 st1h \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e480c800 st1h \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e480dc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e480dc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e480dc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e480c060 st1h \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e480c060 st1h \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e480c060 st1h \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e484c000 st1h \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e484c000 st1h \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e484c000 st1h \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e49fc000 st1h \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e49fc000 st1h \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e49fc000 st1h \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e480a000 st1h \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e480a000 st1h \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e480a000 st1h \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e480a000 st1h \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e480a001 st1h \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e480a001 st1h \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e480a001 st1h \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e480a001 st1h \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e480a01f st1h \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e480a01f st1h \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e480a01f st1h \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e480a01f st1h \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e480a800 st1h \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e480a800 st1h \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e480a800 st1h \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e480bc00 st1h \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e480bc00 st1h \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e480bc00 st1h \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e480a060 st1h \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e480a060 st1h \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e480a060 st1h \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e484a000 st1h \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e484a000 st1h \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e484a000 st1h \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e49fa000 st1h \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e49fa000 st1h \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e49fa000 st1h \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e4a04000 st1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04000 st1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04000 st1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04001 st1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04001 st1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04001 st1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a0401f st1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a0401f st1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a0401f st1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a04800 st1h \{z0\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4a04800 st1h \{z0\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4a04060 st1h \{z0\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4a04060 st1h \{z0\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4a44000 st1h \{z0\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4a44000 st1h \{z0\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4be4000 st1h \{z0\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4be4000 st1h \{z0\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4a08000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08000 st1h \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08001 st1h \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a0801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a0801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a0801f st1h \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\] -.*: e4a08800 st1h \{z0\.d\}, p2, \[x0,z0\.d,uxtw #1\] -.*: e4a08800 st1h \{z0\.d\}, p2, \[x0,z0\.d,uxtw #1\] -.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0,z0\.d,uxtw #1\] -.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0,z0\.d,uxtw #1\] -.*: e4a08060 st1h \{z0\.d\}, p0, \[x3,z0\.d,uxtw #1\] -.*: e4a08060 st1h \{z0\.d\}, p0, \[x3,z0\.d,uxtw #1\] -.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,uxtw #1\] -.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,uxtw #1\] -.*: e4a48000 st1h \{z0\.d\}, p0, \[x0,z4\.d,uxtw #1\] -.*: e4a48000 st1h \{z0\.d\}, p0, \[x0,z4\.d,uxtw #1\] -.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0,z31\.d,uxtw #1\] -.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0,z31\.d,uxtw #1\] -.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\] -.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0,z0\.d,sxtw #1\] -.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0,z0\.d,sxtw #1\] -.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,sxtw #1\] -.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,sxtw #1\] -.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3,z0\.d,sxtw #1\] -.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3,z0\.d,sxtw #1\] -.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,sxtw #1\] -.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,sxtw #1\] -.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0,z4\.d,sxtw #1\] -.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0,z4\.d,sxtw #1\] -.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0,z31\.d,sxtw #1\] -.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0,z31\.d,sxtw #1\] -.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\] -.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0,z0\.d,lsl #1\] -.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0,z0\.d,lsl #1\] -.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,lsl #1\] -.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0,z0\.d,lsl #1\] -.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3,z0\.d,lsl #1\] -.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3,z0\.d,lsl #1\] -.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,lsl #1\] -.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp,z0\.d,lsl #1\] -.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0,z4\.d,lsl #1\] -.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0,z4\.d,lsl #1\] -.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0,z31\.d,lsl #1\] -.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0,z31\.d,lsl #1\] -.*: e4c04000 st1h \{z0\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04000 st1h \{z0\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04000 st1h \{z0\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04001 st1h \{z1\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04001 st1h \{z1\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04001 st1h \{z1\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c0401f st1h \{z31\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c0401f st1h \{z31\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c0401f st1h \{z31\.s\}, p0, \[x0,x0,lsl #1\] -.*: e4c04800 st1h \{z0\.s\}, p2, \[x0,x0,lsl #1\] -.*: e4c04800 st1h \{z0\.s\}, p2, \[x0,x0,lsl #1\] -.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0,x0,lsl #1\] -.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0,x0,lsl #1\] -.*: e4c04060 st1h \{z0\.s\}, p0, \[x3,x0,lsl #1\] -.*: e4c04060 st1h \{z0\.s\}, p0, \[x3,x0,lsl #1\] -.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp,x0,lsl #1\] -.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp,x0,lsl #1\] -.*: e4c44000 st1h \{z0\.s\}, p0, \[x0,x4,lsl #1\] -.*: e4c44000 st1h \{z0\.s\}, p0, \[x0,x4,lsl #1\] -.*: e4de4000 st1h \{z0\.s\}, p0, \[x0,x30,lsl #1\] -.*: e4de4000 st1h \{z0\.s\}, p0, \[x0,x30,lsl #1\] -.*: e4c08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e4c08800 st1h \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4c08800 st1h \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4c08800 st1h \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e4c08060 st1h \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e4c08060 st1h \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e4c08060 st1h \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e4c48000 st1h \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e4c48000 st1h \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e4c48000 st1h \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e4df8000 st1h \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e4df8000 st1h \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e4df8000 st1h \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e4e04000 st1h \{z0\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04000 st1h \{z0\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04000 st1h \{z0\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04001 st1h \{z1\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04001 st1h \{z1\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04001 st1h \{z1\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e0401f st1h \{z31\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e0401f st1h \{z31\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e0401f st1h \{z31\.d\}, p0, \[x0,x0,lsl #1\] -.*: e4e04800 st1h \{z0\.d\}, p2, \[x0,x0,lsl #1\] -.*: e4e04800 st1h \{z0\.d\}, p2, \[x0,x0,lsl #1\] -.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0,x0,lsl #1\] -.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0,x0,lsl #1\] -.*: e4e04060 st1h \{z0\.d\}, p0, \[x3,x0,lsl #1\] -.*: e4e04060 st1h \{z0\.d\}, p0, \[x3,x0,lsl #1\] -.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp,x0,lsl #1\] -.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp,x0,lsl #1\] -.*: e4e44000 st1h \{z0\.d\}, p0, \[x0,x4,lsl #1\] -.*: e4e44000 st1h \{z0\.d\}, p0, \[x0,x4,lsl #1\] -.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0,x30,lsl #1\] -.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0,x30,lsl #1\] -.*: e4e08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08000 st1h \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08001 st1h \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e0801f st1h \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\] -.*: e4e08800 st1h \{z0\.s\}, p2, \[x0,z0\.s,uxtw #1\] -.*: e4e08800 st1h \{z0\.s\}, p2, \[x0,z0\.s,uxtw #1\] -.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0,z0\.s,uxtw #1\] -.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0,z0\.s,uxtw #1\] -.*: e4e08060 st1h \{z0\.s\}, p0, \[x3,z0\.s,uxtw #1\] -.*: e4e08060 st1h \{z0\.s\}, p0, \[x3,z0\.s,uxtw #1\] -.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,uxtw #1\] -.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,uxtw #1\] -.*: e4e48000 st1h \{z0\.s\}, p0, \[x0,z4\.s,uxtw #1\] -.*: e4e48000 st1h \{z0\.s\}, p0, \[x0,z4\.s,uxtw #1\] -.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0,z31\.s,uxtw #1\] -.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0,z31\.s,uxtw #1\] -.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\] -.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0,z0\.s,sxtw #1\] -.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0,z0\.s,sxtw #1\] -.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0,z0\.s,sxtw #1\] -.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0,z0\.s,sxtw #1\] -.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3,z0\.s,sxtw #1\] -.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3,z0\.s,sxtw #1\] -.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,sxtw #1\] -.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp,z0\.s,sxtw #1\] -.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0,z4\.s,sxtw #1\] -.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0,z4\.s,sxtw #1\] -.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0,z31\.s,sxtw #1\] -.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0,z31\.s,sxtw #1\] +.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e5efe000 st1d \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e5efe000 st1d \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a04800 st1h \{z0\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4a04800 st1h \{z0\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4a04060 st1h \{z0\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4a04060 st1h \{z0\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4a44000 st1h \{z0\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4a44000 st1h \{z0\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4be4000 st1h \{z0\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4be4000 st1h \{z0\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\] +.*: e4a08800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\] +.*: e4a08800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\] +.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\] +.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\] +.*: e4a08060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\] +.*: e4a08060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\] +.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\] +.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\] +.*: e4a48000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\] +.*: e4a48000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\] +.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\] +.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\] +.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\] +.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\] +.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\] +.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\] +.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\] +.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\] +.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\] +.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\] +.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\] +.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\] +.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\] +.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\] +.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\] +.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\] +.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\] +.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\] +.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\] +.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\] +.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\] +.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\] +.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\] +.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\] +.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\] +.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\] +.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\] +.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\] +.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\] +.*: e4c04800 st1h \{z0\.s\}, p2, \[x0, x0, lsl #1\] +.*: e4c04800 st1h \{z0\.s\}, p2, \[x0, x0, lsl #1\] +.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0, x0, lsl #1\] +.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0, x0, lsl #1\] +.*: e4c04060 st1h \{z0\.s\}, p0, \[x3, x0, lsl #1\] +.*: e4c04060 st1h \{z0\.s\}, p0, \[x3, x0, lsl #1\] +.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp, x0, lsl #1\] +.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp, x0, lsl #1\] +.*: e4c44000 st1h \{z0\.s\}, p0, \[x0, x4, lsl #1\] +.*: e4c44000 st1h \{z0\.s\}, p0, \[x0, x4, lsl #1\] +.*: e4de4000 st1h \{z0\.s\}, p0, \[x0, x30, lsl #1\] +.*: e4de4000 st1h \{z0\.s\}, p0, \[x0, x30, lsl #1\] +.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\] +.*: e4e04800 st1h \{z0\.d\}, p2, \[x0, x0, lsl #1\] +.*: e4e04800 st1h \{z0\.d\}, p2, \[x0, x0, lsl #1\] +.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0, x0, lsl #1\] +.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0, x0, lsl #1\] +.*: e4e04060 st1h \{z0\.d\}, p0, \[x3, x0, lsl #1\] +.*: e4e04060 st1h \{z0\.d\}, p0, \[x3, x0, lsl #1\] +.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp, x0, lsl #1\] +.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp, x0, lsl #1\] +.*: e4e44000 st1h \{z0\.d\}, p0, \[x0, x4, lsl #1\] +.*: e4e44000 st1h \{z0\.d\}, p0, \[x0, x4, lsl #1\] +.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0, x30, lsl #1\] +.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0, x30, lsl #1\] +.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\] +.*: e4e08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\] +.*: e4e08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\] +.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\] +.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\] +.*: e4e08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\] +.*: e4e08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\] +.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\] +.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\] +.*: e4e48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\] +.*: e4e48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\] +.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\] +.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\] +.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\] +.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\] +.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\] +.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\] +.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\] +.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\] +.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\] +.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\] +.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\] +.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\] +.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\] +.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\] +.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\] .*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\] .*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\] .*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\] @@ -29924,14 +29924,14 @@ Disassembly of section .*: .*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\] .*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\] .*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\] -.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e4afe000 st1h \{z0\.h\}, p0, \[x0,#-1,mul vl\] -.*: e4afe000 st1h \{z0\.h\}, p0, \[x0,#-1,mul vl\] +.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e4afe000 st1h \{z0\.h\}, p0, \[x0, #-1, mul vl\] +.*: e4afe000 st1h \{z0\.h\}, p0, \[x0, #-1, mul vl\] .*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\] .*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\] .*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\] @@ -29956,14 +29956,14 @@ Disassembly of section .*: .*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\] .*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\] .*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\] -.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d,#30\] -.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d,#30\] -.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d,#32\] -.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d,#32\] -.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d,#34\] -.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d,#34\] -.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d,#62\] -.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d,#62\] +.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d, #30\] +.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d, #30\] +.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d, #32\] +.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d, #32\] +.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d, #34\] +.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d, #34\] +.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d, #62\] +.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d, #62\] .*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\] .*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\] .*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\] @@ -29995,14 +29995,14 @@ Disassembly of section .*: .*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\] .*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\] .*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\] -.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0,#-1,mul vl\] -.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0,#-1,mul vl\] +.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0, #-1, mul vl\] +.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0, #-1, mul vl\] .*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\] .*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\] .*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\] @@ -30027,14 +30027,14 @@ Disassembly of section .*: .*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\] .*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\] .*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\] -.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s,#30\] -.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s,#30\] -.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s,#32\] -.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s,#32\] -.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s,#34\] -.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s,#34\] -.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s,#62\] -.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s,#62\] +.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s, #30\] +.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s, #30\] +.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s, #32\] +.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s, #32\] +.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s, #34\] +.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s, #34\] +.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s, #62\] +.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s, #62\] .*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\] .*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\] .*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\] @@ -30066,311 +30066,311 @@ Disassembly of section .*: .*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\] .*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\] .*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\] -.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e4efe000 st1h \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e4efe000 st1h \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e5008000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e500801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e500801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e500801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e500801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw\] -.*: e5008800 st1w \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5008800 st1w \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5008800 st1w \{z0\.d\}, p2, \[x0,z0\.d,uxtw\] -.*: e5009c00 st1w \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5009c00 st1w \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5009c00 st1w \{z0\.d\}, p7, \[x0,z0\.d,uxtw\] -.*: e5008060 st1w \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e5008060 st1w \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e5008060 st1w \{z0\.d\}, p0, \[x3,z0\.d,uxtw\] -.*: e50083e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e50083e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e50083e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,uxtw\] -.*: e5048000 st1w \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e5048000 st1w \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e5048000 st1w \{z0\.d\}, p0, \[x0,z4\.d,uxtw\] -.*: e51f8000 st1w \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e51f8000 st1w \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e51f8000 st1w \{z0\.d\}, p0, \[x0,z31\.d,uxtw\] -.*: e500c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw\] -.*: e500c800 st1w \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e500c800 st1w \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e500c800 st1w \{z0\.d\}, p2, \[x0,z0\.d,sxtw\] -.*: e500dc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e500dc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e500dc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,sxtw\] -.*: e500c060 st1w \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e500c060 st1w \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e500c060 st1w \{z0\.d\}, p0, \[x3,z0\.d,sxtw\] -.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,sxtw\] -.*: e504c000 st1w \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e504c000 st1w \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e504c000 st1w \{z0\.d\}, p0, \[x0,z4\.d,sxtw\] -.*: e51fc000 st1w \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e51fc000 st1w \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e51fc000 st1w \{z0\.d\}, p0, \[x0,z31\.d,sxtw\] -.*: e500a000 st1w \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e500a000 st1w \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e500a000 st1w \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e500a000 st1w \{z0\.d\}, p0, \[x0,z0\.d\] -.*: e500a001 st1w \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e500a001 st1w \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e500a001 st1w \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e500a001 st1w \{z1\.d\}, p0, \[x0,z0\.d\] -.*: e500a01f st1w \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e500a01f st1w \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e500a01f st1w \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e500a01f st1w \{z31\.d\}, p0, \[x0,z0\.d\] -.*: e500a800 st1w \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e500a800 st1w \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e500a800 st1w \{z0\.d\}, p2, \[x0,z0\.d\] -.*: e500bc00 st1w \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e500bc00 st1w \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e500bc00 st1w \{z0\.d\}, p7, \[x0,z0\.d\] -.*: e500a060 st1w \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e500a060 st1w \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e500a060 st1w \{z0\.d\}, p0, \[x3,z0\.d\] -.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d\] -.*: e504a000 st1w \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e504a000 st1w \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e504a000 st1w \{z0\.d\}, p0, \[x0,z4\.d\] -.*: e51fa000 st1w \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e51fa000 st1w \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e51fa000 st1w \{z0\.d\}, p0, \[x0,z31\.d\] -.*: e5208000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208000 st1w \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208001 st1w \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e520801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e520801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e520801f st1w \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\] -.*: e5208800 st1w \{z0\.d\}, p2, \[x0,z0\.d,uxtw #2\] -.*: e5208800 st1w \{z0\.d\}, p2, \[x0,z0\.d,uxtw #2\] -.*: e5209c00 st1w \{z0\.d\}, p7, \[x0,z0\.d,uxtw #2\] -.*: e5209c00 st1w \{z0\.d\}, p7, \[x0,z0\.d,uxtw #2\] -.*: e5208060 st1w \{z0\.d\}, p0, \[x3,z0\.d,uxtw #2\] -.*: e5208060 st1w \{z0\.d\}, p0, \[x3,z0\.d,uxtw #2\] -.*: e52083e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,uxtw #2\] -.*: e52083e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,uxtw #2\] -.*: e5248000 st1w \{z0\.d\}, p0, \[x0,z4\.d,uxtw #2\] -.*: e5248000 st1w \{z0\.d\}, p0, \[x0,z4\.d,uxtw #2\] -.*: e53f8000 st1w \{z0\.d\}, p0, \[x0,z31\.d,uxtw #2\] -.*: e53f8000 st1w \{z0\.d\}, p0, \[x0,z31\.d,uxtw #2\] -.*: e520c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c000 st1w \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c001 st1w \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c01f st1w \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\] -.*: e520c800 st1w \{z0\.d\}, p2, \[x0,z0\.d,sxtw #2\] -.*: e520c800 st1w \{z0\.d\}, p2, \[x0,z0\.d,sxtw #2\] -.*: e520dc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,sxtw #2\] -.*: e520dc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,sxtw #2\] -.*: e520c060 st1w \{z0\.d\}, p0, \[x3,z0\.d,sxtw #2\] -.*: e520c060 st1w \{z0\.d\}, p0, \[x3,z0\.d,sxtw #2\] -.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,sxtw #2\] -.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,sxtw #2\] -.*: e524c000 st1w \{z0\.d\}, p0, \[x0,z4\.d,sxtw #2\] -.*: e524c000 st1w \{z0\.d\}, p0, \[x0,z4\.d,sxtw #2\] -.*: e53fc000 st1w \{z0\.d\}, p0, \[x0,z31\.d,sxtw #2\] -.*: e53fc000 st1w \{z0\.d\}, p0, \[x0,z31\.d,sxtw #2\] -.*: e520a000 st1w \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a000 st1w \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a000 st1w \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a001 st1w \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a001 st1w \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a001 st1w \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a01f st1w \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a01f st1w \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a01f st1w \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\] -.*: e520a800 st1w \{z0\.d\}, p2, \[x0,z0\.d,lsl #2\] -.*: e520a800 st1w \{z0\.d\}, p2, \[x0,z0\.d,lsl #2\] -.*: e520bc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,lsl #2\] -.*: e520bc00 st1w \{z0\.d\}, p7, \[x0,z0\.d,lsl #2\] -.*: e520a060 st1w \{z0\.d\}, p0, \[x3,z0\.d,lsl #2\] -.*: e520a060 st1w \{z0\.d\}, p0, \[x3,z0\.d,lsl #2\] -.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,lsl #2\] -.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp,z0\.d,lsl #2\] -.*: e524a000 st1w \{z0\.d\}, p0, \[x0,z4\.d,lsl #2\] -.*: e524a000 st1w \{z0\.d\}, p0, \[x0,z4\.d,lsl #2\] -.*: e53fa000 st1w \{z0\.d\}, p0, \[x0,z31\.d,lsl #2\] -.*: e53fa000 st1w \{z0\.d\}, p0, \[x0,z31\.d,lsl #2\] -.*: e5404000 st1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404000 st1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404000 st1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404001 st1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404001 st1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404001 st1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e540401f st1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e540401f st1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e540401f st1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5404800 st1w \{z0\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5404800 st1w \{z0\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5405c00 st1w \{z0\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5405c00 st1w \{z0\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5404060 st1w \{z0\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5404060 st1w \{z0\.s\}, p0, \[x3,x0,lsl #2\] -.*: e54043e0 st1w \{z0\.s\}, p0, \[sp,x0,lsl #2\] -.*: e54043e0 st1w \{z0\.s\}, p0, \[sp,x0,lsl #2\] -.*: e5444000 st1w \{z0\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5444000 st1w \{z0\.s\}, p0, \[x0,x4,lsl #2\] -.*: e55e4000 st1w \{z0\.s\}, p0, \[x0,x30,lsl #2\] -.*: e55e4000 st1w \{z0\.s\}, p0, \[x0,x30,lsl #2\] -.*: e5408000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e540801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e540801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e540801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e540801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw\] -.*: e5408800 st1w \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e5408800 st1w \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e5408800 st1w \{z0\.s\}, p2, \[x0,z0\.s,uxtw\] -.*: e5409c00 st1w \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e5409c00 st1w \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e5409c00 st1w \{z0\.s\}, p7, \[x0,z0\.s,uxtw\] -.*: e5408060 st1w \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e5408060 st1w \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e5408060 st1w \{z0\.s\}, p0, \[x3,z0\.s,uxtw\] -.*: e54083e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e54083e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e54083e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,uxtw\] -.*: e5448000 st1w \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e5448000 st1w \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e5448000 st1w \{z0\.s\}, p0, \[x0,z4\.s,uxtw\] -.*: e55f8000 st1w \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e55f8000 st1w \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e55f8000 st1w \{z0\.s\}, p0, \[x0,z31\.s,uxtw\] -.*: e540c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw\] -.*: e540c800 st1w \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e540c800 st1w \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e540c800 st1w \{z0\.s\}, p2, \[x0,z0\.s,sxtw\] -.*: e540dc00 st1w \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e540dc00 st1w \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e540dc00 st1w \{z0\.s\}, p7, \[x0,z0\.s,sxtw\] -.*: e540c060 st1w \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e540c060 st1w \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e540c060 st1w \{z0\.s\}, p0, \[x3,z0\.s,sxtw\] -.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,sxtw\] -.*: e544c000 st1w \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e544c000 st1w \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e544c000 st1w \{z0\.s\}, p0, \[x0,z4\.s,sxtw\] -.*: e55fc000 st1w \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e55fc000 st1w \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e55fc000 st1w \{z0\.s\}, p0, \[x0,z31\.s,sxtw\] -.*: e5604000 st1w \{z0\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604000 st1w \{z0\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604000 st1w \{z0\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604001 st1w \{z1\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604001 st1w \{z1\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604001 st1w \{z1\.d\}, p0, \[x0,x0,lsl #2\] -.*: e560401f st1w \{z31\.d\}, p0, \[x0,x0,lsl #2\] -.*: e560401f st1w \{z31\.d\}, p0, \[x0,x0,lsl #2\] -.*: e560401f st1w \{z31\.d\}, p0, \[x0,x0,lsl #2\] -.*: e5604800 st1w \{z0\.d\}, p2, \[x0,x0,lsl #2\] -.*: e5604800 st1w \{z0\.d\}, p2, \[x0,x0,lsl #2\] -.*: e5605c00 st1w \{z0\.d\}, p7, \[x0,x0,lsl #2\] -.*: e5605c00 st1w \{z0\.d\}, p7, \[x0,x0,lsl #2\] -.*: e5604060 st1w \{z0\.d\}, p0, \[x3,x0,lsl #2\] -.*: e5604060 st1w \{z0\.d\}, p0, \[x3,x0,lsl #2\] -.*: e56043e0 st1w \{z0\.d\}, p0, \[sp,x0,lsl #2\] -.*: e56043e0 st1w \{z0\.d\}, p0, \[sp,x0,lsl #2\] -.*: e5644000 st1w \{z0\.d\}, p0, \[x0,x4,lsl #2\] -.*: e5644000 st1w \{z0\.d\}, p0, \[x0,x4,lsl #2\] -.*: e57e4000 st1w \{z0\.d\}, p0, \[x0,x30,lsl #2\] -.*: e57e4000 st1w \{z0\.d\}, p0, \[x0,x30,lsl #2\] -.*: e5608000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608000 st1w \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608001 st1w \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e560801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e560801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e560801f st1w \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\] -.*: e5608800 st1w \{z0\.s\}, p2, \[x0,z0\.s,uxtw #2\] -.*: e5608800 st1w \{z0\.s\}, p2, \[x0,z0\.s,uxtw #2\] -.*: e5609c00 st1w \{z0\.s\}, p7, \[x0,z0\.s,uxtw #2\] -.*: e5609c00 st1w \{z0\.s\}, p7, \[x0,z0\.s,uxtw #2\] -.*: e5608060 st1w \{z0\.s\}, p0, \[x3,z0\.s,uxtw #2\] -.*: e5608060 st1w \{z0\.s\}, p0, \[x3,z0\.s,uxtw #2\] -.*: e56083e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,uxtw #2\] -.*: e56083e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,uxtw #2\] -.*: e5648000 st1w \{z0\.s\}, p0, \[x0,z4\.s,uxtw #2\] -.*: e5648000 st1w \{z0\.s\}, p0, \[x0,z4\.s,uxtw #2\] -.*: e57f8000 st1w \{z0\.s\}, p0, \[x0,z31\.s,uxtw #2\] -.*: e57f8000 st1w \{z0\.s\}, p0, \[x0,z31\.s,uxtw #2\] -.*: e560c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c000 st1w \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c001 st1w \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c01f st1w \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\] -.*: e560c800 st1w \{z0\.s\}, p2, \[x0,z0\.s,sxtw #2\] -.*: e560c800 st1w \{z0\.s\}, p2, \[x0,z0\.s,sxtw #2\] -.*: e560dc00 st1w \{z0\.s\}, p7, \[x0,z0\.s,sxtw #2\] -.*: e560dc00 st1w \{z0\.s\}, p7, \[x0,z0\.s,sxtw #2\] -.*: e560c060 st1w \{z0\.s\}, p0, \[x3,z0\.s,sxtw #2\] -.*: e560c060 st1w \{z0\.s\}, p0, \[x3,z0\.s,sxtw #2\] -.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,sxtw #2\] -.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp,z0\.s,sxtw #2\] -.*: e564c000 st1w \{z0\.s\}, p0, \[x0,z4\.s,sxtw #2\] -.*: e564c000 st1w \{z0\.s\}, p0, \[x0,z4\.s,sxtw #2\] -.*: e57fc000 st1w \{z0\.s\}, p0, \[x0,z31\.s,sxtw #2\] -.*: e57fc000 st1w \{z0\.s\}, p0, \[x0,z31\.s,sxtw #2\] +.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e4efe000 st1h \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e4efe000 st1h \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\] +.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\] +.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\] +.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\] +.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\] +.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\] +.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\] +.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\] +.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\] +.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\] +.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\] +.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\] +.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\] +.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\] +.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\] +.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\] +.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\] +.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\] +.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\] +.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\] +.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\] +.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\] +.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\] +.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\] +.*: e5208800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\] +.*: e5208800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\] +.*: e5209c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\] +.*: e5209c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\] +.*: e5208060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\] +.*: e5208060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\] +.*: e52083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\] +.*: e52083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\] +.*: e5248000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\] +.*: e5248000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\] +.*: e53f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\] +.*: e53f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\] +.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\] +.*: e520c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\] +.*: e520c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\] +.*: e520dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\] +.*: e520dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\] +.*: e520c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\] +.*: e520c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\] +.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\] +.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\] +.*: e524c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\] +.*: e524c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\] +.*: e53fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\] +.*: e53fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\] +.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\] +.*: e520a800 st1w \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\] +.*: e520a800 st1w \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\] +.*: e520bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\] +.*: e520bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\] +.*: e520a060 st1w \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\] +.*: e520a060 st1w \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\] +.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\] +.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\] +.*: e524a000 st1w \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\] +.*: e524a000 st1w \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\] +.*: e53fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\] +.*: e53fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\] +.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5404800 st1w \{z0\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5404800 st1w \{z0\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5405c00 st1w \{z0\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5405c00 st1w \{z0\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5404060 st1w \{z0\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5404060 st1w \{z0\.s\}, p0, \[x3, x0, lsl #2\] +.*: e54043e0 st1w \{z0\.s\}, p0, \[sp, x0, lsl #2\] +.*: e54043e0 st1w \{z0\.s\}, p0, \[sp, x0, lsl #2\] +.*: e5444000 st1w \{z0\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5444000 st1w \{z0\.s\}, p0, \[x0, x4, lsl #2\] +.*: e55e4000 st1w \{z0\.s\}, p0, \[x0, x30, lsl #2\] +.*: e55e4000 st1w \{z0\.s\}, p0, \[x0, x30, lsl #2\] +.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\] +.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\] +.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\] +.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\] +.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\] +.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\] +.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\] +.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\] +.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\] +.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\] +.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\] +.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\] +.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\] +.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\] +.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\] +.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\] +.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\] +.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\] +.*: e5604800 st1w \{z0\.d\}, p2, \[x0, x0, lsl #2\] +.*: e5604800 st1w \{z0\.d\}, p2, \[x0, x0, lsl #2\] +.*: e5605c00 st1w \{z0\.d\}, p7, \[x0, x0, lsl #2\] +.*: e5605c00 st1w \{z0\.d\}, p7, \[x0, x0, lsl #2\] +.*: e5604060 st1w \{z0\.d\}, p0, \[x3, x0, lsl #2\] +.*: e5604060 st1w \{z0\.d\}, p0, \[x3, x0, lsl #2\] +.*: e56043e0 st1w \{z0\.d\}, p0, \[sp, x0, lsl #2\] +.*: e56043e0 st1w \{z0\.d\}, p0, \[sp, x0, lsl #2\] +.*: e5644000 st1w \{z0\.d\}, p0, \[x0, x4, lsl #2\] +.*: e5644000 st1w \{z0\.d\}, p0, \[x0, x4, lsl #2\] +.*: e57e4000 st1w \{z0\.d\}, p0, \[x0, x30, lsl #2\] +.*: e57e4000 st1w \{z0\.d\}, p0, \[x0, x30, lsl #2\] +.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\] +.*: e5608800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\] +.*: e5608800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\] +.*: e5609c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\] +.*: e5609c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\] +.*: e5608060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\] +.*: e5608060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\] +.*: e56083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\] +.*: e56083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\] +.*: e5648000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\] +.*: e5648000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\] +.*: e57f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\] +.*: e57f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\] +.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\] +.*: e560c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\] +.*: e560c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\] +.*: e560dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\] +.*: e560dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\] +.*: e560c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\] +.*: e560c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\] +.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\] +.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\] +.*: e564c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\] +.*: e564c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\] +.*: e57fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\] +.*: e57fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\] .*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\] .*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\] .*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\] @@ -30395,14 +30395,14 @@ Disassembly of section .*: .*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\] .*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\] .*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\] -.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d,#60\] -.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d,#60\] -.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d,#64\] -.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d,#64\] -.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d,#68\] -.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d,#68\] -.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d,#124\] -.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d,#124\] +.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d, #60\] +.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d, #60\] +.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d, #64\] +.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d, #64\] +.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d, #68\] +.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d, #68\] +.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d, #124\] +.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d, #124\] .*: e540e000 st1w \{z0\.s\}, p0, \[x0\] .*: e540e000 st1w \{z0\.s\}, p0, \[x0\] .*: e540e000 st1w \{z0\.s\}, p0, \[x0\] @@ -30434,14 +30434,14 @@ Disassembly of section .*: .*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\] .*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\] .*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\] -.*: e547e000 st1w \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e547e000 st1w \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e548e000 st1w \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e548e000 st1w \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e549e000 st1w \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e549e000 st1w \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e54fe000 st1w \{z0\.s\}, p0, \[x0,#-1,mul vl\] -.*: e54fe000 st1w \{z0\.s\}, p0, \[x0,#-1,mul vl\] +.*: e547e000 st1w \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e547e000 st1w \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e548e000 st1w \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e548e000 st1w \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e549e000 st1w \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e549e000 st1w \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e54fe000 st1w \{z0\.s\}, p0, \[x0, #-1, mul vl\] +.*: e54fe000 st1w \{z0\.s\}, p0, \[x0, #-1, mul vl\] .*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\] .*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\] .*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\] @@ -30466,14 +30466,14 @@ Disassembly of section .*: .*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\] .*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\] .*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\] -.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s,#60\] -.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s,#60\] -.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s,#64\] -.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s,#64\] -.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s,#68\] -.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s,#68\] -.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s,#124\] -.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s,#124\] +.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s, #60\] +.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s, #60\] +.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s, #64\] +.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s, #64\] +.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s, #68\] +.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s, #68\] +.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s, #124\] +.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s, #124\] .*: e560e000 st1w \{z0\.d\}, p0, \[x0\] .*: e560e000 st1w \{z0\.d\}, p0, \[x0\] .*: e560e000 st1w \{z0\.d\}, p0, \[x0\] @@ -30505,57 +30505,57 @@ Disassembly of section .*: .*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\] .*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\] .*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\] -.*: e567e000 st1w \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e567e000 st1w \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e568e000 st1w \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e568e000 st1w \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e569e000 st1w \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e569e000 st1w \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e56fe000 st1w \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e56fe000 st1w \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0,x0\] -.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0,x0\] -.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0,x0\] -.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0,x0\] -.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0,x0\] -.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0,x0\] -.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0,x0\] -.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0,x0\] -.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0,x0\] -.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0,x0\] -.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0,x0\] -.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0,x0\] -.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0,x0\] -.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3,x0\] -.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3,x0\] -.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3,x0\] -.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3,x0\] -.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3,x0\] -.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp,x0\] -.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp,x0\] -.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp,x0\] -.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp,x0\] -.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp,x0\] -.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x4\] -.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x4\] -.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x4\] -.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x4\] -.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x4\] -.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x30\] -.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x30\] -.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x30\] -.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x30\] -.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0,x30\] +.*: e567e000 st1w \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e567e000 st1w \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e568e000 st1w \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e568e000 st1w \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e569e000 st1w \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e569e000 st1w \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e56fe000 st1w \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e56fe000 st1w \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\] +.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\] +.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\] +.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\] +.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\] +.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\] +.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\] +.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\] +.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\] +.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\] +.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\] +.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\] +.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\] +.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\] +.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\] +.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\] +.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\] +.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\] +.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\] +.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\] +.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\] +.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\] +.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\] +.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\] +.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\] +.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\] +.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\] +.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\] +.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\] +.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\] +.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\] +.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\] +.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\] .*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\] .*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\] .*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\] @@ -30602,44 +30602,44 @@ Disassembly of section .*: .*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\] .*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\] .*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\] -.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\] -.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\] -.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\] -.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\] -.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\] -.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\] -.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\] -.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\] -.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\] -.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\] -.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\] -.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\] -.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\] +.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\] +.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\] +.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\] +.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\] +.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\] +.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\] +.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\] +.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\] +.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\] +.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\] +.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\] +.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\] +.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\] .*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\] .*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\] .*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\] @@ -30686,44 +30686,44 @@ Disassembly of section .*: .*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\] .*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\] .*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\] -.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\] -.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\] -.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\] -.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\] -.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\] -.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\] -.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\] -.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\] -.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\] -.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\] -.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\] -.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\] -.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\] +.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\] +.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\] +.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\] +.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\] +.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\] +.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\] +.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\] +.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\] +.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\] +.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\] +.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\] +.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\] +.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\] .*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\] .*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\] .*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\] @@ -30770,44 +30770,44 @@ Disassembly of section .*: .*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\] .*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\] .*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\] -.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\] -.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\] -.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\] -.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\] -.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\] -.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\] -.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\] -.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\] -.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\] -.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\] -.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\] -.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\] -.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\] -.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\] -.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\] -.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\] -.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\] -.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\] -.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\] -.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\] +.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\] +.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\] +.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\] +.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\] +.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\] +.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\] +.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\] +.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\] +.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\] +.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\] +.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\] +.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\] +.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\] +.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\] +.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\] +.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\] +.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\] +.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\] +.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\] +.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\] .*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\] .*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\] .*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\] @@ -30854,61 +30854,61 @@ Disassembly of section .*: .*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\] .*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\] .*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\] -.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\] -.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\] -.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\] -.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\] -.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\] -.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\] -.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\] -.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\] -.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\] -.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\] -.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\] -.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\] -.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x0\] -.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x0\] -.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x0\] -.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x0\] -.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x0\] -.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0,x0\] -.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\] -.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0,x0\] -.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0,x0\] -.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0,x0\] -.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0,x0\] -.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0,x0\] -.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0,x0\] -.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0,x0\] -.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0,x0\] -.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0,x0\] -.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0,x0\] -.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3,x0\] -.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3,x0\] -.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3,x0\] -.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3,x0\] -.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3,x0\] -.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp,x0\] -.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp,x0\] -.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp,x0\] -.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp,x0\] -.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp,x0\] -.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x4\] -.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x4\] -.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x4\] -.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x4\] -.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x4\] -.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x30\] -.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x30\] -.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x30\] -.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x30\] -.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0,x30\] +.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\] +.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\] +.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\] +.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\] +.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\] +.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\] +.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\] +.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\] +.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\] +.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\] +.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\] +.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\] +.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\] +.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\] +.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\] +.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\] +.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\] +.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\] +.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\] +.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\] +.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\] +.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\] +.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\] +.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\] +.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\] +.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\] +.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\] +.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\] +.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\] +.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\] +.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\] +.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\] +.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\] +.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\] +.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\] +.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\] +.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\] +.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\] +.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\] +.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\] +.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\] +.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\] +.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\] +.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\] +.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\] +.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\] +.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\] +.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\] +.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\] .*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\] .*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\] .*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\] @@ -30955,44 +30955,44 @@ Disassembly of section .*: .*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\] .*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\] .*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\] -.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\] -.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\] -.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\] -.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\] -.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\] -.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\] -.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\] -.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\] -.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\] -.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\] -.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\] -.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\] -.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\] +.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\] +.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\] +.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\] +.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\] +.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\] +.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\] +.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\] +.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\] +.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\] +.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\] +.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\] +.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\] +.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\] .*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\] .*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\] .*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\] @@ -31039,44 +31039,44 @@ Disassembly of section .*: .*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\] .*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\] .*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\] -.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\] -.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\] -.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\] -.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\] -.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\] -.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\] -.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\] -.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\] -.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\] -.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\] -.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\] -.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\] -.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\] +.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\] +.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\] +.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\] +.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\] +.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\] +.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\] +.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\] +.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\] +.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\] +.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\] +.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\] +.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\] +.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\] .*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\] .*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\] .*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\] @@ -31123,44 +31123,44 @@ Disassembly of section .*: .*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\] .*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\] .*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\] -.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\] -.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\] -.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\] -.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\] -.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\] -.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\] -.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\] -.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\] -.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\] -.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\] -.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\] -.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\] -.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\] -.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\] -.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\] -.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\] -.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\] -.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\] -.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\] -.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\] +.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\] +.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\] +.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\] +.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\] +.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\] +.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\] +.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\] +.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\] +.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\] +.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\] +.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\] +.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\] +.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\] +.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\] +.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\] +.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\] +.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\] +.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\] +.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\] +.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\] .*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\] .*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\] .*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\] @@ -31207,61 +31207,61 @@ Disassembly of section .*: .*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\] .*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\] .*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\] -.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\] -.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\] -.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\] -.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\] -.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\] -.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\] -.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\] -.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\] -.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\] -.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\] -.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\] -.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\] -.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x0\] -.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0,x0\] -.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0,x0\] -.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0,x0\] -.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0,x0\] -.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0,x0\] -.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\] -.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0,x0\] -.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0,x0\] -.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0,x0\] -.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0,x0\] -.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0,x0\] -.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0,x0\] -.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0,x0\] -.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0,x0\] -.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0,x0\] -.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0,x0\] -.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3,x0\] -.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3,x0\] -.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3,x0\] -.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3,x0\] -.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3,x0\] -.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp,x0\] -.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp,x0\] -.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp,x0\] -.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp,x0\] -.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp,x0\] -.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x4\] -.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x4\] -.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x4\] -.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x4\] -.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x4\] -.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x30\] -.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x30\] -.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x30\] -.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x30\] -.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0,x30\] +.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\] +.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\] +.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\] +.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\] +.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\] +.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\] +.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\] +.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\] +.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\] +.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\] +.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\] +.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\] +.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\] +.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\] +.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\] +.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\] +.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\] +.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\] +.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\] +.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\] +.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\] +.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\] +.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\] +.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\] +.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\] +.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\] +.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\] +.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\] +.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\] +.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\] +.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\] +.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\] +.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\] +.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\] +.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\] +.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\] +.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\] +.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\] +.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\] +.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\] +.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\] +.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\] +.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\] +.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\] +.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\] +.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\] +.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\] +.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\] +.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\] .*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\] .*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\] .*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\] @@ -31308,44 +31308,44 @@ Disassembly of section .*: .*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\] .*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\] .*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\] -.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\] -.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\] -.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\] -.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\] -.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\] -.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\] -.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\] -.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\] -.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\] -.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\] -.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\] -.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\] -.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\] -.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\] +.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\] +.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\] +.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\] +.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\] +.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\] +.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\] +.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\] +.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\] +.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\] +.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\] +.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\] +.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\] +.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\] +.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\] .*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\] .*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\] .*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\] @@ -31392,44 +31392,44 @@ Disassembly of section .*: .*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\] .*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\] .*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\] -.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\] -.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\] -.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\] -.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\] -.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\] -.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\] -.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\] -.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\] -.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\] -.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\] -.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\] -.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\] -.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\] -.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\] +.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\] +.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\] +.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\] +.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\] +.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\] +.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\] +.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\] +.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\] +.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\] +.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\] +.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\] +.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\] +.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\] +.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\] .*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\] .*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\] .*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\] @@ -31476,44 +31476,44 @@ Disassembly of section .*: .*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\] .*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\] .*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\] -.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\] -.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\] -.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\] -.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\] -.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\] -.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\] -.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\] -.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\] -.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\] -.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\] -.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\] -.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\] -.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\] -.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\] -.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\] -.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\] -.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\] -.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\] -.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\] -.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\] -.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\] +.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\] +.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\] +.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\] +.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\] +.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\] +.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\] +.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\] +.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\] +.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\] +.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\] +.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\] +.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\] +.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\] +.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\] +.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\] +.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\] +.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\] +.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\] +.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\] +.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\] +.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\] .*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\] .*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\] .*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\] @@ -31560,48 +31560,48 @@ Disassembly of section .*: .*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\] .*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\] .*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\] -.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\] -.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\] -.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\] -.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\] -.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\] -.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\] -.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\] -.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\] -.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\] -.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\] -.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\] -.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\] -.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0,x0\] -.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0,x0\] -.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0,x0\] -.*: e400601f stnt1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400601f stnt1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400601f stnt1b \{z31\.b\}, p0, \[x0,x0\] -.*: e400601f stnt1b \{z31\.b\}, p0, \[x0,x0\] -.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0,x0\] -.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0,x0\] -.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3,x0\] -.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3,x0\] -.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3,x0\] -.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp,x0\] -.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp,x0\] -.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp,x0\] -.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0,x4\] -.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0,x4\] -.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0,x4\] -.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0,x30\] -.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0,x30\] -.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0,x30\] +.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\] +.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\] +.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\] +.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\] +.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\] +.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\] +.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\] +.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\] +.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\] +.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\] +.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\] +.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\] +.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\] +.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\] +.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\] +.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\] +.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\] +.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\] +.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\] +.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\] +.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\] +.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\] +.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\] +.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\] +.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\] +.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\] +.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\] +.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\] +.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\] +.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\] +.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\] .*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\] .*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\] .*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\] @@ -31633,35 +31633,35 @@ Disassembly of section .*: .*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\] .*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\] .*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\] -.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0,#7,mul vl\] -.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0,#7,mul vl\] -.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0,#-8,mul vl\] -.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0,#-8,mul vl\] -.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0,#-7,mul vl\] -.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0,#-7,mul vl\] -.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0,#-1,mul vl\] -.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0,#-1,mul vl\] -.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0,x0,lsl #3\] -.*: e580601f stnt1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e580601f stnt1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e580601f stnt1d \{z31\.d\}, p0, \[x0,x0,lsl #3\] -.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0,x0,lsl #3\] -.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0,x0,lsl #3\] -.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3,x0,lsl #3\] -.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3,x0,lsl #3\] -.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp,x0,lsl #3\] -.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp,x0,lsl #3\] -.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0,x4,lsl #3\] -.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0,x4,lsl #3\] -.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0,x30,lsl #3\] -.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0,x30,lsl #3\] +.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0, #7, mul vl\] +.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0, #7, mul vl\] +.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0, #-8, mul vl\] +.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0, #-8, mul vl\] +.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0, #-7, mul vl\] +.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0, #-7, mul vl\] +.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0, #-1, mul vl\] +.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0, #-1, mul vl\] +.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\] +.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\] +.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0, x0, lsl #3\] +.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0, x0, lsl #3\] +.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3, x0, lsl #3\] +.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3, x0, lsl #3\] +.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp, x0, lsl #3\] +.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp, x0, lsl #3\] +.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0, x4, lsl #3\] +.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0, x4, lsl #3\] +.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0, x30, lsl #3\] +.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0, x30, lsl #3\] .*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\] .*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\] .*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\] @@ -31693,35 +31693,35 @@ Disassembly of section .*: .*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\] .*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\] .*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\] -.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0,#7,mul vl\] -.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0,#-8,mul vl\] -.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0,#-7,mul vl\] -.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0,#-1,mul vl\] -.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0,x0,lsl #1\] -.*: e480601f stnt1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e480601f stnt1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e480601f stnt1h \{z31\.h\}, p0, \[x0,x0,lsl #1\] -.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0,x0,lsl #1\] -.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0,x0,lsl #1\] -.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3,x0,lsl #1\] -.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3,x0,lsl #1\] -.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp,x0,lsl #1\] -.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp,x0,lsl #1\] -.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0,x4,lsl #1\] -.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0,x4,lsl #1\] -.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0,x30,lsl #1\] -.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0,x30,lsl #1\] +.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0, #7, mul vl\] +.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0, #-8, mul vl\] +.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0, #-7, mul vl\] +.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0, #-1, mul vl\] +.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\] +.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\] +.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0, x0, lsl #1\] +.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0, x0, lsl #1\] +.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3, x0, lsl #1\] +.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3, x0, lsl #1\] +.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp, x0, lsl #1\] +.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp, x0, lsl #1\] +.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0, x4, lsl #1\] +.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0, x4, lsl #1\] +.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0, x30, lsl #1\] +.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0, x30, lsl #1\] .*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\] .*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\] .*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\] @@ -31753,35 +31753,35 @@ Disassembly of section .*: .*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\] .*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\] .*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\] -.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0,#7,mul vl\] -.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0,#-8,mul vl\] -.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0,#-7,mul vl\] -.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0,#-1,mul vl\] -.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0,#-1,mul vl\] -.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0,x0,lsl #2\] -.*: e500601f stnt1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e500601f stnt1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e500601f stnt1w \{z31\.s\}, p0, \[x0,x0,lsl #2\] -.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0,x0,lsl #2\] -.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0,x0,lsl #2\] -.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3,x0,lsl #2\] -.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3,x0,lsl #2\] -.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp,x0,lsl #2\] -.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp,x0,lsl #2\] -.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0,x4,lsl #2\] -.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0,x4,lsl #2\] -.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0,x30,lsl #2\] -.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0,x30,lsl #2\] +.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0, #7, mul vl\] +.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0, #-8, mul vl\] +.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0, #-7, mul vl\] +.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0, #-1, mul vl\] +.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0, #-1, mul vl\] +.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\] +.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\] +.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0, x0, lsl #2\] +.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0, x0, lsl #2\] +.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3, x0, lsl #2\] +.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3, x0, lsl #2\] +.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp, x0, lsl #2\] +.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp, x0, lsl #2\] +.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0, x4, lsl #2\] +.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0, x4, lsl #2\] +.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0, x30, lsl #2\] +.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0, x30, lsl #2\] .*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\] .*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\] .*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\] @@ -31813,14 +31813,14 @@ Disassembly of section .*: .*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\] .*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\] .*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\] -.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0,#7,mul vl\] -.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0,#-8,mul vl\] -.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0,#-7,mul vl\] -.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0,#-1,mul vl\] -.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0,#-1,mul vl\] +.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0, #7, mul vl\] +.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0, #-8, mul vl\] +.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0, #-7, mul vl\] +.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0, #-1, mul vl\] +.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0, #-1, mul vl\] .*: e5800000 str p0, \[x0\] .*: e5800000 str p0, \[x0\] .*: e5800000 str p0, \[x0\] @@ -31841,14 +31841,14 @@ Disassembly of section .*: .*: e58003e0 str p0, \[sp\] .*: e58003e0 str p0, \[sp\] .*: e58003e0 str p0, \[sp\] -.*: e59f1c00 str p0, \[x0,#255,mul vl\] -.*: e59f1c00 str p0, \[x0,#255,mul vl\] -.*: e5a00000 str p0, \[x0,#-256,mul vl\] -.*: e5a00000 str p0, \[x0,#-256,mul vl\] -.*: e5a00400 str p0, \[x0,#-255,mul vl\] -.*: e5a00400 str p0, \[x0,#-255,mul vl\] -.*: e5bf1c00 str p0, \[x0,#-1,mul vl\] -.*: e5bf1c00 str p0, \[x0,#-1,mul vl\] +.*: e59f1c00 str p0, \[x0, #255, mul vl\] +.*: e59f1c00 str p0, \[x0, #255, mul vl\] +.*: e5a00000 str p0, \[x0, #-256, mul vl\] +.*: e5a00000 str p0, \[x0, #-256, mul vl\] +.*: e5a00400 str p0, \[x0, #-255, mul vl\] +.*: e5a00400 str p0, \[x0, #-255, mul vl\] +.*: e5bf1c00 str p0, \[x0, #-1, mul vl\] +.*: e5bf1c00 str p0, \[x0, #-1, mul vl\] .*: e5804000 str z0, \[x0\] .*: e5804000 str z0, \[x0\] .*: e5804000 str z0, \[x0\] @@ -31869,14 +31869,14 @@ Disassembly of section .*: .*: e58043e0 str z0, \[sp\] .*: e58043e0 str z0, \[sp\] .*: e58043e0 str z0, \[sp\] -.*: e59f5c00 str z0, \[x0,#255,mul vl\] -.*: e59f5c00 str z0, \[x0,#255,mul vl\] -.*: e5a04000 str z0, \[x0,#-256,mul vl\] -.*: e5a04000 str z0, \[x0,#-256,mul vl\] -.*: e5a04400 str z0, \[x0,#-255,mul vl\] -.*: e5a04400 str z0, \[x0,#-255,mul vl\] -.*: e5bf5c00 str z0, \[x0,#-1,mul vl\] -.*: e5bf5c00 str z0, \[x0,#-1,mul vl\] +.*: e59f5c00 str z0, \[x0, #255, mul vl\] +.*: e59f5c00 str z0, \[x0, #255, mul vl\] +.*: e5a04000 str z0, \[x0, #-256, mul vl\] +.*: e5a04000 str z0, \[x0, #-256, mul vl\] +.*: e5a04400 str z0, \[x0, #-255, mul vl\] +.*: e5a04400 str z0, \[x0, #-255, mul vl\] +.*: e5bf5c00 str z0, \[x0, #-1, mul vl\] +.*: e5bf5c00 str z0, \[x0, #-1, mul vl\] .*: 04200400 sub z0\.b, z0\.b, z0\.b .*: 04200400 sub z0\.b, z0\.b, z0\.b .*: 04200401 sub z1\.b, z0\.b, z0\.b diff --git a/gas/testsuite/gas/aarch64/symbol.d b/gas/testsuite/gas/aarch64/symbol.d index 3d8b480d4ac..6afb03bd600 100644 --- a/gas/testsuite/gas/aarch64/symbol.d +++ b/gas/testsuite/gas/aarch64/symbol.d @@ -5,10 +5,10 @@ Disassembly of section \.text: 0000000000000000 <.*>: - 0: b9400401 ldr w1, \[x0,#4\] - 4: b9400401 ldr w1, \[x0,#4\] - 8: b9401001 ldr w1, \[x0,#16\] - c: b9401001 ldr w1, \[x0,#16\] + 0: b9400401 ldr w1, \[x0, #4\] + 4: b9400401 ldr w1, \[x0, #4\] + 8: b9401001 ldr w1, \[x0, #16\] + c: b9401001 ldr w1, \[x0, #16\] 10: 8b020020 add x0, x1, x2 14: 91002820 add x0, x1, #0xa 18: d1002c20 sub x0, x1, #0xb diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d index 2da13eea9e1..2cfcdb5fd0f 100644 --- a/gas/testsuite/gas/aarch64/system.d +++ b/gas/testsuite/gas/aarch64/system.d @@ -192,179 +192,179 @@ Disassembly of section \.text: 2e0: d5033fdf isb 2e4: d8000000 prfm pldl1keep, 0 <LABEL1> 2e4: R_AARCH64_LD_PREL_LO19 LABEL1 - 2e8: f8af6be0 prfm pldl1keep, \[sp,x15\] - 2ec: f8be58e0 prfm pldl1keep, \[x7,w30,uxtw #3\] - 2f0: f9800c60 prfm pldl1keep, \[x3,#24\] + 2e8: f8af6be0 prfm pldl1keep, \[sp, x15\] + 2ec: f8be58e0 prfm pldl1keep, \[x7, w30, uxtw #3\] + 2f0: f9800c60 prfm pldl1keep, \[x3, #24\] 2f4: d8000001 prfm pldl1strm, 0 <LABEL1> 2f4: R_AARCH64_LD_PREL_LO19 LABEL1 - 2f8: f8af6be1 prfm pldl1strm, \[sp,x15\] - 2fc: f8be58e1 prfm pldl1strm, \[x7,w30,uxtw #3\] - 300: f9800c61 prfm pldl1strm, \[x3,#24\] + 2f8: f8af6be1 prfm pldl1strm, \[sp, x15\] + 2fc: f8be58e1 prfm pldl1strm, \[x7, w30, uxtw #3\] + 300: f9800c61 prfm pldl1strm, \[x3, #24\] 304: d8000002 prfm pldl2keep, 0 <LABEL1> 304: R_AARCH64_LD_PREL_LO19 LABEL1 - 308: f8af6be2 prfm pldl2keep, \[sp,x15\] - 30c: f8be58e2 prfm pldl2keep, \[x7,w30,uxtw #3\] - 310: f9800c62 prfm pldl2keep, \[x3,#24\] + 308: f8af6be2 prfm pldl2keep, \[sp, x15\] + 30c: f8be58e2 prfm pldl2keep, \[x7, w30, uxtw #3\] + 310: f9800c62 prfm pldl2keep, \[x3, #24\] 314: d8000003 prfm pldl2strm, 0 <LABEL1> 314: R_AARCH64_LD_PREL_LO19 LABEL1 - 318: f8af6be3 prfm pldl2strm, \[sp,x15\] - 31c: f8be58e3 prfm pldl2strm, \[x7,w30,uxtw #3\] - 320: f9800c63 prfm pldl2strm, \[x3,#24\] + 318: f8af6be3 prfm pldl2strm, \[sp, x15\] + 31c: f8be58e3 prfm pldl2strm, \[x7, w30, uxtw #3\] + 320: f9800c63 prfm pldl2strm, \[x3, #24\] 324: d8000004 prfm pldl3keep, 0 <LABEL1> 324: R_AARCH64_LD_PREL_LO19 LABEL1 - 328: f8af6be4 prfm pldl3keep, \[sp,x15\] - 32c: f8be58e4 prfm pldl3keep, \[x7,w30,uxtw #3\] - 330: f9800c64 prfm pldl3keep, \[x3,#24\] + 328: f8af6be4 prfm pldl3keep, \[sp, x15\] + 32c: f8be58e4 prfm pldl3keep, \[x7, w30, uxtw #3\] + 330: f9800c64 prfm pldl3keep, \[x3, #24\] 334: d8000005 prfm pldl3strm, 0 <LABEL1> 334: R_AARCH64_LD_PREL_LO19 LABEL1 - 338: f8af6be5 prfm pldl3strm, \[sp,x15\] - 33c: f8be58e5 prfm pldl3strm, \[x7,w30,uxtw #3\] - 340: f9800c65 prfm pldl3strm, \[x3,#24\] + 338: f8af6be5 prfm pldl3strm, \[sp, x15\] + 33c: f8be58e5 prfm pldl3strm, \[x7, w30, uxtw #3\] + 340: f9800c65 prfm pldl3strm, \[x3, #24\] 344: d8000006 prfm #0x06, 0 <LABEL1> 344: R_AARCH64_LD_PREL_LO19 LABEL1 - 348: f8af6be6 prfm #0x06, \[sp,x15\] - 34c: f8be58e6 prfm #0x06, \[x7,w30,uxtw #3\] - 350: f9800c66 prfm #0x06, \[x3,#24\] + 348: f8af6be6 prfm #0x06, \[sp, x15\] + 34c: f8be58e6 prfm #0x06, \[x7, w30, uxtw #3\] + 350: f9800c66 prfm #0x06, \[x3, #24\] 354: d8000007 prfm #0x07, 0 <LABEL1> 354: R_AARCH64_LD_PREL_LO19 LABEL1 - 358: f8af6be7 prfm #0x07, \[sp,x15\] - 35c: f8be58e7 prfm #0x07, \[x7,w30,uxtw #3\] - 360: f9800c67 prfm #0x07, \[x3,#24\] + 358: f8af6be7 prfm #0x07, \[sp, x15\] + 35c: f8be58e7 prfm #0x07, \[x7, w30, uxtw #3\] + 360: f9800c67 prfm #0x07, \[x3, #24\] 364: d8000008 prfm plil1keep, 0 <LABEL1> 364: R_AARCH64_LD_PREL_LO19 LABEL1 - 368: f8af6be8 prfm plil1keep, \[sp,x15\] - 36c: f8be58e8 prfm plil1keep, \[x7,w30,uxtw #3\] - 370: f9800c68 prfm plil1keep, \[x3,#24\] + 368: f8af6be8 prfm plil1keep, \[sp, x15\] + 36c: f8be58e8 prfm plil1keep, \[x7, w30, uxtw #3\] + 370: f9800c68 prfm plil1keep, \[x3, #24\] 374: d8000009 prfm plil1strm, 0 <LABEL1> 374: R_AARCH64_LD_PREL_LO19 LABEL1 - 378: f8af6be9 prfm plil1strm, \[sp,x15\] - 37c: f8be58e9 prfm plil1strm, \[x7,w30,uxtw #3\] - 380: f9800c69 prfm plil1strm, \[x3,#24\] + 378: f8af6be9 prfm plil1strm, \[sp, x15\] + 37c: f8be58e9 prfm plil1strm, \[x7, w30, uxtw #3\] + 380: f9800c69 prfm plil1strm, \[x3, #24\] 384: d800000a prfm plil2keep, 0 <LABEL1> 384: R_AARCH64_LD_PREL_LO19 LABEL1 - 388: f8af6bea prfm plil2keep, \[sp,x15\] - 38c: f8be58ea prfm plil2keep, \[x7,w30,uxtw #3\] - 390: f9800c6a prfm plil2keep, \[x3,#24\] + 388: f8af6bea prfm plil2keep, \[sp, x15\] + 38c: f8be58ea prfm plil2keep, \[x7, w30, uxtw #3\] + 390: f9800c6a prfm plil2keep, \[x3, #24\] 394: d800000b prfm plil2strm, 0 <LABEL1> 394: R_AARCH64_LD_PREL_LO19 LABEL1 - 398: f8af6beb prfm plil2strm, \[sp,x15\] - 39c: f8be58eb prfm plil2strm, \[x7,w30,uxtw #3\] - 3a0: f9800c6b prfm plil2strm, \[x3,#24\] + 398: f8af6beb prfm plil2strm, \[sp, x15\] + 39c: f8be58eb prfm plil2strm, \[x7, w30, uxtw #3\] + 3a0: f9800c6b prfm plil2strm, \[x3, #24\] 3a4: d800000c prfm plil3keep, 0 <LABEL1> 3a4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3a8: f8af6bec prfm plil3keep, \[sp,x15\] - 3ac: f8be58ec prfm plil3keep, \[x7,w30,uxtw #3\] - 3b0: f9800c6c prfm plil3keep, \[x3,#24\] + 3a8: f8af6bec prfm plil3keep, \[sp, x15\] + 3ac: f8be58ec prfm plil3keep, \[x7, w30, uxtw #3\] + 3b0: f9800c6c prfm plil3keep, \[x3, #24\] 3b4: d800000d prfm plil3strm, 0 <LABEL1> 3b4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3b8: f8af6bed prfm plil3strm, \[sp,x15\] - 3bc: f8be58ed prfm plil3strm, \[x7,w30,uxtw #3\] - 3c0: f9800c6d prfm plil3strm, \[x3,#24\] + 3b8: f8af6bed prfm plil3strm, \[sp, x15\] + 3bc: f8be58ed prfm plil3strm, \[x7, w30, uxtw #3\] + 3c0: f9800c6d prfm plil3strm, \[x3, #24\] 3c4: d800000e prfm #0x0e, 0 <LABEL1> 3c4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3c8: f8af6bee prfm #0x0e, \[sp,x15\] - 3cc: f8be58ee prfm #0x0e, \[x7,w30,uxtw #3\] - 3d0: f9800c6e prfm #0x0e, \[x3,#24\] + 3c8: f8af6bee prfm #0x0e, \[sp, x15\] + 3cc: f8be58ee prfm #0x0e, \[x7, w30, uxtw #3\] + 3d0: f9800c6e prfm #0x0e, \[x3, #24\] 3d4: d800000f prfm #0x0f, 0 <LABEL1> 3d4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3d8: f8af6bef prfm #0x0f, \[sp,x15\] - 3dc: f8be58ef prfm #0x0f, \[x7,w30,uxtw #3\] - 3e0: f9800c6f prfm #0x0f, \[x3,#24\] + 3d8: f8af6bef prfm #0x0f, \[sp, x15\] + 3dc: f8be58ef prfm #0x0f, \[x7, w30, uxtw #3\] + 3e0: f9800c6f prfm #0x0f, \[x3, #24\] 3e4: d8000010 prfm pstl1keep, 0 <LABEL1> 3e4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3e8: f8af6bf0 prfm pstl1keep, \[sp,x15\] - 3ec: f8be58f0 prfm pstl1keep, \[x7,w30,uxtw #3\] - 3f0: f9800c70 prfm pstl1keep, \[x3,#24\] + 3e8: f8af6bf0 prfm pstl1keep, \[sp, x15\] + 3ec: f8be58f0 prfm pstl1keep, \[x7, w30, uxtw #3\] + 3f0: f9800c70 prfm pstl1keep, \[x3, #24\] 3f4: d8000011 prfm pstl1strm, 0 <LABEL1> 3f4: R_AARCH64_LD_PREL_LO19 LABEL1 - 3f8: f8af6bf1 prfm pstl1strm, \[sp,x15\] - 3fc: f8be58f1 prfm pstl1strm, \[x7,w30,uxtw #3\] - 400: f9800c71 prfm pstl1strm, \[x3,#24\] + 3f8: f8af6bf1 prfm pstl1strm, \[sp, x15\] + 3fc: f8be58f1 prfm pstl1strm, \[x7, w30, uxtw #3\] + 400: f9800c71 prfm pstl1strm, \[x3, #24\] 404: d8000012 prfm pstl2keep, 0 <LABEL1> 404: R_AARCH64_LD_PREL_LO19 LABEL1 - 408: f8af6bf2 prfm pstl2keep, \[sp,x15\] - 40c: f8be58f2 prfm pstl2keep, \[x7,w30,uxtw #3\] - 410: f9800c72 prfm pstl2keep, \[x3,#24\] + 408: f8af6bf2 prfm pstl2keep, \[sp, x15\] + 40c: f8be58f2 prfm pstl2keep, \[x7, w30, uxtw #3\] + 410: f9800c72 prfm pstl2keep, \[x3, #24\] 414: d8000013 prfm pstl2strm, 0 <LABEL1> 414: R_AARCH64_LD_PREL_LO19 LABEL1 - 418: f8af6bf3 prfm pstl2strm, \[sp,x15\] - 41c: f8be58f3 prfm pstl2strm, \[x7,w30,uxtw #3\] - 420: f9800c73 prfm pstl2strm, \[x3,#24\] + 418: f8af6bf3 prfm pstl2strm, \[sp, x15\] + 41c: f8be58f3 prfm pstl2strm, \[x7, w30, uxtw #3\] + 420: f9800c73 prfm pstl2strm, \[x3, #24\] 424: d8000014 prfm pstl3keep, 0 <LABEL1> 424: R_AARCH64_LD_PREL_LO19 LABEL1 - 428: f8af6bf4 prfm pstl3keep, \[sp,x15\] - 42c: f8be58f4 prfm pstl3keep, \[x7,w30,uxtw #3\] - 430: f9800c74 prfm pstl3keep, \[x3,#24\] + 428: f8af6bf4 prfm pstl3keep, \[sp, x15\] + 42c: f8be58f4 prfm pstl3keep, \[x7, w30, uxtw #3\] + 430: f9800c74 prfm pstl3keep, \[x3, #24\] 434: d8000015 prfm pstl3strm, 0 <LABEL1> 434: R_AARCH64_LD_PREL_LO19 LABEL1 - 438: f8af6bf5 prfm pstl3strm, \[sp,x15\] - 43c: f8be58f5 prfm pstl3strm, \[x7,w30,uxtw #3\] - 440: f9800c75 prfm pstl3strm, \[x3,#24\] + 438: f8af6bf5 prfm pstl3strm, \[sp, x15\] + 43c: f8be58f5 prfm pstl3strm, \[x7, w30, uxtw #3\] + 440: f9800c75 prfm pstl3strm, \[x3, #24\] 444: d8000016 prfm #0x16, 0 <LABEL1> 444: R_AARCH64_LD_PREL_LO19 LABEL1 - 448: f8af6bf6 prfm #0x16, \[sp,x15\] - 44c: f8be58f6 prfm #0x16, \[x7,w30,uxtw #3\] - 450: f9800c76 prfm #0x16, \[x3,#24\] + 448: f8af6bf6 prfm #0x16, \[sp, x15\] + 44c: f8be58f6 prfm #0x16, \[x7, w30, uxtw #3\] + 450: f9800c76 prfm #0x16, \[x3, #24\] 454: d8000017 prfm #0x17, 0 <LABEL1> 454: R_AARCH64_LD_PREL_LO19 LABEL1 - 458: f8af6bf7 prfm #0x17, \[sp,x15\] - 45c: f8be58f7 prfm #0x17, \[x7,w30,uxtw #3\] - 460: f9800c77 prfm #0x17, \[x3,#24\] + 458: f8af6bf7 prfm #0x17, \[sp, x15\] + 45c: f8be58f7 prfm #0x17, \[x7, w30, uxtw #3\] + 460: f9800c77 prfm #0x17, \[x3, #24\] 464: d8000018 prfm #0x18, 0 <LABEL1> 464: R_AARCH64_LD_PREL_LO19 LABEL1 - 468: f8af6bf8 prfm #0x18, \[sp,x15\] - 46c: f8be58f8 prfm #0x18, \[x7,w30,uxtw #3\] - 470: f9800c78 prfm #0x18, \[x3,#24\] + 468: f8af6bf8 prfm #0x18, \[sp, x15\] + 46c: f8be58f8 prfm #0x18, \[x7, w30, uxtw #3\] + 470: f9800c78 prfm #0x18, \[x3, #24\] 474: d8000019 prfm #0x19, 0 <LABEL1> 474: R_AARCH64_LD_PREL_LO19 LABEL1 - 478: f8af6bf9 prfm #0x19, \[sp,x15\] - 47c: f8be58f9 prfm #0x19, \[x7,w30,uxtw #3\] - 480: f9800c79 prfm #0x19, \[x3,#24\] + 478: f8af6bf9 prfm #0x19, \[sp, x15\] + 47c: f8be58f9 prfm #0x19, \[x7, w30, uxtw #3\] + 480: f9800c79 prfm #0x19, \[x3, #24\] 484: d800001a prfm #0x1a, 0 <LABEL1> 484: R_AARCH64_LD_PREL_LO19 LABEL1 - 488: f8af6bfa prfm #0x1a, \[sp,x15\] - 48c: f8be58fa prfm #0x1a, \[x7,w30,uxtw #3\] - 490: f9800c7a prfm #0x1a, \[x3,#24\] + 488: f8af6bfa prfm #0x1a, \[sp, x15\] + 48c: f8be58fa prfm #0x1a, \[x7, w30, uxtw #3\] + 490: f9800c7a prfm #0x1a, \[x3, #24\] 494: d800001b prfm #0x1b, 0 <LABEL1> 494: R_AARCH64_LD_PREL_LO19 LABEL1 - 498: f8af6bfb prfm #0x1b, \[sp,x15\] - 49c: f8be58fb prfm #0x1b, \[x7,w30,uxtw #3\] - 4a0: f9800c7b prfm #0x1b, \[x3,#24\] + 498: f8af6bfb prfm #0x1b, \[sp, x15\] + 49c: f8be58fb prfm #0x1b, \[x7, w30, uxtw #3\] + 4a0: f9800c7b prfm #0x1b, \[x3, #24\] 4a4: d800001c prfm #0x1c, 0 <LABEL1> 4a4: R_AARCH64_LD_PREL_LO19 LABEL1 - 4a8: f8af6bfc prfm #0x1c, \[sp,x15\] - 4ac: f8be58fc prfm #0x1c, \[x7,w30,uxtw #3\] - 4b0: f9800c7c prfm #0x1c, \[x3,#24\] + 4a8: f8af6bfc prfm #0x1c, \[sp, x15\] + 4ac: f8be58fc prfm #0x1c, \[x7, w30, uxtw #3\] + 4b0: f9800c7c prfm #0x1c, \[x3, #24\] 4b4: d800001d prfm #0x1d, 0 <LABEL1> 4b4: R_AARCH64_LD_PREL_LO19 LABEL1 - 4b8: f8af6bfd prfm #0x1d, \[sp,x15\] - 4bc: f8be58fd prfm #0x1d, \[x7,w30,uxtw #3\] - 4c0: f9800c7d prfm #0x1d, \[x3,#24\] + 4b8: f8af6bfd prfm #0x1d, \[sp, x15\] + 4bc: f8be58fd prfm #0x1d, \[x7, w30, uxtw #3\] + 4c0: f9800c7d prfm #0x1d, \[x3, #24\] 4c4: d800001e prfm #0x1e, 0 <LABEL1> 4c4: R_AARCH64_LD_PREL_LO19 LABEL1 - 4c8: f8af6bfe prfm #0x1e, \[sp,x15\] - 4cc: f8be58fe prfm #0x1e, \[x7,w30,uxtw #3\] - 4d0: f9800c7e prfm #0x1e, \[x3,#24\] + 4c8: f8af6bfe prfm #0x1e, \[sp, x15\] + 4cc: f8be58fe prfm #0x1e, \[x7, w30, uxtw #3\] + 4d0: f9800c7e prfm #0x1e, \[x3, #24\] 4d4: d800001f prfm #0x1f, 0 <LABEL1> 4d4: R_AARCH64_LD_PREL_LO19 LABEL1 - 4d8: f8af6bff prfm #0x1f, \[sp,x15\] - 4dc: f8be58ff prfm #0x1f, \[x7,w30,uxtw #3\] - 4e0: f9800c7f prfm #0x1f, \[x3,#24\] - 4e4: f9800c60 prfm pldl1keep, \[x3,#24\] - 4e8: f9800c61 prfm pldl1strm, \[x3,#24\] - 4ec: f9800c62 prfm pldl2keep, \[x3,#24\] - 4f0: f9800c63 prfm pldl2strm, \[x3,#24\] - 4f4: f9800c64 prfm pldl3keep, \[x3,#24\] - 4f8: f9800c65 prfm pldl3strm, \[x3,#24\] - 4fc: f9800c68 prfm plil1keep, \[x3,#24\] - 500: f9800c69 prfm plil1strm, \[x3,#24\] - 504: f9800c6a prfm plil2keep, \[x3,#24\] - 508: f9800c6b prfm plil2strm, \[x3,#24\] - 50c: f9800c6c prfm plil3keep, \[x3,#24\] - 510: f9800c6d prfm plil3strm, \[x3,#24\] - 514: f9800c70 prfm pstl1keep, \[x3,#24\] - 518: f9800c71 prfm pstl1strm, \[x3,#24\] - 51c: f9800c72 prfm pstl2keep, \[x3,#24\] - 520: f9800c73 prfm pstl2strm, \[x3,#24\] - 524: f9800c74 prfm pstl3keep, \[x3,#24\] - 528: f9800c75 prfm pstl3strm, \[x3,#24\] + 4d8: f8af6bff prfm #0x1f, \[sp, x15\] + 4dc: f8be58ff prfm #0x1f, \[x7, w30, uxtw #3\] + 4e0: f9800c7f prfm #0x1f, \[x3, #24\] + 4e4: f9800c60 prfm pldl1keep, \[x3, #24\] + 4e8: f9800c61 prfm pldl1strm, \[x3, #24\] + 4ec: f9800c62 prfm pldl2keep, \[x3, #24\] + 4f0: f9800c63 prfm pldl2strm, \[x3, #24\] + 4f4: f9800c64 prfm pldl3keep, \[x3, #24\] + 4f8: f9800c65 prfm pldl3strm, \[x3, #24\] + 4fc: f9800c68 prfm plil1keep, \[x3, #24\] + 500: f9800c69 prfm plil1strm, \[x3, #24\] + 504: f9800c6a prfm plil2keep, \[x3, #24\] + 508: f9800c6b prfm plil2strm, \[x3, #24\] + 50c: f9800c6c prfm plil3keep, \[x3, #24\] + 510: f9800c6d prfm plil3strm, \[x3, #24\] + 514: f9800c70 prfm pstl1keep, \[x3, #24\] + 518: f9800c71 prfm pstl1strm, \[x3, #24\] + 51c: f9800c72 prfm pstl2keep, \[x3, #24\] + 520: f9800c73 prfm pstl2strm, \[x3, #24\] + 524: f9800c74 prfm pstl3keep, \[x3, #24\] + 528: f9800c75 prfm pstl3strm, \[x3, #24\] diff --git a/gas/testsuite/gas/aarch64/tls-desc.d b/gas/testsuite/gas/aarch64/tls-desc.d index 751e7970692..378fcb54317 100644 --- a/gas/testsuite/gas/aarch64/tls-desc.d +++ b/gas/testsuite/gas/aarch64/tls-desc.d @@ -9,7 +9,7 @@ Disassembly of section \.text: 0: R_AARCH64_TLSDESC_OFF_G1 var 4: f2800000 movk x0, #0x0 4: R_AARCH64_TLSDESC_OFF_G0_NC var - 8: f8606a41 ldr x1, \[x18,x0\] + 8: f8606a41 ldr x1, \[x18, x0\] 8: R_AARCH64_TLSDESC_LDR var c: 8b000240 add x0, x18, x0 c: R_AARCH64_TLSDESC_ADD var diff --git a/gas/testsuite/gas/aarch64/verbose-error.l b/gas/testsuite/gas/aarch64/verbose-error.l index 314a5cc6db8..5696a5c4671 100644 --- a/gas/testsuite/gas/aarch64/verbose-error.l +++ b/gas/testsuite/gas/aarch64/verbose-error.l @@ -2,9 +2,9 @@ [^:]*:4: Error: missing shift amount at operand 2 -- `strb w7,\[x30,x0,lsl\]' [^:]*:5: Error: operand mismatch -- `ubfm w0,x1,8,31' [^:]*:5: Info: did you mean this\? -[^:]*:5: Info: ubfm w0,w1,#8,#31 +[^:]*:5: Info: ubfm w0, w1, #8, #31 [^:]*:5: Info: other valid variant\(s\): -[^:]*:5: Info: ubfm x0,x1,#8,#31 +[^:]*:5: Info: ubfm x0, x1, #8, #31 [^:]*:6: Error: immediate value out of range 0 to 31 at operand 4 -- `bfm w0,w1,8,43' [^:]*:7: Error: invalid shift amount at operand 2 -- `strb w7,\[x30,x0,lsl#1\]' [^:]*:8: Error: invalid addressing mode at operand 2 -- `st2 {v4.2d,v5.2d},\[x3,#3\]' @@ -13,164 +13,164 @@ [^:]*:11: Error: missing immediate expression at operand 1 -- `svc' [^:]*:12: Error: operand mismatch -- `add v0.4s,v1.4s,v2.2s' [^:]*:12: Info: did you mean this\? -[^:]*:12: Info: add v0.4s,v1.4s,v2.4s +[^:]*:12: Info: add v0.4s, v1.4s, v2.4s [^:]*:12: Info: other valid variant\(s\): -[^:]*:12: Info: add v0.8b,v1.8b,v2.8b -[^:]*:12: Info: add v0.16b,v1.16b,v2.16b -[^:]*:12: Info: add v0.4h,v1.4h,v2.4h -[^:]*:12: Info: add v0.8h,v1.8h,v2.8h -[^:]*:12: Info: add v0.2s,v1.2s,v2.2s -[^:]*:12: Info: add v0.2d,v1.2d,v2.2d +[^:]*:12: Info: add v0.8b, v1.8b, v2.8b +[^:]*:12: Info: add v0.16b, v1.16b, v2.16b +[^:]*:12: Info: add v0.4h, v1.4h, v2.4h +[^:]*:12: Info: add v0.8h, v1.8h, v2.8h +[^:]*:12: Info: add v0.2s, v1.2s, v2.2s +[^:]*:12: Info: add v0.2d, v1.2d, v2.2d [^:]*:13: Error: operand mismatch -- `urecpe v0.1d,v7.1d' [^:]*:13: Info: did you mean this\? -[^:]*:13: Info: urecpe v0.2s,v7.2s +[^:]*:13: Info: urecpe v0.2s, v7.2s [^:]*:13: Info: other valid variant\(s\): -[^:]*:13: Info: urecpe v0.4s,v7.4s +[^:]*:13: Info: urecpe v0.4s, v7.4s [^:]*:14: Error: operand mismatch -- `adds w0,wsp,x0,uxtx#1' [^:]*:14: Info: did you mean this\? -[^:]*:14: Info: adds w0,wsp,w0, uxtx #1 +[^:]*:14: Info: adds w0, wsp, w0, uxtx #1 [^:]*:14: Info: other valid variant\(s\): -[^:]*:14: Info: adds x0,sp,w0, uxtx #1 -[^:]*:14: Info: adds x0,sp,x0, lsl #1 +[^:]*:14: Info: adds x0, sp, w0, uxtx #1 +[^:]*:14: Info: adds x0, sp, x0, lsl #1 [^:]*:15: Error: operand mismatch -- `fmov d0,s0' [^:]*:15: Info: did you mean this\? -[^:]*:15: Info: fmov s0,s0 +[^:]*:15: Info: fmov s0, s0 [^:]*:15: Info: other valid variant\(s\): -[^:]*:15: Info: fmov d0,d0 +[^:]*:15: Info: fmov d0, d0 [^:]*:16: Error: operand mismatch -- `ldnp h3,h7,\[sp\],#16' [^:]*:16: Info: did you mean this\? -[^:]*:16: Info: ldnp s3,s7,\[sp\],#16 +[^:]*:16: Info: ldnp s3, s7, \[sp\], #16 [^:]*:16: Info: other valid variant\(s\): -[^:]*:16: Info: ldnp d3,d7,\[sp\],#16 -[^:]*:16: Info: ldnp q3,q7,\[sp\],#16 +[^:]*:16: Info: ldnp d3, d7, \[sp\], #16 +[^:]*:16: Info: ldnp q3, q7, \[sp\], #16 [^:]*:18: Error: operand mismatch -- `suqadd v0.8b,v1.16b' [^:]*:18: Info: did you mean this\? -[^:]*:18: Info: suqadd v0.8b,v1.8b +[^:]*:18: Info: suqadd v0.8b, v1.8b [^:]*:18: Info: other valid variant\(s\): -[^:]*:18: Info: suqadd v0.16b,v1.16b -[^:]*:18: Info: suqadd v0.4h,v1.4h -[^:]*:18: Info: suqadd v0.8h,v1.8h -[^:]*:18: Info: suqadd v0.2s,v1.2s -[^:]*:18: Info: suqadd v0.4s,v1.4s -[^:]*:18: Info: suqadd v0.2d,v1.2d +[^:]*:18: Info: suqadd v0.16b, v1.16b +[^:]*:18: Info: suqadd v0.4h, v1.4h +[^:]*:18: Info: suqadd v0.8h, v1.8h +[^:]*:18: Info: suqadd v0.2s, v1.2s +[^:]*:18: Info: suqadd v0.4s, v1.4s +[^:]*:18: Info: suqadd v0.2d, v1.2d [^:]*:20: Error: operand mismatch -- `ursqrte v2.8b,v3.8b' [^:]*:20: Info: did you mean this\? -[^:]*:20: Info: ursqrte v2.2s,v3.2s +[^:]*:20: Info: ursqrte v2.2s, v3.2s [^:]*:20: Info: other valid variant\(s\): -[^:]*:20: Info: ursqrte v2.4s,v3.4s +[^:]*:20: Info: ursqrte v2.4s, v3.4s [^:]*:22: Error: operand mismatch -- `rev32 v4.2s,v5.2s' [^:]*:22: Info: did you mean this\? -[^:]*:22: Info: rev32 v4.8b,v5.8b +[^:]*:22: Info: rev32 v4.8b, v5.8b [^:]*:22: Info: other valid variant\(s\): -[^:]*:22: Info: rev32 v4.16b,v5.16b -[^:]*:22: Info: rev32 v4.4h,v5.4h -[^:]*:22: Info: rev32 v4.8h,v5.8h +[^:]*:22: Info: rev32 v4.16b, v5.16b +[^:]*:22: Info: rev32 v4.4h, v5.4h +[^:]*:22: Info: rev32 v4.8h, v5.8h [^:]*:24: Error: operand mismatch -- `frintn v6.8b,v7.8b' [^:]*:24: Info: did you mean this\? -[^:]*:24: Info: frintn v6.4h,v7.4h +[^:]*:24: Info: frintn v6.4h, v7.4h [^:]*:24: Info: other valid variant\(s\): -[^:]*:24: Info: frintn v6.8h,v7.8h +[^:]*:24: Info: frintn v6.8h, v7.8h [^:]*:26: Error: operand mismatch -- `rev64 v8.2d,v9.2d' [^:]*:26: Info: did you mean this\? -[^:]*:26: Info: rev64 v8.8b,v9.8b +[^:]*:26: Info: rev64 v8.8b, v9.8b [^:]*:26: Info: other valid variant\(s\): -[^:]*:26: Info: rev64 v8.16b,v9.16b -[^:]*:26: Info: rev64 v8.4h,v9.4h -[^:]*:26: Info: rev64 v8.8h,v9.8h -[^:]*:26: Info: rev64 v8.2s,v9.2s -[^:]*:26: Info: rev64 v8.4s,v9.4s +[^:]*:26: Info: rev64 v8.16b, v9.16b +[^:]*:26: Info: rev64 v8.4h, v9.4h +[^:]*:26: Info: rev64 v8.8h, v9.8h +[^:]*:26: Info: rev64 v8.2s, v9.2s +[^:]*:26: Info: rev64 v8.4s, v9.4s [^:]*:28: Error: operand mismatch -- `rev16 v10.2s,v11.2s' [^:]*:28: Info: did you mean this\? -[^:]*:28: Info: rev16 v10.8b,v11.8b +[^:]*:28: Info: rev16 v10.8b, v11.8b [^:]*:28: Info: other valid variant\(s\): -[^:]*:28: Info: rev16 v10.16b,v11.16b +[^:]*:28: Info: rev16 v10.16b, v11.16b [^:]*:30: Error: operand mismatch -- `saddlp v12.8b,v13.8b' [^:]*:30: Info: did you mean this\? -[^:]*:30: Info: saddlp v12.4h,v13.8b +[^:]*:30: Info: saddlp v12.4h, v13.8b [^:]*:30: Info: other valid variant\(s\): -[^:]*:30: Info: saddlp v12.8h,v13.16b -[^:]*:30: Info: saddlp v12.2s,v13.4h -[^:]*:30: Info: saddlp v12.4s,v13.8h -[^:]*:30: Info: saddlp v12.1d,v13.2s -[^:]*:30: Info: saddlp v12.2d,v13.4s +[^:]*:30: Info: saddlp v12.8h, v13.16b +[^:]*:30: Info: saddlp v12.2s, v13.4h +[^:]*:30: Info: saddlp v12.4s, v13.8h +[^:]*:30: Info: saddlp v12.1d, v13.2s +[^:]*:30: Info: saddlp v12.2d, v13.4s [^:]*:32: Error: operand mismatch -- `shll v14.8b,v15.8h,#1' [^:]*:32: Info: did you mean this\? -[^:]*:32: Info: shll v14.8h,v15.8b,#1 +[^:]*:32: Info: shll v14.8h, v15.8b, #1 [^:]*:32: Info: other valid variant\(s\): -[^:]*:32: Info: shll v14.4s,v15.4h,#1 -[^:]*:32: Info: shll v14.2d,v15.2s,#1 +[^:]*:32: Info: shll v14.4s, v15.4h, #1 +[^:]*:32: Info: shll v14.2d, v15.2s, #1 [^:]*:34: Error: operand mismatch -- `shll2 v14.8b,v15.8h,#1' [^:]*:34: Info: did you mean this\? -[^:]*:34: Info: shll2 v14.4s,v15.8h,#1 +[^:]*:34: Info: shll2 v14.4s, v15.8h, #1 [^:]*:34: Info: other valid variant\(s\): -[^:]*:34: Info: shll2 v14.8h,v15.16b,#1 -[^:]*:34: Info: shll2 v14.2d,v15.4s,#1 +[^:]*:34: Info: shll2 v14.8h, v15.16b, #1 +[^:]*:34: Info: shll2 v14.2d, v15.4s, #1 [^:]*:36: Error: operand mismatch -- `fcvtxn v22.8b,v23.8b' [^:]*:36: Info: did you mean this\? -[^:]*:36: Info: fcvtxn v22.2s,v23.2d +[^:]*:36: Info: fcvtxn v22.2s, v23.2d [^:]*:38: Error: operand mismatch -- `fcvtxn2 v24.8b,v25.8b' [^:]*:38: Info: did you mean this\? -[^:]*:38: Info: fcvtxn2 v24.4s,v25.2d +[^:]*:38: Info: fcvtxn2 v24.4s, v25.2d [^:]*:40: Error: operand mismatch -- `fcvtn v25.4s,v26.4s' [^:]*:40: Info: did you mean this\? -[^:]*:40: Info: fcvtn v25.4h,v26.4s +[^:]*:40: Info: fcvtn v25.4h, v26.4s [^:]*:40: Info: other valid variant\(s\): -[^:]*:40: Info: fcvtn v25.2s,v26.2d +[^:]*:40: Info: fcvtn v25.2s, v26.2d [^:]*:42: Error: operand mismatch -- `fcvtn2 v27.4s,v28.4s' [^:]*:42: Info: did you mean this\? -[^:]*:42: Info: fcvtn2 v27.8h,v28.4s +[^:]*:42: Info: fcvtn2 v27.8h, v28.4s [^:]*:42: Info: other valid variant\(s\): -[^:]*:42: Info: fcvtn2 v27.4s,v28.2d +[^:]*:42: Info: fcvtn2 v27.4s, v28.2d [^:]*:44: Error: operand mismatch -- `fcvtl v29.8b,v30.8b' [^:]*:44: Info: did you mean this\? -[^:]*:44: Info: fcvtl v29.4s,v30.4h +[^:]*:44: Info: fcvtl v29.4s, v30.4h [^:]*:44: Info: other valid variant\(s\): -[^:]*:44: Info: fcvtl v29.2d,v30.2s +[^:]*:44: Info: fcvtl v29.2d, v30.2s [^:]*:46: Error: operand mismatch -- `fcvtl2 v1.2d,v2.2d' [^:]*:46: Info: did you mean this\? -[^:]*:46: Info: fcvtl2 v1.2d,v2.4s +[^:]*:46: Info: fcvtl2 v1.2d, v2.4s [^:]*:46: Info: other valid variant\(s\): -[^:]*:46: Info: fcvtl2 v1.4s,v2.8h +[^:]*:46: Info: fcvtl2 v1.4s, v2.8h [^:]*:48: Error: operand mismatch -- `sqadd v16.8b,v17.8h,v18.8h' [^:]*:48: Info: did you mean this\? -[^:]*:48: Info: sqadd v16.8h,v17.8h,v18.8h +[^:]*:48: Info: sqadd v16.8h, v17.8h, v18.8h [^:]*:48: Info: other valid variant\(s\): -[^:]*:48: Info: sqadd v16.8b,v17.8b,v18.8b -[^:]*:48: Info: sqadd v16.16b,v17.16b,v18.16b -[^:]*:48: Info: sqadd v16.4h,v17.4h,v18.4h -[^:]*:48: Info: sqadd v16.2s,v17.2s,v18.2s -[^:]*:48: Info: sqadd v16.4s,v17.4s,v18.4s -[^:]*:48: Info: sqadd v16.2d,v17.2d,v18.2d +[^:]*:48: Info: sqadd v16.8b, v17.8b, v18.8b +[^:]*:48: Info: sqadd v16.16b, v17.16b, v18.16b +[^:]*:48: Info: sqadd v16.4h, v17.4h, v18.4h +[^:]*:48: Info: sqadd v16.2s, v17.2s, v18.2s +[^:]*:48: Info: sqadd v16.4s, v17.4s, v18.4s +[^:]*:48: Info: sqadd v16.2d, v17.2d, v18.2d [^:]*:50: Error: operand mismatch -- `shadd v19.8b,v20.8h,v21.8h' [^:]*:50: Info: did you mean this\? -[^:]*:50: Info: shadd v19.8h,v20.8h,v21.8h +[^:]*:50: Info: shadd v19.8h, v20.8h, v21.8h [^:]*:50: Info: other valid variant\(s\): -[^:]*:50: Info: shadd v19.8b,v20.8b,v21.8b -[^:]*:50: Info: shadd v19.16b,v20.16b,v21.16b -[^:]*:50: Info: shadd v19.4h,v20.4h,v21.4h -[^:]*:50: Info: shadd v19.2s,v20.2s,v21.2s -[^:]*:50: Info: shadd v19.4s,v20.4s,v21.4s +[^:]*:50: Info: shadd v19.8b, v20.8b, v21.8b +[^:]*:50: Info: shadd v19.16b, v20.16b, v21.16b +[^:]*:50: Info: shadd v19.4h, v20.4h, v21.4h +[^:]*:50: Info: shadd v19.2s, v20.2s, v21.2s +[^:]*:50: Info: shadd v19.4s, v20.4s, v21.4s [^:]*:52: Error: operand mismatch -- `sha1su0 v1.16b,v2.16b,v3.16b' [^:]*:52: Info: did you mean this\? -[^:]*:52: Info: sha1su0 v1.4s,v2.4s,v3.4s +[^:]*:52: Info: sha1su0 v1.4s, v2.4s, v3.4s [^:]*:54: Error: operand mismatch -- `shadd v1.2d,v2.2d,v3.2d' [^:]*:54: Info: did you mean this\? -[^:]*:54: Info: shadd v1.8b,v2.8b,v3.8b +[^:]*:54: Info: shadd v1.8b, v2.8b, v3.8b [^:]*:54: Info: other valid variant\(s\): -[^:]*:54: Info: shadd v1.16b,v2.16b,v3.16b -[^:]*:54: Info: shadd v1.4h,v2.4h,v3.4h -[^:]*:54: Info: shadd v1.8h,v2.8h,v3.8h -[^:]*:54: Info: shadd v1.2s,v2.2s,v3.2s -[^:]*:54: Info: shadd v1.4s,v2.4s,v3.4s +[^:]*:54: Info: shadd v1.16b, v2.16b, v3.16b +[^:]*:54: Info: shadd v1.4h, v2.4h, v3.4h +[^:]*:54: Info: shadd v1.8h, v2.8h, v3.8h +[^:]*:54: Info: shadd v1.2s, v2.2s, v3.2s +[^:]*:54: Info: shadd v1.4s, v2.4s, v3.4s [^:]*:56: Error: operand mismatch -- `sqdmulh v1.16b,v2.16b,v3.16b' [^:]*:56: Info: did you mean this\? -[^:]*:56: Info: sqdmulh v1.4h,v2.4h,v3.4h +[^:]*:56: Info: sqdmulh v1.4h, v2.4h, v3.4h [^:]*:56: Info: other valid variant\(s\): -[^:]*:56: Info: sqdmulh v1.8h,v2.8h,v3.8h -[^:]*:56: Info: sqdmulh v1.2s,v2.2s,v3.2s -[^:]*:56: Info: sqdmulh v1.4s,v2.4s,v3.4s +[^:]*:56: Info: sqdmulh v1.8h, v2.8h, v3.8h +[^:]*:56: Info: sqdmulh v1.2s, v2.2s, v3.2s +[^:]*:56: Info: sqdmulh v1.4s, v2.4s, v3.4s [^:]*:58: Error: operand mismatch -- `sqdmlal2 v1.16b,v2.16b,v3.16b' [^:]*:58: Info: did you mean this\? -[^:]*:58: Info: sqdmlal2 v1.4s,v2.8h,v3.8h +[^:]*:58: Info: sqdmlal2 v1.4s, v2.8h, v3.8h [^:]*:58: Info: other valid variant\(s\): -[^:]*:58: Info: sqdmlal2 v1.2d,v2.4s,v3.4s +[^:]*:58: Info: sqdmlal2 v1.2d, v2.4s, v3.4s diff --git a/ld/ChangeLog b/ld/ChangeLog index 01c8a04fbf7..0d900f8fac8 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,5 +1,49 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after "," + in addresses. + * testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-301.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-302.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-310.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-313.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-515.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-516.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-531.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-532.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-533.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-534.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-535.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-536.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-537.d: Likewise. + * testsuite/ld-aarch64/emit-relocs-538.d: Likewise. + * testsuite/ld-aarch64/erratum835769.d: Likewise. + * testsuite/ld-aarch64/erratum843419.d: Likewise. + * testsuite/ld-aarch64/farcall-b-plt.d: Likewise. + * testsuite/ld-aarch64/farcall-bl-plt.d: Likewise. + * testsuite/ld-aarch64/gc-plt-relocs.d: Likewise. + * testsuite/ld-aarch64/ifunc-21.d: Likewise. + * testsuite/ld-aarch64/ifunc-7c.d: Likewise. + * testsuite/ld-aarch64/tls-desc-ie.d: Likewise. + * testsuite/ld-aarch64/tls-large-desc-be.d: Likewise. + * testsuite/ld-aarch64/tls-large-desc.d: Likewise. + * testsuite/ld-aarch64/tls-large-ie-be.d: Likewise. + * testsuite/ld-aarch64/tls-large-ie.d: Likewise. + * testsuite/ld-aarch64/tls-relax-all.d: Likewise. + * testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise. + * testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. + * testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise. + * testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. + * testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise. + * testsuite/ld-aarch64/tls-tiny-desc.d: Likewise. + * testsuite/ld-aarch64/tls-tiny-gd.d: Likewise. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. * testsuite/ld-aarch64/weak-undefined.d: Likewise. diff --git a/ld/testsuite/ld-aarch64/emit-relocs-28.d b/ld/testsuite/ld-aarch64/emit-relocs-28.d index 24424b93871..fd5c71c3b6d 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-28.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-28.d @@ -11,9 +11,9 @@ Disassembly of section .text: .* <\.text>: .*: .* adrp x2, .* <.*> .*: R_AARCH64_P32_ADR_PREL_PG_HI21 _GLOBAL_OFFSET_TABLE_ - .*: .* ldr x0, \[x2,#.*\] + .*: .* ldr x0, \[x2, #.*\] .*: R_AARCH64_P32_LD32_GOTPAGE_LO14 globala - .*: .* ldr x0, \[x2,#.*\] + .*: .* ldr x0, \[x2, #.*\] .*: R_AARCH64_P32_LD32_GOTPAGE_LO14 globalb - .*: .* ldr x0, \[x2,#.*\] + .*: .* ldr x0, \[x2, #.*\] .*: R_AARCH64_P32_LD32_GOTPAGE_LO14 globalc diff --git a/ld/testsuite/ld-aarch64/emit-relocs-301-be.d b/ld/testsuite/ld-aarch64/emit-relocs-301-be.d index dbe25609416..63f10457dc4 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-301-be.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-301-be.d @@ -17,7 +17,7 @@ Disassembly of section .text: 10010: R_AARCH64_MOVW_GOTOFF_G0_NC globalb 10014: f2800100 movk x0, #0x8 10014: R_AARCH64_MOVW_GOTOFF_G0_NC globalc - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 00000000 \.word 0x00000000 1001c: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ 10020: 0000ffe4 \.word 0x0000ffe4 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-301.d b/ld/testsuite/ld-aarch64/emit-relocs-301.d index 9270c9e20c5..9d6e31fcc74 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-301.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-301.d @@ -17,7 +17,7 @@ Disassembly of section .text: 10010: R_AARCH64_MOVW_GOTOFF_G0_NC globalb 10014: f2800100 movk x0, #0x8 10014: R_AARCH64_MOVW_GOTOFF_G0_NC globalc - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 0000ffe4 \.word 0x0000ffe4 1001c: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ 10020: 00000000 \.word 0x00000000 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-302-be.d b/ld/testsuite/ld-aarch64/emit-relocs-302-be.d index da8beef81cf..3cdf9fe08ed 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-302-be.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-302-be.d @@ -17,7 +17,7 @@ Disassembly of section .text: 10010: R_AARCH64_MOVW_GOTOFF_G1 globalb 10014: d2a00000 movz x0, #0x0, lsl #16 10014: R_AARCH64_MOVW_GOTOFF_G1 globalc - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 00000000 \.word 0x00000000 1001c: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ 10020: 0000ffe4 \.word 0x0000ffe4 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-302.d b/ld/testsuite/ld-aarch64/emit-relocs-302.d index 696b83655cd..a36d25ecb82 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-302.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-302.d @@ -17,7 +17,7 @@ Disassembly of section .text: 10010: R_AARCH64_MOVW_GOTOFF_G1 globalb 10014: d2a00000 movz x0, #0x0, lsl #16 10014: R_AARCH64_MOVW_GOTOFF_G1 globalc - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 0000ffe4 \.word 0x0000ffe4 1001c: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ 10020: 00000000 \.word 0x00000000 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-310-be.d b/ld/testsuite/ld-aarch64/emit-relocs-310-be.d index 7ef6fb66732..7eec2ab5f09 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-310-be.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-310-be.d @@ -11,11 +11,11 @@ Disassembly of section .text: 10000: 580000c1 ldr x1, 10018 <\.text\+0x18> 10004: 100000a2 adr x2, 10018 <\.text\+0x18> 10008: 8b010041 add x1, x2, x1 - 1000c: f9400820 ldr x0, \[x1,#16\] + 1000c: f9400820 ldr x0, \[x1, #16\] 1000c: R_AARCH64_LD64_GOTOFF_LO15 globala - 10010: f9400c20 ldr x0, \[x1,#24\] + 10010: f9400c20 ldr x0, \[x1, #24\] 10010: R_AARCH64_LD64_GOTOFF_LO15 globalb - 10014: f9400420 ldr x0, \[x1,#8\] + 10014: f9400420 ldr x0, \[x1, #8\] 10014: R_AARCH64_LD64_GOTOFF_LO15 globalc 10018: 00000000 .word 0x00000000 10018: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ diff --git a/ld/testsuite/ld-aarch64/emit-relocs-310.d b/ld/testsuite/ld-aarch64/emit-relocs-310.d index 2f78ddd2941..f7af0a3c254 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-310.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-310.d @@ -11,11 +11,11 @@ Disassembly of section .text: 10000: 580000c1 ldr x1, 10018 <\.text\+0x18> 10004: 100000a2 adr x2, 10018 <\.text\+0x18> 10008: 8b010041 add x1, x2, x1 - 1000c: f9400820 ldr x0, \[x1,#16\] + 1000c: f9400820 ldr x0, \[x1, #16\] 1000c: R_AARCH64_LD64_GOTOFF_LO15 globala - 10010: f9400c20 ldr x0, \[x1,#24\] + 10010: f9400c20 ldr x0, \[x1, #24\] 10010: R_AARCH64_LD64_GOTOFF_LO15 globalb - 10014: f9400420 ldr x0, \[x1,#8\] + 10014: f9400420 ldr x0, \[x1, #8\] 10014: R_AARCH64_LD64_GOTOFF_LO15 globalc 10018: 0000ffe8 .word 0x0000ffe8 10018: R_AARCH64_PREL64 _GLOBAL_OFFSET_TABLE_ diff --git a/ld/testsuite/ld-aarch64/emit-relocs-313.d b/ld/testsuite/ld-aarch64/emit-relocs-313.d index 0a7b5d151bc..1a28b3580f1 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-313.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-313.d @@ -10,9 +10,9 @@ Disassembly of section .text: 0000000000010000 <\.text>: 10000: 90000082 adrp x2, 20000 <_GLOBAL_OFFSET_TABLE_> 10000: R_AARCH64_ADR_PREL_PG_HI21 _GLOBAL_OFFSET_TABLE_ - 10004: f9400840 ldr x0, \[x2,#16\] + 10004: f9400840 ldr x0, \[x2, #16\] 10004: R_AARCH64_LD64_GOTPAGE_LO15 globala - 10008: f9400c40 ldr x0, \[x2,#24\] + 10008: f9400c40 ldr x0, \[x2, #24\] 10008: R_AARCH64_LD64_GOTPAGE_LO15 globalb - 1000c: f9400440 ldr x0, \[x2,#8\] + 1000c: f9400440 ldr x0, \[x2, #8\] 1000c: R_AARCH64_LD64_GOTPAGE_LO15 globalc diff --git a/ld/testsuite/ld-aarch64/emit-relocs-515-be.d b/ld/testsuite/ld-aarch64/emit-relocs-515-be.d index 6e0039d40d2..0bd39e3b755 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-515-be.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-515-be.d @@ -20,15 +20,15 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010024 \<.plt\>: - 10024: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + 10024: a9bf7bf0 stp x16, x30, \[sp, #-16\]! 10028: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 1002c: f9401611 ldr x17, \[x16,#40\] + 1002c: f9401611 ldr x17, \[x16, #40\] 10030: 9100a210 add x16, x16, #0x28 10034: d61f0220 br x17 10038: d503201f nop 1003c: d503201f nop 10040: d503201f nop 10044: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 10048: f9401a11 ldr x17, \[x16,#48\] + 10048: f9401a11 ldr x17, \[x16, #48\] 1004c: 9100c210 add x16, x16, #0x30 10050: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-515.d b/ld/testsuite/ld-aarch64/emit-relocs-515.d index a4e8a47af21..67f436bd3c9 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-515.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-515.d @@ -20,15 +20,15 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010024 \<.plt\>: - 10024: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + 10024: a9bf7bf0 stp x16, x30, \[sp, #-16\]! 10028: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 1002c: f9401611 ldr x17, \[x16,#40\] + 1002c: f9401611 ldr x17, \[x16, #40\] 10030: 9100a210 add x16, x16, #0x28 10034: d61f0220 br x17 10038: d503201f nop 1003c: d503201f nop 10040: d503201f nop 10044: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 10048: f9401a11 ldr x17, \[x16,#48\] + 10048: f9401a11 ldr x17, \[x16, #48\] 1004c: 9100c210 add x16, x16, #0x30 10050: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-516-be.d b/ld/testsuite/ld-aarch64/emit-relocs-516-be.d index 3a5576209aa..e3b528de8b7 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-516-be.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-516-be.d @@ -21,15 +21,15 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010028 \<.plt\>: - 10028: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + 10028: a9bf7bf0 stp x16, x30, \[sp, #-16\]! 1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 10030: f9401e11 ldr x17, \[x16,#56\] + 10030: f9401e11 ldr x17, \[x16, #56\] 10034: 9100e210 add x16, x16, #0x38 10038: d61f0220 br x17 1003c: d503201f nop 10040: d503201f nop 10044: d503201f nop 10048: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 1004c: f9402211 ldr x17, \[x16,#64\] + 1004c: f9402211 ldr x17, \[x16, #64\] 10050: 91010210 add x16, x16, #0x40 10054: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-516.d b/ld/testsuite/ld-aarch64/emit-relocs-516.d index 09d2c7a57e4..2ace032221d 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-516.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-516.d @@ -21,15 +21,15 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010028 \<.plt\>: - 10028: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + 10028: a9bf7bf0 stp x16, x30, \[sp, #-16\]! 1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 10030: f9401e11 ldr x17, \[x16,#56\] + 10030: f9401e11 ldr x17, \[x16, #56\] 10034: 9100e210 add x16, x16, #0x38 10038: d61f0220 br x17 1003c: d503201f nop 10040: d503201f nop 10044: d503201f nop 10048: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - 1004c: f9402211 ldr x17, \[x16,#64\] + 1004c: f9402211 ldr x17, \[x16, #64\] 10050: 91010210 add x16, x16, #0x40 10054: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-531.d b/ld/testsuite/ld-aarch64/emit-relocs-531.d index 588f127e25f..20b78e90f3d 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-531.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-531.d @@ -3,5 +3,5 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: 39801115 ldrsb x21, \[x8,#4\] + 10000: 39801115 ldrsb x21, \[x8, #4\] 10000: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 v2 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-532.d b/ld/testsuite/ld-aarch64/emit-relocs-532.d index f5f49b8407f..318c9264dce 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-532.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-532.d @@ -3,7 +3,7 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: 3980109d ldrsb x29, \[x4,#4\] + 10000: 3980109d ldrsb x29, \[x4, #4\] 10000: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC v2 - 10004: 398020f2 ldrsb x18, \[x7,#8\] + 10004: 398020f2 ldrsb x18, \[x7, #8\] 10004: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC v3 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-533.d b/ld/testsuite/ld-aarch64/emit-relocs-533.d index 09b3d11cb5d..35f8cc1e8d7 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-533.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-533.d @@ -3,5 +3,5 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: 798008eb ldrsh x11, \[x7,#4\] + 10000: 798008eb ldrsh x11, \[x7, #4\] 10000: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 v2 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-534.d b/ld/testsuite/ld-aarch64/emit-relocs-534.d index e2fa478794f..121fdc4c0b2 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-534.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-534.d @@ -3,7 +3,7 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: 798009d6 ldrsh x22, \[x14,#4\] + 10000: 798009d6 ldrsh x22, \[x14, #4\] 10000: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v2 - 10004: 79a71a28 ldrsh x8, \[x17,#5004\] + 10004: 79a71a28 ldrsh x8, \[x17, #5004\] 10004: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v3 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-535.d b/ld/testsuite/ld-aarch64/emit-relocs-535.d index 32766bfbe91..4dfc1274433 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-535.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-535.d @@ -3,5 +3,5 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: b9800661 ldrsw x1, \[x19,#4\] + 10000: b9800661 ldrsw x1, \[x19, #4\] 10000: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 v2 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-536.d b/ld/testsuite/ld-aarch64/emit-relocs-536.d index 862208a80e5..0a42fa15276 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-536.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-536.d @@ -3,7 +3,7 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: b98005d6 ldrsw x22, \[x14,#4\] + 10000: b98005d6 ldrsw x22, \[x14, #4\] 10000: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC v2 - 10004: b9800628 ldrsw x8, \[x17,#4\] + 10004: b9800628 ldrsw x8, \[x17, #4\] 10004: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC v3 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-537.d b/ld/testsuite/ld-aarch64/emit-relocs-537.d index 82cc9bbbb42..9067a90d191 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-537.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-537.d @@ -3,5 +3,5 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: f9400520 ldr x0, \[x9,#8\] + 10000: f9400520 ldr x0, \[x9, #8\] 10000: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 v2 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-538.d b/ld/testsuite/ld-aarch64/emit-relocs-538.d index dffde2337d1..6824c0b2116 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-538.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-538.d @@ -3,7 +3,7 @@ #objdump: -dr #... 0000000000010000 <.text>: - 10000: f9400482 ldr x2, \[x4,#8\] + 10000: f9400482 ldr x2, \[x4, #8\] 10000: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC v2 - 10004: f940062e ldr x14, \[x17,#8\] + 10004: f940062e ldr x14, \[x17, #8\] 10004: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC v3 diff --git a/ld/testsuite/ld-aarch64/erratum835769.d b/ld/testsuite/ld-aarch64/erratum835769.d index f3b0ed4e693..c1a71ad4ea9 100644 --- a/ld/testsuite/ld-aarch64/erratum835769.d +++ b/ld/testsuite/ld-aarch64/erratum835769.d @@ -2,7 +2,7 @@ Disassembly of section .text: #... [0-9a-f]+ <a1ldr>: -[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4,#8\]\! +[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4, #8\]\! [ \t0-9a-f]+:[ \t]+1b017c06[ \t]+mul[ \t]+w6, w0, w1 [ \t0-9a-f]+:[ \t]+f9400084[ \t]+ldr[ \t]+x4, \[x4\] [ \t0-9a-f]+:[ \t0-9a-z]+[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_0> @@ -10,7 +10,7 @@ Disassembly of section .text: [ \t0-9a-f]+:[ \t]+d65f03c0[ \t]+ret [0-9a-f]+ <a5ldr>: -[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4,#8\]! +[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4, #8\]! [ \t0-9a-f]+:[ \t]+1b017c06[ \t]+mul[ \t]+w6, w0, w1 [ \t0-9a-f]+:[ \t]+f9400084[ \t]+ldr[ \t]+x4, \[x4\] [ \t0-9a-f]+:[ \t0-9a-z]+[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_1> @@ -18,7 +18,7 @@ Disassembly of section .text: [ \t0-9a-f]+:[ \t]+d65f03c0[ \t]+ret [0-9a-f]+ <a6ldr>: -[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4,#8\]! +[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4, #8\]! [ \t0-9a-f]+:[ \t]+1b017c06[ \t]+mul[ \t]+w6, w0, w1 [ \t0-9a-f]+:[ \t]+f9400084[ \t]+ldr[ \t]+x4, \[x4\] [ \t0-9a-f]+:[ \t]+9b031885[ \t]+madd[ \t]+x5, x4, x3, x6 @@ -26,7 +26,7 @@ Disassembly of section .text: [ \t0-9a-f]+:[ \t]+d65f03c0[ \t]+ret [0-9a-f]+ <a7str>: -[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4,#8\]! +[ \t0-9a-f]+:[ \t]+b8408c87[ \t]+ldr[ \t]+w7, \[x4, #8\]! [ \t0-9a-f]+:[ \t]+1b017c06[ \t]+mul[ \t]+w6, w0, w1 [ \t0-9a-f]+:[ \t]+f9000084[ \t]+str[ \t]+x4, \[x4\] [ \t0-9a-f]+:[ \t0-9a-z]+[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_2> diff --git a/ld/testsuite/ld-aarch64/erratum843419.d b/ld/testsuite/ld-aarch64/erratum843419.d index 4be8f9e5850..55a8a8ca905 100644 --- a/ld/testsuite/ld-aarch64/erratum843419.d +++ b/ld/testsuite/ld-aarch64/erratum843419.d @@ -9,17 +9,17 @@ Disassembly of section .e843419: 0000000020000000 <e843419>: 20000000: d10043ff sub sp, sp, #0x10 20000004: d28001a7 mov x7, #0xd // #13 - 20000008: b9000fe7 str w7, \[sp,#12\] + 20000008: b9000fe7 str w7, \[sp, #12\] 2000000c: 140003fb b 20000ff8 <e843419_1> ... 0000000020000ff8 <e843419_1>: 20000ff8: 90100000 adrp x0, 40000000 <[_a-zA-z0-9]+> - 20000ffc: f800c007 stur x7, \[x0,#12\] + 20000ffc: f800c007 stur x7, \[x0, #12\] 20001000: d2800128 mov x8, #0x9 // #9 20001004: 14000008 b 20001024 <e843419@0002_00000013_1004> 20001008: 8b050020 add x0, x1, x5 - 2000100c: b9400fe7 ldr w7, \[sp,#12\] + 2000100c: b9400fe7 ldr w7, \[sp, #12\] 20001010: 0b0700e0 add w0, w7, w7 20001014: 910043ff add sp, sp, #0x10 20001018: 14000005 b 2000102c <__e835769_veneer> @@ -39,7 +39,7 @@ Disassembly of section .e843419: Disassembly of section .e835769: 0000000003000000 <e835769>: - 3000000: b8408c87 ldr w7, \[x4,#8\]! + 3000000: b8408c87 ldr w7, \[x4, #8\]! 3000004: 1b017c06 mul w6, w0, w1 3000008: f9400084 ldr x4, \[x4\] 300000c: 14000004 b 300001c <__erratum_835769_veneer_0> @@ -57,7 +57,7 @@ Disassembly of section .text: 0000000000400000 <main>: 400000: d10043ff sub sp, sp, #0x10 400004: d28001a7 mov x7, #0xd // #13 - 400008: b9000fe7 str w7, \[sp,#12\] + 400008: b9000fe7 str w7, \[sp, #12\] 40000c: 14000003 b 400018 <__e843419_veneer> 400010: d65f03c0 ret 400014: 14000400 b 401014 <__e843419_veneer\+0xffc> diff --git a/ld/testsuite/ld-aarch64/farcall-b-plt.d b/ld/testsuite/ld-aarch64/farcall-b-plt.d index 49c82eb1d17..00469affef5 100644 --- a/ld/testsuite/ld-aarch64/farcall-b-plt.d +++ b/ld/testsuite/ld-aarch64/farcall-b-plt.d @@ -8,9 +8,9 @@ Disassembly of section .plt: .* <foo@plt.*>: -.*: a9bf7bf0 stp x16, x30, \[sp,#-16\]! +.*: a9bf7bf0 stp x16, x30, \[sp, #-16\]! .*: .* adrp x16, .* <__foo_veneer\+.*> -.*: .* ldr x17, \[x16,#.*\] +.*: .* ldr x17, \[x16, #.*\] .*: .* add x16, x16, #.* .*: d61f0220 br x17 .*: d503201f nop @@ -19,7 +19,7 @@ Disassembly of section .plt: .* <foo@plt>: .*: .* adrp x16, .* <__foo_veneer\+.*> -.*: .* ldr x17, \[x16,#.*\] +.*: .* ldr x17, \[x16, #.*\] .*: .* add x16, x16, #.* .*: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/farcall-bl-plt.d b/ld/testsuite/ld-aarch64/farcall-bl-plt.d index 457a4faa0b3..28fcb8cee25 100644 --- a/ld/testsuite/ld-aarch64/farcall-bl-plt.d +++ b/ld/testsuite/ld-aarch64/farcall-bl-plt.d @@ -8,9 +8,9 @@ Disassembly of section .plt: .* <foo@plt.*>: -.*: a9bf7bf0 stp x16, x30, \[sp,#-16\]! +.*: a9bf7bf0 stp x16, x30, \[sp, #-16\]! .*: .* adrp x16, .* <__foo_veneer\+.*> -.*: .* ldr x17, \[x16,#.*\] +.*: .* ldr x17, \[x16, #.*\] .*: .* add x16, x16, #.* .*: d61f0220 br x17 .*: d503201f nop @@ -19,7 +19,7 @@ Disassembly of section .plt: .* <foo@plt>: .*: .* adrp x16, .* <__foo_veneer\+.*> -.*: .* ldr x17, \[x16,#.*\] +.*: .* ldr x17, \[x16, #.*\] .*: .* add x16, x16, #.* .*: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/gc-plt-relocs.d b/ld/testsuite/ld-aarch64/gc-plt-relocs.d index cb38c8dc038..086968c7281 100644 --- a/ld/testsuite/ld-aarch64/gc-plt-relocs.d +++ b/ld/testsuite/ld-aarch64/gc-plt-relocs.d @@ -34,15 +34,15 @@ Disassembly of section .text: Disassembly of section .plt: 0+8010 \<\.plt\>: - 8010: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + 8010: a9bf7bf0 stp x16, x30, \[sp, #-16\]! 8014: b0000010 adrp x16, 9000 .* - 8018: f9400e11 ldr x17, \[x16,#24\] + 8018: f9400e11 ldr x17, \[x16, #24\] 801c: 91006210 add x16, x16, #0x18 8020: d61f0220 br x17 8024: d503201f nop 8028: d503201f nop 802c: d503201f nop 8030: b0000010 adrp x16, 9000 .* - 8034: f9401211 ldr x17, \[x16,#32\] + 8034: f9401211 ldr x17, \[x16, #32\] 8038: 91008210 add x16, x16, #0x20 803c: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/ifunc-21.d b/ld/testsuite/ld-aarch64/ifunc-21.d index 9ea01e6b6e5..eef2e62b64c 100644 --- a/ld/testsuite/ld-aarch64/ifunc-21.d +++ b/ld/testsuite/ld-aarch64/ifunc-21.d @@ -20,7 +20,7 @@ Disassembly of section .text: .* <bar>: .*: 90000080 adrp x0, 10000 <.*> - .*: .* ldr x0, \[x0,#(960|1040)\] + .*: .* ldr x0, \[x0, #(960|1040)\] .*: d65f03c0 ret #pass
\ No newline at end of file diff --git a/ld/testsuite/ld-aarch64/ifunc-7c.d b/ld/testsuite/ld-aarch64/ifunc-7c.d index 1967742bf9e..e56322a4a2f 100644 --- a/ld/testsuite/ld-aarch64/ifunc-7c.d +++ b/ld/testsuite/ld-aarch64/ifunc-7c.d @@ -16,4 +16,4 @@ Disassembly of section \.text: [0-9a-f]+ <__start>: [0-9a-f]+: [0-9a-f]+ bl [0-9a-f]+ <\*ABS\*\+0x[0-9a-f]+@plt> [0-9a-f]+: [0-9a-f]+ adrp x0, [0-9]+ <__start\+0x[0-9a-f]+> - [0-9a-f]+: [0-9a-f]+ ldr x0, \[x0,.+\] + [0-9a-f]+: [0-9a-f]+ ldr x0, \[x0, .+\] diff --git a/ld/testsuite/ld-aarch64/tls-desc-ie.d b/ld/testsuite/ld-aarch64/tls-desc-ie.d index 037da07bbfe..5b778723555 100644 --- a/ld/testsuite/ld-aarch64/tls-desc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-desc-ie.d @@ -7,14 +7,14 @@ +10008: 94000016 bl 10060 <v1\+0x10060> +1000c: d503201f nop +10010: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10014: f9400400 ldr x0, \[x0,#8\] + +10014: f9400400 ldr x0, \[x0, #8\] +10018: d503201f nop +1001c: d503201f nop +10020: d53bd041 mrs x1, tpidr_el0 +10024: 8b000020 add x0, x1, x0 +10028: d53bd042 mrs x2, tpidr_el0 +1002c: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10030: f9400400 ldr x0, \[x0,#8\] + +10030: f9400400 ldr x0, \[x0, #8\] +10034: 8b000040 add x0, x2, x0 +10038: b9400000 ldr w0, \[x0\] +1003c: 0b000020 add w0, w1, w0 @@ -22,15 +22,15 @@ Disassembly of section .plt: 0000000000010040 <.plt>: - +10040: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +10040: a9bf7bf0 stp x16, x30, \[sp, #-16\]! +10044: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_> - +10048: f9401a11 ldr x17, \[x16,#48\] + +10048: f9401a11 ldr x17, \[x16, #48\] +1004c: 9100c210 add x16, x16, #0x30 +10050: d61f0220 br x17 +10054: d503201f nop +10058: d503201f nop +1005c: d503201f nop +10060: 90000090 adrp x16, 20000 <_GLOBAL_OFFSET_TABLE_> - +10064: f9401e11 ldr x17, \[x16,#56\] + +10064: f9401e11 ldr x17, \[x16, #56\] +10068: 9100e210 add x16, x16, #0x38 +1006c: d61f0220 br x17 diff --git a/ld/testsuite/ld-aarch64/tls-large-desc-be.d b/ld/testsuite/ld-aarch64/tls-large-desc-be.d index 2d72da6761c..217794ce94c 100644 --- a/ld/testsuite/ld-aarch64/tls-large-desc-be.d +++ b/ld/testsuite/ld-aarch64/tls-large-desc-be.d @@ -12,7 +12,7 @@ Disassembly of section .text: +10008: 8b020032 add x18, x1, x2 +1000c: d2a00000 movz x0, #0x0, lsl #16 +10010: f2800500 movk x0, #0x28 - +10014: f8606a41 ldr x1, \[x18,x0\] + +10014: f8606a41 ldr x1, \[x18, x0\] +10018: 8b000240 add x0, x18, x0 +1001c: d63f0020 blr x1 +10020: 00000000 .word 0x00000000 @@ -21,18 +21,18 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010028 <.plt>: - +10028: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +10028: a9bf7bf0 stp x16, x30, \[sp, #-16\]! +1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10030: f9401211 ldr x17, \[x16,#32\] + +10030: f9401211 ldr x17, \[x16, #32\] +10034: 91008210 add x16, x16, #0x20 +10038: d61f0220 br x17 +1003c: d503201f nop +10040: d503201f nop +10044: d503201f nop - +10048: a9bf0fe2 stp x2, x3, \[sp,#-16\]! + +10048: a9bf0fe2 stp x2, x3, \[sp, #-16\]! +1004c: 90000082 adrp x2, 20000 \<_GLOBAL_OFFSET_TABLE_\> +10050: 90000083 adrp x3, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10054: f9400442 ldr x2, \[x2,#8\] + +10054: f9400442 ldr x2, \[x2, #8\] +10058: 91004063 add x3, x3, #0x10 +1005c: d61f0040 br x2 +10060: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-large-desc.d b/ld/testsuite/ld-aarch64/tls-large-desc.d index b8dcc02259c..9fa6dccfa41 100644 --- a/ld/testsuite/ld-aarch64/tls-large-desc.d +++ b/ld/testsuite/ld-aarch64/tls-large-desc.d @@ -12,7 +12,7 @@ Disassembly of section .text: +10008: 8b020032 add x18, x1, x2 +1000c: d2a00000 movz x0, #0x0, lsl #16 +10010: f2800500 movk x0, #0x28 - +10014: f8606a41 ldr x1, \[x18,x0\] + +10014: f8606a41 ldr x1, \[x18, x0\] +10018: 8b000240 add x0, x18, x0 +1001c: d63f0020 blr x1 +10020: 0000ffe0 .word 0x0000ffe0 @@ -21,18 +21,18 @@ Disassembly of section .text: Disassembly of section .plt: 0000000000010028 <.plt>: - +10028: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +10028: a9bf7bf0 stp x16, x30, \[sp, #-16\]! +1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10030: f9401211 ldr x17, \[x16,#32\] + +10030: f9401211 ldr x17, \[x16, #32\] +10034: 91008210 add x16, x16, #0x20 +10038: d61f0220 br x17 +1003c: d503201f nop +10040: d503201f nop +10044: d503201f nop - +10048: a9bf0fe2 stp x2, x3, \[sp,#-16\]! + +10048: a9bf0fe2 stp x2, x3, \[sp, #-16\]! +1004c: 90000082 adrp x2, 20000 \<_GLOBAL_OFFSET_TABLE_\> +10050: 90000083 adrp x3, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10054: f9400442 ldr x2, \[x2,#8\] + +10054: f9400442 ldr x2, \[x2, #8\] +10058: 91004063 add x3, x3, #0x10 +1005c: d61f0040 br x2 +10060: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-large-ie-be.d b/ld/testsuite/ld-aarch64/tls-large-ie-be.d index 380718bf5c2..64a4384f41b 100644 --- a/ld/testsuite/ld-aarch64/tls-large-ie-be.d +++ b/ld/testsuite/ld-aarch64/tls-large-ie-be.d @@ -13,7 +13,7 @@ Disassembly of section .text: 1000c: d53bd042 mrs x2, tpidr_el0 10010: d2a00000 movz x0, #0x0, lsl #16 10014: f2800100 movk x0, #0x8 - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 8b020000 add x0, x0, x2 10020: d503201f nop 10024: 0000(ffdc|0000) .word 0x0000(ffdc|0000) diff --git a/ld/testsuite/ld-aarch64/tls-large-ie.d b/ld/testsuite/ld-aarch64/tls-large-ie.d index 13b77f31e30..98606d6f963 100644 --- a/ld/testsuite/ld-aarch64/tls-large-ie.d +++ b/ld/testsuite/ld-aarch64/tls-large-ie.d @@ -13,7 +13,7 @@ Disassembly of section .text: 1000c: d53bd042 mrs x2, tpidr_el0 10010: d2a00000 movz x0, #0x0, lsl #16 10014: f2800100 movk x0, #0x8 - 10018: f8606820 ldr x0, \[x1,x0\] + 10018: f8606820 ldr x0, \[x1, x0\] 1001c: 8b020000 add x0, x0, x2 10020: d503201f nop 10024: 0000ffdc .word 0x0000ffdc diff --git a/ld/testsuite/ld-aarch64/tls-relax-all.d b/ld/testsuite/ld-aarch64/tls-relax-all.d index b36b634e101..59421864f95 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-all.d +++ b/ld/testsuite/ld-aarch64/tls-relax-all.d @@ -2,10 +2,10 @@ #ld: -T relocs.ld -e0 #objdump: -dr #... - +10000: a9bf7bfd stp x29, x30, \[sp,#-16\]! + +10000: a9bf7bfd stp x29, x30, \[sp, #-16\]! +10004: 910003fd mov x29, sp +10008: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +1000c: f9400400 ldr x0, \[x0,#8\] + +1000c: f9400400 ldr x0, \[x0, #8\] +10010: d503201f nop +10014: d503201f nop +10018: d53bd041 mrs x1, tpidr_el0 @@ -20,7 +20,7 @@ +1003c: b9400000 ldr w0, \[x0\] +10040: 0b000021 add w1, w1, w0 +10044: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10048: f9400800 ldr x0, \[x0,#16\] + +10048: f9400800 ldr x0, \[x0, #16\] +1004c: d53bd041 mrs x1, tpidr_el0 +10050: 8b000020 add x0, x1, x0 +10054: b9400000 ldr w0, \[x0\] diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d index d3783ac7f56..f80bb907770 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d @@ -3,7 +3,7 @@ #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10004: f9400400 ldr x0, \[x0,#8\] + +10004: f9400400 ldr x0, \[x0, #8\] +10008: d53bd041 mrs x1, tpidr_el0 +1000c: 8b000020 add x0, x1, x0 +10010: b9400000 ldr w0, \[x0\] diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d index 92002deaedd..2b8e346fc66 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d @@ -4,7 +4,7 @@ #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> +10004: d503201f nop - +10008: f9400400 ldr x0, \[x0,#8\] + +10008: f9400400 ldr x0, \[x0, #8\] +1000c: d503201f nop +10010: d503201f nop +10014: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d index 634a55ae115..86277f82565 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d @@ -3,7 +3,7 @@ #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10004: f9400400 ldr x0, \[x0,#8\] + +10004: f9400400 ldr x0, \[x0, #8\] +10008: d503201f nop +1000c: d503201f nop +10010: d53bd041 mrs x1, tpidr_el0 diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d index ea2e59bea8d..8994b94e0b1 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d +++ b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d @@ -12,7 +12,7 @@ Disassembly of section .text: +10008: 8b020032 add x18, x1, x2 +1000c: d2a00000 movz x0, #0x0, lsl #16 +10010: f2800100 movk x0, #0x8 - +10014: f8606a40 ldr x0, \[x18,x0\] + +10014: f8606a40 ldr x0, \[x18, x0\] +10018: d503201f nop +1001c: d503201f nop +10020: 00000000 .word 0x00000000 diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d index 680fc57ea1d..21ad5e5a18c 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d @@ -12,7 +12,7 @@ Disassembly of section .text: +10008: 8b020032 add x18, x1, x2 +1000c: d2a00000 movz x0, #0x0, lsl #16 +10010: f2800100 movk x0, #0x8 - +10014: f8606a40 ldr x0, \[x18,x0\] + +10014: f8606a40 ldr x0, \[x18, x0\] +10018: d503201f nop +1001c: d503201f nop +10020: 0000ffe0 .word 0x0000ffe0 diff --git a/ld/testsuite/ld-aarch64/tls-tiny-desc.d b/ld/testsuite/ld-aarch64/tls-tiny-desc.d index fc75eee2ddf..7b88786a302 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-desc.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-desc.d @@ -13,18 +13,18 @@ Disassembly of section .text: Disassembly of section .plt: 000000000001000c \<.plt\>: - +1000c: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +1000c: a9bf7bf0 stp x16, x30, \[sp, #-16\]! +10010: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10014: f9401211 ldr x17, \[x16,#32\] + +10014: f9401211 ldr x17, \[x16, #32\] +10018: 91008210 add x16, x16, #0x20 +1001c: d61f0220 br x17 +10020: d503201f nop +10024: d503201f nop +10028: d503201f nop - +1002c: a9bf0fe2 stp x2, x3, \[sp,#-16\]! + +1002c: a9bf0fe2 stp x2, x3, \[sp, #-16\]! +10030: 90000082 adrp x2, 20000 \<_GLOBAL_OFFSET_TABLE_\> +10034: 90000083 adrp x3, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10038: f9400442 ldr x2, \[x2,#8\] + +10038: f9400442 ldr x2, \[x2, #8\] +1003c: 91004063 add x3, x3, #0x10 +10040: d61f0040 br x2 +10044: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-tiny-gd.d b/ld/testsuite/ld-aarch64/tls-tiny-gd.d index 5e777069394..2f55f7b7db8 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-gd.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-gd.d @@ -13,15 +13,15 @@ Disassembly of section .text: Disassembly of section .plt: 000000000001000c \<.plt\>: - +1000c: a9bf7bf0 stp x16, x30, \[sp,#-16\]! + +1000c: a9bf7bf0 stp x16, x30, \[sp, #-16\]! +10010: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10014: f9401611 ldr x17, \[x16,#40\] + +10014: f9401611 ldr x17, \[x16, #40\] +10018: 9100a210 add x16, x16, #0x28 +1001c: d61f0220 br x17 +10020: d503201f nop +10024: d503201f nop +10028: d503201f nop +1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\> - +10030: f9401a11 ldr x17, \[x16,#48\] + +10030: f9401a11 ldr x17, \[x16, #48\] +10034: 9100c210 add x16, x16, #0x30 +10038: d61f0220 br x17 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 63271f2dd89..c712058bb4d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * aarch64-opc.c (print_immediate_offset_address): Print spaces + after commas in addresses. + (aarch64_print_operand): Likewise. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" rather than "should be" or "expected to be" in error messages. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0f0795bf404..adc34e29b9c 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2864,20 +2864,20 @@ print_immediate_offset_address (char *buf, size_t size, if (opnd->addr.writeback) { if (opnd->addr.preind) - snprintf (buf, size, "[%s,#%d]!", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm); else - snprintf (buf, size, "[%s],#%d", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm); } else { if (opnd->shifter.operator_present) { assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL); - snprintf (buf, size, "[%s,#%d,mul vl]", + snprintf (buf, size, "[%s, #%d, mul vl]", base, opnd->addr.offset.imm); } else if (opnd->addr.offset.imm) - snprintf (buf, size, "[%s,#%d]", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm); else snprintf (buf, size, "[%s]", base); } @@ -2912,15 +2912,15 @@ print_register_offset_address (char *buf, size_t size, if (print_extend_p) { if (print_amount_p) - snprintf (tb, sizeof (tb), ",%s #%" PRIi64, shift_name, + snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name, opnd->shifter.amount); else - snprintf (tb, sizeof (tb), ",%s", shift_name); + snprintf (tb, sizeof (tb), ", %s", shift_name); } else tb[0] = '\0'; - snprintf (buf, size, "[%s,%s%s]", base, offset, tb); + snprintf (buf, size, "[%s, %s%s]", base, offset, tb); } /* Generate the string representation of the operand OPNDS[IDX] for OPCODE @@ -3433,7 +3433,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_ADDR_UIMM12: name = get_64bit_int_reg_name (opnd->addr.base_regno, 1); if (opnd->addr.offset.imm) - snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm); else snprintf (buf, size, "[%s]", name); break; |