diff options
Diffstat (limited to 'gdb/rs6000-tdep.c')
| -rw-r--r-- | gdb/rs6000-tdep.c | 412 |
1 files changed, 206 insertions, 206 deletions
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index d4d7781a790..58df38b003d 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -243,7 +243,7 @@ ppc_floating_point_unit_p (struct gdbarch *gdbarch) struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); return (tdep->ppc_fp0_regnum >= 0 - && tdep->ppc_fpscr_regnum >= 0); + && tdep->ppc_fpscr_regnum >= 0); } /* Return non-zero if the architecture described by GDBARCH has @@ -254,7 +254,7 @@ ppc_altivec_support_p (struct gdbarch *gdbarch) struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); return (tdep->ppc_vr0_regnum >= 0 - && tdep->ppc_vrsave_regnum >= 0); + && tdep->ppc_vrsave_regnum >= 0); } /* Check that TABLE[GDB_REGNO] is not already initialized, and then @@ -302,8 +302,8 @@ init_sim_regno_table (struct gdbarch *arch) if (tdep->ppc_fp0_regnum >= 0) for (i = 0; i < ppc_num_fprs; i++) set_sim_regno (sim_regno, - tdep->ppc_fp0_regnum + i, - sim_ppc_f0_regnum + i); + tdep->ppc_fp0_regnum + i, + sim_ppc_f0_regnum + i); if (tdep->ppc_fpscr_regnum >= 0) set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); @@ -325,15 +325,15 @@ init_sim_regno_table (struct gdbarch *arch) if (tdep->ppc_vr0_regnum >= 0) { for (i = 0; i < ppc_num_vrs; i++) - set_sim_regno (sim_regno, - tdep->ppc_vr0_regnum + i, - sim_ppc_vr0_regnum + i); + set_sim_regno (sim_regno, + tdep->ppc_vr0_regnum + i, + sim_ppc_vr0_regnum + i); /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, - we can treat this more like the other cases. */ + we can treat this more like the other cases. */ set_sim_regno (sim_regno, - tdep->ppc_vr0_regnum + ppc_num_vrs, - sim_ppc_vscr_regnum); + tdep->ppc_vr0_regnum + ppc_num_vrs, + sim_ppc_vscr_regnum); } /* vsave is a special-purpose register, so the code below handles it. */ @@ -341,8 +341,8 @@ init_sim_regno_table (struct gdbarch *arch) if (tdep->ppc_ev0_upper_regnum >= 0) for (i = 0; i < ppc_num_gprs; i++) set_sim_regno (sim_regno, - tdep->ppc_ev0_upper_regnum + i, - sim_ppc_rh0_regnum + i); + tdep->ppc_ev0_upper_regnum + i, + sim_ppc_rh0_regnum + i); if (tdep->ppc_acc_regnum >= 0) set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); /* spefscr is a special-purpose register, so the code below handles it. */ @@ -686,8 +686,8 @@ insn_changes_sp_or_jumps (unsigned long insn) /* Changes the stack pointer. */ /* NOTE: There are many ways to change the value of a given register. - The ways below are those used when the register is R1, the SP, - in a funtion's epilogue. */ + The ways below are those used when the register is R1, the SP, + in a funtion's epilogue. */ if (opcode == 31 && subcode == 444 && a == 1) return 1; /* mr R1,Rn */ @@ -715,17 +715,17 @@ insn_changes_sp_or_jumps (unsigned long insn) 1) scan forward from the point of execution: a) If you find an instruction that modifies the stack pointer - or transfers control (except a return), execution is not in - an epilogue, return. + or transfers control (except a return), execution is not in + an epilogue, return. b) Stop scanning if you find a return instruction or reach the - end of the function or reach the hard limit for the size of - an epilogue. + end of the function or reach the hard limit for the size of + an epilogue. 2) scan backward from the point of execution: - a) If you find an instruction that modifies the stack pointer, - execution *is* in an epilogue, return. - b) Stop scanning if you reach an instruction that transfers - control or the beginning of the function or reach the hard - limit for the size of an epilogue. */ + a) If you find an instruction that modifies the stack pointer, + execution *is* in an epilogue, return. + b) Stop scanning if you reach an instruction that transfers + control or the beginning of the function or reach the hard + limit for the size of an epilogue. */ static int rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, @@ -753,10 +753,10 @@ rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) { if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) - return 0; + return 0; insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); if (insn == 0x4e800020) - break; + break; /* Assume a bctr is a tail call unless it points strictly within this function. */ if (insn == 0x4e800420) @@ -769,7 +769,7 @@ rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, break; } if (insn_changes_sp_or_jumps (insn)) - return 0; + return 0; } /* Scan backward until adjustment to stack pointer (R1). */ @@ -779,10 +779,10 @@ rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, scan_pc -= PPC_INSN_SIZE) { if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) - return 0; + return 0; insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); if (insn_changes_sp_or_jumps (insn)) - return 1; + return 1; } return 0; @@ -890,7 +890,7 @@ ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, if (debug_displaced) { fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", - paddress (gdbarch, from), paddress (gdbarch, to)); + paddress (gdbarch, from), paddress (gdbarch, to)); displaced_step_dump_bytes (gdb_stdlog, buf, len); } @@ -1033,16 +1033,16 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); /* Assume that there is at most one conditional branch in the atomic - sequence. If a conditional branch is found, put a breakpoint in - its destination address. */ + sequence. If a conditional branch is found, put a breakpoint in + its destination address. */ if ((insn & BRANCH_MASK) == BC_INSN) - { - int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; - int absolute = insn & 2; + { + int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; + int absolute = insn & 2; - if (bc_insn_count >= 1) - return {}; /* More than one conditional branch found, fallback - to the standard single-step code. */ + if (bc_insn_count >= 1) + return {}; /* More than one conditional branch found, fallback + to the standard single-step code. */ if (absolute) breaks[1] = immediate; @@ -1051,10 +1051,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) bc_insn_count++; last_breakpoint++; - } + } if (IS_STORE_CONDITIONAL_INSN (insn)) - break; + break; } /* Assume that the atomic sequence ends with a Store Conditional @@ -1112,12 +1112,12 @@ store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) const int ry_regno = GET_SRC_REG (op); if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) - { - *r0_contains_arg = 1; - return 1; - } + { + *r0_contains_arg = 1; + return 1; + } else - return 0; + return 0; } /* Save a General Purpose Register on stack. */ @@ -1130,7 +1130,7 @@ store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) return (rx_regno >= 3 && rx_regno <= 10); } - + /* Save a General Purpose Register on stack via the Frame Pointer. */ if (framep && @@ -1139,11 +1139,11 @@ store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ { /* Rx: Usually, only r3 - r10 are used for parameter passing. - However, the compiler sometimes uses r0 to hold an argument. */ + However, the compiler sometimes uses r0 to hold an argument. */ const int rx_regno = GET_SRC_REG (op); return ((rx_regno >= 3 && rx_regno <= 10) - || (rx_regno == 0 && *r0_contains_arg)); + || (rx_regno == 0 && *r0_contains_arg)); } if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ @@ -1269,93 +1269,93 @@ rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) unsigned long op = rs6000_fetch_instruction (gdbarch, pc); /* First possible sequence: A small number of probes. - stw 0, -<some immediate>(1) - [repeat this instruction any (small) number of times]. */ + stw 0, -<some immediate>(1) + [repeat this instruction any (small) number of times]. */ if ((op & 0xffff0000) == 0x90010000) { while ((op & 0xffff0000) == 0x90010000) - { - pc = pc + 4; - op = rs6000_fetch_instruction (gdbarch, pc); - } + { + pc = pc + 4; + op = rs6000_fetch_instruction (gdbarch, pc); + } return pc; } /* Second sequence: A probing loop. - addi 12,1,-<some immediate> - lis 0,-<some immediate> - [possibly ori 0,0,<some immediate>] - add 0,12,0 - cmpw 0,12,0 - beq 0,<disp> - addi 12,12,-<some immediate> - stw 0,0(12) - b <disp> - [possibly one last probe: stw 0,<some immediate>(12)]. */ + addi 12,1,-<some immediate> + lis 0,-<some immediate> + [possibly ori 0,0,<some immediate>] + add 0,12,0 + cmpw 0,12,0 + beq 0,<disp> + addi 12,12,-<some immediate> + stw 0,0(12) + b <disp> + [possibly one last probe: stw 0,<some immediate>(12)]. */ while (1) { /* addi 12,1,-<some immediate> */ if ((op & 0xffff0000) != 0x39810000) - break; + break; /* lis 0,-<some immediate> */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xffff0000) != 0x3c000000) - break; + break; pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); /* [possibly ori 0,0,<some immediate>] */ if ((op & 0xffff0000) == 0x60000000) - { - pc = pc + 4; - op = rs6000_fetch_instruction (gdbarch, pc); - } + { + pc = pc + 4; + op = rs6000_fetch_instruction (gdbarch, pc); + } /* add 0,12,0 */ if (op != 0x7c0c0214) - break; + break; /* cmpw 0,12,0 */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if (op != 0x7c0c0000) - break; + break; /* beq 0,<disp> */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xff9f0001) != 0x41820000) - break; + break; /* addi 12,12,-<some immediate> */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xffff0000) != 0x398c0000) - break; + break; /* stw 0,0(12) */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if (op != 0x900c0000) - break; + break; /* b <disp> */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xfc000001) != 0x48000000) - break; + break; /* [possibly one last probe: stw 0,<some immediate>(12)]. */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xffff0000) == 0x900c0000) - { - pc = pc + 4; - op = rs6000_fetch_instruction (gdbarch, pc); - } + { + pc = pc + 4; + op = rs6000_fetch_instruction (gdbarch, pc); + } /* We found a valid stack-check sequence, return the new PC. */ return pc; @@ -1365,54 +1365,54 @@ rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) limit (saved in a run-time global variable) and the current stack pointer: - addi 0,1,-<some immediate> - lis 12,__gnat_stack_limit@ha - lwz 12,__gnat_stack_limit@l(12) - twllt 0,12 + addi 0,1,-<some immediate> + lis 12,__gnat_stack_limit@ha + lwz 12,__gnat_stack_limit@l(12) + twllt 0,12 or, with a small variant in the case of a bigger stack frame: - addis 0,1,<some immediate> - addic 0,0,-<some immediate> - lis 12,__gnat_stack_limit@ha - lwz 12,__gnat_stack_limit@l(12) - twllt 0,12 + addis 0,1,<some immediate> + addic 0,0,-<some immediate> + lis 12,__gnat_stack_limit@ha + lwz 12,__gnat_stack_limit@l(12) + twllt 0,12 */ while (1) { /* addi 0,1,-<some immediate> */ if ((op & 0xffff0000) != 0x38010000) - { - /* small stack frame variant not recognized; try the - big stack frame variant: */ + { + /* small stack frame variant not recognized; try the + big stack frame variant: */ - /* addis 0,1,<some immediate> */ - if ((op & 0xffff0000) != 0x3c010000) - break; + /* addis 0,1,<some immediate> */ + if ((op & 0xffff0000) != 0x3c010000) + break; - /* addic 0,0,-<some immediate> */ - pc = pc + 4; - op = rs6000_fetch_instruction (gdbarch, pc); - if ((op & 0xffff0000) != 0x30000000) - break; - } + /* addic 0,0,-<some immediate> */ + pc = pc + 4; + op = rs6000_fetch_instruction (gdbarch, pc); + if ((op & 0xffff0000) != 0x30000000) + break; + } /* lis 12,<some immediate> */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xffff0000) != 0x3d800000) - break; + break; /* lwz 12,<some immediate>(12) */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xffff0000) != 0x818c0000) - break; + break; /* twllt 0,12 */ pc = pc + 4; op = rs6000_fetch_instruction (gdbarch, pc); if ((op & 0xfffffffe) != 0x7c406008) - break; + break; /* We found a valid stack-check sequence, return the new PC. */ return pc; @@ -1489,7 +1489,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, for (;; pc += 4) { /* Sometimes it isn't clear if an instruction is a prologue - instruction or not. When we encounter one of these ambiguous + instruction or not. When we encounter one of these ambiguous cases, we'll set prev_insn_was_prologue_insn to 0 (false). Otherwise, we'll assume that it really is a prologue instruction. */ if (prev_insn_was_prologue_insn) @@ -1527,15 +1527,15 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, ones. */ if (lr_reg == -1) lr_reg = (op & 0x03e00000) >> 21; - if (lr_reg == 0) - r0_contains_arg = 0; + if (lr_reg == 0) + r0_contains_arg = 0; continue; } else if ((op & 0xfc1fffff) == 0x7c000026) { /* mfcr Rx */ cr_reg = (op & 0x03e00000) >> 21; - if (cr_reg == 0) - r0_contains_arg = 0; + if (cr_reg == 0) + r0_contains_arg = 0; continue; } @@ -1584,7 +1584,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, continue; } else if (op == 0x60000000) - { + { /* nop */ /* Allow nops in the prologue, but do not consider them to be part of the prologue unless followed by other prologue @@ -1597,7 +1597,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, { /* addis 0,0,NUM, used for >= 32k frames */ fdata->offset = (op & 0x0000ffff) << 16; fdata->frameless = 0; - r0_contains_arg = 0; + r0_contains_arg = 0; continue; } @@ -1605,7 +1605,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, { /* ori 0,0,NUM, 2nd half of >= 32k frames */ fdata->offset |= (op & 0x0000ffff); fdata->frameless = 0; - r0_contains_arg = 0; + r0_contains_arg = 0; continue; } @@ -1684,7 +1684,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, /* If the return address has already been saved, we can skip calls to blrl (for PIC). */ - if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) + if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) { fdata->used_bl = 1; continue; @@ -1759,12 +1759,12 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, continue; /* move parameters from argument registers to local variable - registers */ + registers */ } else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ - (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ - (((op >> 21) & 31) <= 10) && - ((long) ((op >> 16) & 31) + (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ + (((op >> 21) & 31) <= 10) && + ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ { continue; @@ -1773,7 +1773,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, } /* Move parameters from argument registers to temporary register. */ else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) - { + { continue; /* Set up frame pointer */ @@ -1818,28 +1818,28 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ { - vrsave_reg = GET_SRC_REG (op); + vrsave_reg = GET_SRC_REG (op); continue; } else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ - { - continue; - } + { + continue; + } /* Store the register where vrsave was saved to onto the stack: - rS is the register where vrsave was stored in a previous + rS is the register where vrsave was stored in a previous instruction. */ /* 100100 sssss 00001 dddddddd dddddddd */ else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ - { - if (vrsave_reg == GET_SRC_REG (op)) + { + if (vrsave_reg == GET_SRC_REG (op)) { fdata->vrsave_offset = SIGNED_SHORT (op) + offset; vrsave_reg = -1; } - continue; - } + continue; + } /* Compute the new value of vrsave, by modifying the register - where vrsave was saved to. */ + where vrsave was saved to. */ else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ { @@ -1851,22 +1851,22 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, /* 001110 00000 00000 iiii iiii iiii iiii */ /* 001110 01110 00000 iiii iiii iiii iiii */ else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ - || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ + || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ { - if ((op & 0xffff0000) == 0x38000000) - r0_contains_arg = 0; + if ((op & 0xffff0000) == 0x38000000) + r0_contains_arg = 0; li_found_pc = pc; vr_saved_offset = SIGNED_SHORT (op); - /* This insn by itself is not part of the prologue, unless - if part of the pair of insns mentioned above. So do not - record this insn as part of the prologue yet. */ - prev_insn_was_prologue_insn = 0; + /* This insn by itself is not part of the prologue, unless + if part of the pair of insns mentioned above. So do not + record this insn as part of the prologue yet. */ + prev_insn_was_prologue_insn = 0; } /* Store vector register S at (r31+r0) aligned to 16 bytes. */ /* 011111 sssss 11111 00000 00111001110 */ else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ - { + { if (pc == (li_found_pc + 4)) { vr_reg = GET_SRC_REG (op); @@ -1887,16 +1887,16 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, /* Start BookE related instructions. */ /* Store gen register S at (r31+uimm). - Any register less than r13 is volatile, so we don't care. */ + Any register less than r13 is volatile, so we don't care. */ /* 000100 sssss 11111 iiiii 01100100001 */ else if (arch_info->mach == bfd_mach_ppc_e500 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ { - if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ + if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ { - unsigned int imm; + unsigned int imm; ev_reg = GET_SRC_REG (op); - imm = (op >> 11) & 0x1f; + imm = (op >> 11) & 0x1f; ev_offset = imm * 8; /* If this is the first vector reg to be saved, or if it has a lower number than others previously seen, @@ -1907,40 +1907,40 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, fdata->ev_offset = ev_offset + offset; } } - continue; - } + continue; + } /* Store gen register rS at (r1+rB). */ /* 000100 sssss 00001 bbbbb 01100100000 */ else if (arch_info->mach == bfd_mach_ppc_e500 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ { - if (pc == (li_found_pc + 4)) - { - ev_reg = GET_SRC_REG (op); + if (pc == (li_found_pc + 4)) + { + ev_reg = GET_SRC_REG (op); /* If this is the first vector reg to be saved, or if - it has a lower number than others previously seen, - reupdate the frame info. */ - /* We know the contents of rB from the previous instruction. */ + it has a lower number than others previously seen, + reupdate the frame info. */ + /* We know the contents of rB from the previous instruction. */ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) { - fdata->saved_ev = ev_reg; - fdata->ev_offset = vr_saved_offset + offset; + fdata->saved_ev = ev_reg; + fdata->ev_offset = vr_saved_offset + offset; } vr_saved_offset = -1; ev_reg = -1; li_found_pc = 0; - } - continue; - } + } + continue; + } /* Store gen register r31 at (rA+uimm). */ /* 000100 11111 aaaaa iiiii 01100100001 */ else if (arch_info->mach == bfd_mach_ppc_e500 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ - { - /* Wwe know that the source register is 31 already, but - it can't hurt to compute it. */ + { + /* Wwe know that the source register is 31 already, but + it can't hurt to compute it. */ ev_reg = GET_SRC_REG (op); - ev_offset = ((op >> 11) & 0x1f) * 8; + ev_offset = ((op >> 11) & 0x1f) * 8; /* If this is the first vector reg to be saved, or if it has a lower number than others previously seen, reupdate the frame info. */ @@ -1953,21 +1953,21 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, continue; } /* Store gen register S at (r31+r0). - Store param on stack when offset from SP bigger than 4 bytes. */ + Store param on stack when offset from SP bigger than 4 bytes. */ /* 000100 sssss 11111 00000 01100100000 */ else if (arch_info->mach == bfd_mach_ppc_e500 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ { - if (pc == (li_found_pc + 4)) - { - if ((op & 0x03e00000) >= 0x01a00000) + if (pc == (li_found_pc + 4)) + { + if ((op & 0x03e00000) >= 0x01a00000) { ev_reg = GET_SRC_REG (op); /* If this is the first vector reg to be saved, or if it has a lower number than others previously seen, reupdate the frame info. */ - /* We know the contents of r0 from the previous - instruction. */ + /* We know the contents of r0 from the previous + instruction. */ if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) { fdata->saved_ev = ev_reg; @@ -1978,7 +1978,7 @@ skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, vr_saved_offset = -1; li_found_pc = 0; continue; - } + } } /* End BookE related instructions. */ @@ -2117,10 +2117,10 @@ rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); /* We check for ___eabi (three leading underscores) in addition - to __eabi in case the GCC option "-fleading-underscore" was + to __eabi in case the GCC option "-fleading-underscore" was used to compile the program. */ if (s.minsym != NULL - && s.minsym->linkage_name () != NULL + && s.minsym->linkage_name () != NULL && (strcmp (s.minsym->linkage_name (), "__eabi") == 0 || strcmp (s.minsym->linkage_name (), "___eabi") == 0)) pc += 4; @@ -2538,9 +2538,9 @@ rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, static int rs6000_register_to_value (struct frame_info *frame, - int regnum, - struct type *type, - gdb_byte *to, + int regnum, + struct type *type, + gdb_byte *to, int *optimizedp, int *unavailablep) { struct gdbarch *gdbarch = get_frame_arch (frame); @@ -2561,9 +2561,9 @@ rs6000_register_to_value (struct frame_info *frame, static void rs6000_value_to_register (struct frame_info *frame, - int regnum, - struct type *type, - const gdb_byte *from) + int regnum, + struct type *type, + const gdb_byte *from) { struct gdbarch *gdbarch = get_frame_arch (frame); gdb_byte to[PPC_MAX_REGISTER_SIZE]; @@ -3182,23 +3182,23 @@ rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) switch (num) { case 64: - return tdep->ppc_mq_regnum; + return tdep->ppc_mq_regnum; case 65: - return tdep->ppc_lr_regnum; + return tdep->ppc_lr_regnum; case 66: - return tdep->ppc_ctr_regnum; + return tdep->ppc_ctr_regnum; case 76: - return tdep->ppc_xer_regnum; + return tdep->ppc_xer_regnum; case 109: - return tdep->ppc_vrsave_regnum; + return tdep->ppc_vrsave_regnum; case 110: - return tdep->ppc_vrsave_regnum - 1; /* vscr */ + return tdep->ppc_vrsave_regnum - 1; /* vscr */ case 111: - return tdep->ppc_acc_regnum; + return tdep->ppc_acc_regnum; case 112: - return tdep->ppc_spefscr_regnum; + return tdep->ppc_spefscr_regnum; default: - return num; + return num; } } @@ -3226,23 +3226,23 @@ rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) case 64: return tdep->ppc_cr_regnum; case 67: - return tdep->ppc_vrsave_regnum - 1; /* vscr */ + return tdep->ppc_vrsave_regnum - 1; /* vscr */ case 99: - return tdep->ppc_acc_regnum; + return tdep->ppc_acc_regnum; case 100: - return tdep->ppc_mq_regnum; + return tdep->ppc_mq_regnum; case 101: - return tdep->ppc_xer_regnum; + return tdep->ppc_xer_regnum; case 108: - return tdep->ppc_lr_regnum; + return tdep->ppc_lr_regnum; case 109: - return tdep->ppc_ctr_regnum; + return tdep->ppc_ctr_regnum; case 356: - return tdep->ppc_vrsave_regnum; + return tdep->ppc_vrsave_regnum; case 612: - return tdep->ppc_spefscr_regnum; + return tdep->ppc_spefscr_regnum; default: - return num; + return num; } } @@ -3500,7 +3500,7 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) if (safe_read_memory_unsigned_integer (cache->base, wordsize, byte_order, &backchain)) - cache->base = (CORE_ADDR) backchain; + cache->base = (CORE_ADDR) backchain; } trad_frame_set_value (cache->saved_regs, @@ -3515,15 +3515,15 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; /* If skip_prologue says floating-point registers were saved, - but the current architecture has no floating-point registers, - then that's strange. But we have no indices to even record - the addresses under, so we just ignore it. */ + but the current architecture has no floating-point registers, + then that's strange. But we have no indices to even record + the addresses under, so we just ignore it. */ if (ppc_floating_point_unit_p (gdbarch)) - for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) - { - cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; - fpr_addr += 8; - } + for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) + { + cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; + fpr_addr += 8; + } } /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. @@ -5431,7 +5431,7 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, { case 0: /* VSX Scalar Extract Exponent Double-Precision */ case 1: /* VSX Scalar Extract Significand Double-Precision */ - record_full_arch_list_add_reg (regcache, + record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + PPC_RT (insn)); return 0; case 16: /* VSX Scalar Convert Half-Precision format to @@ -5688,7 +5688,7 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, case 583: switch (PPC_FIELD (insn, 11, 5)) - { + { case 1: /* Move From FPSCR & Clear Enables */ case 20: /* Move From FPSCR Control & set DRN */ case 21: /* Move From FPSCR Control & set DRN Immediate */ @@ -5704,7 +5704,7 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, tdep->ppc_fp0_regnum + PPC_FRT (insn)); return 0; - } + } break; case 8: /* Floating Copy Sign */ @@ -6018,7 +6018,7 @@ ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, case 57: switch (insn & 0x3) - { + { case 0: /* Load Floating-Point Double Pair */ tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); record_full_arch_list_add_reg (regcache, tmp); @@ -6760,9 +6760,9 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) if (elf_abi == POWERPC_ELF_AUTO) { if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) - elf_abi = POWERPC_ELF_V2; + elf_abi = POWERPC_ELF_V2; else - elf_abi = POWERPC_ELF_V1; + elf_abi = POWERPC_ELF_V1; } if (soft_float_flag == AUTO_BOOLEAN_TRUE) @@ -6804,8 +6804,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) arches = gdbarch_list_lookup_by_info (arches->next, &info)) { /* Word size in the various PowerPC bfd_arch_info structs isn't - meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform - separate word size check. */ + meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform + separate word size check. */ tdep = gdbarch_tdep (arches->gdbarch); if (tdep && tdep->elf_abi != elf_abi) continue; |