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* Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay2017-06-301-0/+5
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-301-0/+3
* [AArch64] Add dot product support for AArch64 to binutilsTamar Christina2017-06-281-0/+2
* [ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2017-06-281-1/+4
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-281-5/+16
* [ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme2017-06-241-1/+6
* [ARM] Remove ARMv6S-M special casingThomas Preud'homme2017-06-241-5/+7
* [ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme2017-06-211-0/+1
* S/390: Improve error checking for optional operandsAndreas Krebbel2017-05-301-3/+4
* S/390: Remove optional operand flag.Andreas Krebbel2017-05-301-10/+6
* [ARC] Update MAX_INSN_FLGS.claziss2017-05-231-1/+1
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-221-0/+1
* binutils: support for the SPARC M8 processorJose E. Marchesi2017-05-191-2/+23
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-151-5/+34
* Fix match and mask for 64-bit bb opcode.John David Anglin2017-05-141-1/+1
* [ARC] Object attributes.Claudiu Zissulescu2017-05-102-62/+98
* Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra2017-04-111-43/+46
* Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra2017-04-111-5/+0
* Bye Bye PPC_OPCODE_VSX3Alan Modra2017-04-111-3/+0
* Bye bye PPC_OPCODE_ALTIVEC2Alan Modra2017-04-111-3/+0
* RISC-V: Add physical memory protection CSRsAndrew Waterman2017-03-311-0/+40
* Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet2017-03-301-0/+226
* PowerPC -Mraw disassemblyAlan Modra2017-03-291-37/+43
* Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig2017-03-271-6/+8
* S/390: Remove vx2 facility flagAndreas Krebbel2017-03-211-2/+1
* arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig2017-03-211-0/+1
* [AArch64] Additional SVE instructionsRichard Sandiford2017-02-241-0/+6
* [AArch64] Add a "compnum" featureRichard Sandiford2017-02-241-1/+3
* Add new counter-enable CSRsAndrew Waterman2017-02-241-0/+4
* S/390: Add support for new cpu architecture - arch12.Andreas Krebbel2017-02-231-1/+4
* opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo2017-02-231-1/+9
* Add SFENCE.VMA instructionAndrew Waterman2017-02-151-0/+3
* PowerPC register expression checksAlan Modra2017-02-141-70/+78
* [ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu2017-02-061-1/+23
* Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov2017-01-256-6/+6
* [AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2017-01-041-1/+3
* Add support for the Q extension to the RISCV ISA.Kito Cheng2017-01-032-0/+104
* Update year range in copyright notice of all files.Alan Modra2017-01-0270-70/+70
* PRU BFD supportDimitar Dimitrov2016-12-311-0/+411
* MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2016-12-231-2/+8
* MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2016-12-231-5/+5
* MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2016-12-231-0/+4
* Remove high bit set charactersAlan Modra2016-12-211-8/+8
* MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2016-12-201-0/+8
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-131-3/+3
* MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2016-12-091-2/+1
* MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki2016-12-071-1/+1
* MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki2016-12-071-0/+1
* [ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2016-12-051-0/+4
* [ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2016-11-291-0/+5
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