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* RISC-V/zfh: Add half-precision floating-point v0.1 instructions.Nelson Chu2021-07-222-0/+116
* RISC-V/rvv: Add rvv v0.10 instructions.Nelson Chu2021-07-222-1/+1448
* RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions.Nelson Chu2021-07-222-4/+30
* Add markers for 2.37 branchNick Clifton2021-07-031-0/+4
* Synchronize libiberty sources (and include/demangle.h) with GCC master versionNick Clifton2021-07-032-0/+12
* opcodes: constify aarch64_opcode_tablesMike Frysinger2021-07-012-1/+5
* arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw2021-07-012-1/+6
* sim: callback: add printf attributesMike Frysinger2021-06-292-4/+13
* sim: callback: extend syscall interface to handle 7 argsMike Frysinger2021-06-242-1/+6
* sim: callback: add a kill interfaceMike Frysinger2021-06-232-0/+5
* sim: callback: add a getpid interfaceMike Frysinger2021-06-222-0/+5
* elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXXH.J. Lu2021-06-182-0/+17
* Allow readelf to recognise GO buildid notes.Nick Clifton2021-06-152-0/+5
* arc: Construct disassembler options dynamicallyShahab Vahedi2021-06-022-0/+5
* MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2021-05-292-19/+24
* MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2021-05-292-4/+27
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-292-2/+15
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-292-2/+6
* x86: Restore PC16 relocation overflow checkH.J. Lu2021-05-282-1/+5
* x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu2021-05-262-0/+6
* elf: Use official name LoongArch for EM_LOONGARCH.Chenghua Xu2021-05-232-1/+6
* [AArch64] MTE corefile supportLuis Machado2021-05-212-0/+11
* sim: callback: convert FS interfaces to 64-bitMike Frysinger2021-05-142-3/+8
* sim: callback: convert time interface to 64-bitMike Frysinger2021-05-142-1/+8
* sim: callback: inline PTR defineMike Frysinger2021-05-142-3/+8
* sim: callback: use ATTRIBUTE_NORETURNMike Frysinger2021-05-142-5/+5
* sim: callback: always include necessary headersMike Frysinger2021-05-142-4/+4
* sim: create header namespaceMike Frysinger2021-05-144-5/+14
* Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on X...Cl?ment Chigot2021-05-073-0/+10
* libiberty: add htab_eq_stringTom Tromey2021-05-071-0/+3
* or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2021-05-062-0/+6
* libctf, include: support an alternative encoding for nonrepresentable typesNick Alcock2021-05-063-1/+9
* Harmonize and improve auxiliary entries support for XCOFFCl?ment Chigot2021-04-224-101/+117
* Extend the description of PE header flags.Eli Zaretskii2021-04-212-0/+8
* PR27567, Linking PE files adds alignment section flags to executablesAlan Modra2021-04-165-8/+25
* PowerPC disassembly of pcrel referencesAlan Modra2021-04-092-0/+8
* Return symbol from symbol_at_address_funcAlan Modra2021-04-062-5/+10
* Remove strneq macro and use startswith.Martin Liska2021-04-012-1/+4
* Use bool in includeAlan Modra2021-03-3112-77/+89
* Remove bfd_stdint.hAlan Modra2021-03-317-11/+17
* TRUE/FALSE simplificationAlan Modra2021-03-292-7/+11
* opcodes int vs bfd_boolean fixesAlan Modra2021-03-292-1/+5
* include: always do unsigned left-shift in CTF_SET_STIDNick Alcock2021-03-252-8/+15
* AArch64: Add MTE register set support for GDB and gdbserverLuis Machado2021-03-241-0/+3
* elf: Rename EM_INTEL205 to EM_INTELGTH.J. Lu2021-03-192-1/+6
* Fix a potential buffer overrun qwhen writing out PE aux entries.Nick Clifton2021-03-162-2/+7
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-163-0/+112
* Add values for NetBSD .note.netbsd.ident notes (PaX).Frederic Cambus2021-03-122-0/+15
* aix: implement TLS relocation for gas and ldClément Chigot2021-03-125-51/+93
* aix: correct HOWTO table and add missing relocationsClément Chigot2021-03-122-27/+31
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