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* Support ptwriteusers/hjl/ptwriteH.J. Lu2016-08-231-0/+6
* x86: allow suffix-less movzw and 64-bit movzbJan Beulich2016-07-011-12/+3
* x86: remove stray instruction attributesJan Beulich2016-07-011-44/+44
* x86/Intel: fix operand checking for MOVSDJan Beulich2016-07-011-2/+2
* Handle indirect branches for AMD64 and Intel64H.J. Lu2016-06-031-2/+4
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-4/+4
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-0/+7
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-0/+7
* Add support for monitorx/mwaitx instructionsAmit Pawar2015-06-301-0/+13
* x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich2015-06-011-0/+6
* Remove Disp32 from AMD64 direct call/jmpH.J. Lu2015-05-181-2/+2
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-151-2/+4
* Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu2015-05-111-2/+3
* Add znver1 processorGanesh Gopalasubramanian2015-03-171-0/+7
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-0/+17
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-0/+11
* Add pcommit instructionIlya Tocar2014-11-171-0/+6
* Add clwb instructionIlya Tocar2014-11-171-0/+6
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-0/+212
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-0/+385
* Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar2014-07-221-0/+20
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-0/+944
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-0/+7
* Fix memory size for gather/scatter instructionsIlya Tocar2014-03-201-8/+8
* Update copyright yearsAlan Modra2014-03-051-2/+1
* Remove bogus vcvtps2ph variant.Ilya Tocar2014-02-251-1/+0
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-2/+6
* Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar2014-02-201-4/+3
* Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar2014-02-121-0/+22
* Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu2013-10-121-8/+11
* opcodes/Jan Beulich2013-10-081-9/+9
* Add Size64 to movq/vmovq with Reg64 operandH.J. Lu2013-09-301-8/+8
* Add Intel AVX-512 supportH.J. Lu2013-07-261-0/+1209
* Support Intel SHAH.J. Lu2013-07-251-0/+10
* Support Intel MPXH.J. Lu2013-07-241-41/+54
* Replace Xmmword with Qword on cvttps2piH.J. Lu2013-07-081-1/+1
* gas/testsuite/Jan Beulich2013-04-081-2/+1
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-0/+4
* Fix opcode for 64-bit jecxzH.J. Lu2012-11-201-1/+1
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-1/+1
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-1/+1
* There were several cases where the registers in the REX encoded rangeJan Beulich2012-08-071-5/+0
* VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich2012-07-311-1/+1
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-1/+6
* gas/testsuite/Roland McGrath2012-07-021-1/+1
* gas/Roland McGrath2012-06-221-4/+4
* gas/Roland McGrath2012-06-221-56/+56
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-40/+51
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