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* aarch64: Add support for MPAM system registersAlex Coplan2020-08-122-0/+21
* Updated Serbian and Russian translations for various sub-directoriesNick Clifton2020-08-122-244/+318
* PowerPC CELL cctp*Alan Modra2020-08-112-4/+11
* [aarch64] GAS doesn't validate the architecture version for any tlbi register...Przemyslaw Wirkus2020-08-102-102/+105
* Implement missing powerpc mtspr and mfspr extended insnsAlan Modra2020-08-102-6/+161
* Implement missing powerpc extended mnemonicsAlan Modra2020-08-102-7/+16
* Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra2020-08-102-2/+7
* Z8k: fix sout/soudb opcodes with direct addressChristian Groessler2020-08-043-6/+13
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-304-20/+61
* PR26279 Work around maybe-uninitialized warning in s390-mkopc.cAndreas Arnez2020-07-292-1/+8
* Updated German translation for the opcodes sub-directoryNick Clifton2020-07-242-245/+319
* Revert "x86: Don't display eiz with no scale"Jan Beulich2020-07-212-1/+5
* x86: Don't display eiz with no scaleH.J. Lu2020-07-152-1/+7
* x86: move putop() case labels to restore alphabetic sortingJan Beulich2020-07-152-49/+52
* x86: make PUSH/POP disassembly uniformJan Beulich2020-07-152-30/+27
* x86: avoid attaching suffixes to unambiguous insnsJan Beulich2020-07-152-99/+58
* x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu2020-07-142-2/+13
* arc: Detect usage of illegal double register pairsClaudiu Zissulescu2020-07-142-3/+16
* x86/Intel: debug registers are named DRnJan Beulich2020-07-142-1/+5
* x86: drop Rm and the 'L' macroJan Beulich2020-07-142-74/+67
* x86: drop Rdq, Rd, and MaskRJan Beulich2020-07-146-63/+122
* x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich2020-07-142-135/+61
* x86: also use %BW / %DQ for kshift*Jan Beulich2020-07-142-65/+35
* x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich2020-07-148-4913/+1647
* x86: drop further EVEX table entries that can be served by VEX onesJan Beulich2020-07-144-42/+25
* x86: drop need_vex_regJan Beulich2020-07-143-53/+41
* x86: drop Vex128 and Vex256Jan Beulich2020-07-143-56/+65
* x86: replace %LW by %DQJan Beulich2020-07-144-52/+59
* x86: merge/move logic determining the EVEX disp8 shiftJan Beulich2020-07-142-29/+23
* x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich2020-07-144-24/+22
* x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich2020-07-144-43/+35
* x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich2020-07-144-74/+58
* x86: don't disassemble MOVBE with two suffixesJan Beulich2020-07-142-43/+11
* x86: avoid attaching suffix to register-only CRC32Jan Beulich2020-07-142-75/+7
* x86-64: don't hide an empty but meaningless REX prefixJan Beulich2020-07-142-5/+14
* x86: drop dead code from OP_IMREG()Jan Beulich2020-07-142-40/+14
* x86: Add support for Intel AMX instructionsLili Cui2020-07-108-14326/+15063
* x86: various XOP insns lack L and/or W bit decodingJan Beulich2020-07-082-123/+630
* x86: FMA4 scalar insns ignore VEX.LJan Beulich2020-07-084-101/+58
* x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich2020-07-082-74/+32
* x86: re-work operand handling for 5-operand XOP insnsJan Beulich2020-07-082-194/+19
* x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich2020-07-082-65/+49
* arc: Update vector instructions.Claudiu Zissulescu2020-07-073-77/+103
* x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich2020-07-074-77/+27
* x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich2020-07-062-12/+48
* x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich2020-07-064-192/+77
* x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich2020-07-065-24/+90
* x86: adjust/correct V*{F,I}{32x8,64x4}Jan Beulich2020-07-062-14/+22
* x86: drop EVEX table entries that can be made served by VEX onesJan Beulich2020-07-065-165/+92
* x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich2020-07-065-4/+47
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