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* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-083-2/+7
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-085-5237/+5098
* x86: fold several AVX512VL templatesJan Beulich2018-03-084-2052/+357
* x86: fold certain AVX512 rotate and shift templatesJan Beulich2018-03-083-954/+142
* x86: fold VEX-encoded GFNI templatesJan Beulich2018-03-083-86/+21
* x86: fold a few AVX512F templatesJan Beulich2018-03-083-240/+31
* x86: fold LWP templatesJan Beulich2018-03-083-86/+20
* x86: fold FMA and FMA4 templatesJan Beulich2018-03-083-1656/+330
* x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich2018-03-083-2/+7
* x86: drop bogus NoAVXJan Beulich2018-03-083-14/+20
* x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich2018-03-083-4/+9
* x86: drop FloatDJan Beulich2018-03-085-19738/+19743
* x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2018-03-082-8/+12
* x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich2018-03-083-6/+11
* x86: fold AVX vcvtpd2ps memory formsJan Beulich2018-03-083-20/+8
* XCOFF disassemblerAlan Modra2018-03-074-20/+19
* opcodes error messagesAlan Modra2018-03-0378-867/+1218
* x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu2018-03-013-24/+30
* Add missing translations to ALL_LINGUASAlan Modra2018-03-013-2/+7
* [ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme2018-02-272-2/+7
* x86: Add -O[2|s] assembler command-line optionsH.J. Lu2018-02-275-5354/+5388
* crx string overflow warningAlan Modra2018-02-262-1/+6
* RISC-V: Make disassebler work for --enable-targets=all config.Jim Wilson2018-02-222-0/+5
* x86: Add {rex} pseudo prefixH.J. Lu2018-02-223-0/+20
* MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki2018-02-202-2/+6
* [ARM] Fix bxns maskThomas Preud'homme2018-02-192-1/+5
* Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton2018-02-132-3/+13
* WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2018-02-132-3/+8
* MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong2018-02-122-1/+5
* Updated Brazillian portuguese and Russian translationNick Clifton2018-02-052-2/+6
* Enable Intel PCONFIG instruction.Igor Tsimbalist2018-01-237-5483/+5529
* Enable Intel WBNOINVD instruction.Igor Tsimbalist2018-01-237-5483/+5535
* RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2018-01-172-1/+5
* Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist2018-01-176-5557/+5602
* Update translations for various binutils components.Nick Clifton2018-01-163-596/+2117
* RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2018-01-152-0/+13
* Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton2018-01-152-407/+444
* Update pot filesNick Clifton2018-01-132-371/+407
* Bump version number to 2.30.51Nick Clifton2018-01-132-10/+14
* Add note about 2.30 branch creation to changelogsNick Clifton2018-01-131-0/+4
* Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist2018-01-113-172/+5
* x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich2018-01-103-4/+9
* x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich2018-01-103-96/+106
* RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2018-01-092-1/+6
* [Arm] Add CSDB instructionJames Greenhalgh2018-01-092-0/+11
* Add support for the AArch64's CSDB instruction.James Greenhalgh2018-01-095-1012/+1022
* x86: Properly encode vmovd with 64-bit memeoryH.J. Lu2018-01-083-42/+13
* RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson2018-01-052-0/+7
* Update year range in copyright notice of binutils filesAlan Modra2018-01-03277-280/+284
* ChangeLog rotationAlan Modra2018-01-032-1965/+1979
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