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* MAINTAINERS: Update my company e-mail addressMaciej W. Rozycki2018-01-222-1/+5
* Fix compile time warning (in the ARM simulator) about a print statement with ...Nick Clifton2018-01-022-1/+7
* Update copyright year range in all GDB filesJoel Brobecker2018-01-02618-618/+618
* sim: testsuite: add testsuite for or1k simPeter Gavin2017-12-1228-0/+6510
* sim: or1k: add autoconf generated filesStafford Horne2017-12-125-0/+16427
* sim: or1k: add cgen generated filesStafford Horne2017-12-1211-0/+27536
* sim: or1k: add or1k target to simStafford Horne2017-12-1211-0/+1637
* sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])Peter Gavin2017-12-122-0/+25
* sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])Peter Gavin2017-12-125-5/+149
* FT32: support for FT32B processor - part 2/2James Bowman2017-11-012-7/+19
* FT32: support for FT32B processor - part 1James Bowman2017-10-122-7/+15
* Add myself as ft32 maintainer for sim.James Bowman2017-10-122-0/+5
* Update my email address.Jim Wilson2017-10-032-1/+5
* [SIM, ARM] Fix build failureYao Qi2017-09-212-1/+8
* Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin2017-09-0659-202/+434
* Define an error function in the PPC simulator library.John Baldwin2017-09-042-0/+15
* Fix simulatorAnthony Green2017-09-042-7/+16
* Fix simulation of MSP430's open system call.Jozef Lawrynowicz2017-08-292-10/+30
* Correct check for endiannessMichael Eager2017-06-022-1/+5
* Refactor disassembler selectionYao Qi2017-05-242-1/+9
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-2214-202/+454
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-084-0/+112
* Support the fcmXX zero instructions.Jim Wilson2017-04-084-0/+232
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-254-1/+27
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-035-9/+89
* Add missing smov support, and clean up existing umov support.Jim Wilson2017-02-254-75/+227
* Add missing cnt (popcount) instruction support.Jim Wilson2017-02-254-0/+94
* Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2017-02-198-36/+157
* Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2017-02-146-49/+128
* Fix bit/bif instructions.Jim Wilson2017-02-144-10/+107
* Add ldn/stn single support, fix ldnr support.Jim Wilson2017-02-146-269/+698
* sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger2017-02-1339-62/+141
* Add support for cmtst.Jim Wilson2017-01-234-0/+113
* Fixes for addv and xtn2 instructions.Jim Wilson2017-01-175-31/+158
* Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2017-01-094-17/+273
* Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson2017-01-049-33/+618
* update copyright year range in GDB filesJoel Brobecker2017-01-01576-576/+576
* Fix bugs with float compare and Inf operands.Jim Wilson2016-12-214-0/+184
* MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2016-12-142-0/+6
* Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2016-12-137-45/+309
* Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2016-12-032-3/+8
* Fix typo in ChangeLog entry.Jim Wilson2016-12-011-1/+1
* Fix bug with FP stur instructions.Jim Wilson2016-12-012-6/+11
* sim: mips: add PR info to ChangeLogMike Frysinger2016-11-121-0/+2
* sim: mips: fix dv-tx3904cpu build errorMike Frysinger2016-11-112-0/+10
* sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2016-11-112-0/+5
* sim: avr: move changelog entries to subdirMike Frysinger2016-10-182-7/+7
* sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2016-08-162-25/+34
* sim: unify symbol table handlingMike Frysinger2016-08-1517-170/+164
* sim: m68hc11: standardize sim_cpu namingMike Frysinger2016-08-1310-347/+366