From f5b57feac2389eba64bea45f0115474fbbb13d8e Mon Sep 17 00:00:00 2001
From: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu, 30 Mar 2023 11:09:10 +0100
Subject: aarch64: Add support for strided register lists

SME2 has instructions that accept strided register lists,
such as { z0.s, z4.s, z8.s, z12.s }.  The purpose of this
patch is to extend binutils to support such lists.

The parsing code already had (unused) support for strides of 2.
The idea here is instead to accept all strides during parsing
and reject invalid strides during constraint checking.

The SME2 instructions that accept strided operands also have
non-strided forms.  The errors about invalid strides therefore
take a bitmask of acceptable strides, which allows multiple
possibilities to be summed up in a single message.

I've tried to update all code that handles register lists.
---
 include/opcode/aarch64.h | 38 ++++++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 12 deletions(-)

(limited to 'include')

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 61afe561a12..ef59d531d17 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1122,6 +1122,19 @@ struct aarch64_indexed_za
   unsigned v : 1;	/* <HV> horizontal or vertical vector indicator.  */
 };
 
+/* Information about a list of registers.  */
+struct aarch64_reglist
+{
+  unsigned first_regno : 8;
+  unsigned num_regs : 8;
+  /* The difference between the nth and the n+1th register.  */
+  unsigned stride : 8;
+  /* 1 if it is a list of reg element.  */
+  unsigned has_index : 1;
+  /* Lane index; valid only when has_index is 1.  */
+  int64_t index;
+} reglist;
+
 /* Structure representing an operand.  */
 
 struct aarch64_opnd_info
@@ -1142,15 +1155,7 @@ struct aarch64_opnd_info
 	  int64_t index;
 	} reglane;
       /* e.g. LVn.  */
-      struct
-	{
-	  unsigned first_regno : 5;
-	  unsigned num_regs : 3;
-	  /* 1 if it is a list of reg element.  */
-	  unsigned has_index : 1;
-	  /* Lane index; valid only when has_index is 1.  */
-	  int64_t index;
-	} reglist;
+      struct aarch64_reglist reglist;
       /* e.g. immediate or pc relative address offset.  */
       struct
 	{
@@ -1288,11 +1293,19 @@ struct aarch64_inst
    The following errors are only reported against an asm string that is
    syntactically valid and that has valid operand qualifiers.
 
-   AARCH64_OPDE_REG_LIST
-     Error about the register list operand having an unexpected number of
+   AARCH64_OPDE_REG_LIST_LENGTH
+     Error about a register list operand having an unexpected number of
      registers.  This error is low severity because there might be another
      opcode entry that supports the given number of registers.
 
+   AARCH64_OPDE_REG_LIST_STRIDE
+     Error about a register list operand having the correct number
+     (and type) of registers, but an unexpected stride.  This error is
+     more severe than AARCH64_OPDE_REG_LIST_LENGTH because it implies
+     that the length is known to be correct.  However, it is lower than
+     many other errors, since some instructions have forms that share
+     the same number of registers but have different strides.
+
    AARCH64_OPDE_UNTIED_IMMS
      The asm failed to use the same immediate for a destination operand
      and a tied source operand.
@@ -1342,7 +1355,8 @@ enum aarch64_operand_error_kind
   AARCH64_OPDE_SYNTAX_ERROR,
   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
   AARCH64_OPDE_INVALID_VARIANT,
-  AARCH64_OPDE_REG_LIST,
+  AARCH64_OPDE_REG_LIST_LENGTH,
+  AARCH64_OPDE_REG_LIST_STRIDE,
   AARCH64_OPDE_UNTIED_IMMS,
   AARCH64_OPDE_UNTIED_OPERAND,
   AARCH64_OPDE_OUT_OF_RANGE,
-- 
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