From 4a306116670c5747b682948e0fd3f9a62051c7c6 Mon Sep 17 00:00:00 2001
From: Dave Brolley <brolley@redhat.com>
Date: Fri, 29 Aug 2003 16:41:31 +0000
Subject: New sim testsuite for Fujitsu FRV. Contributed by Red Hat.

---
 sim/testsuite/sim/frv/cld.cgs | 126 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)
 create mode 100644 sim/testsuite/sim/frv/cld.cgs

(limited to 'sim/testsuite/sim/frv/cld.cgs')

diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs
new file mode 100644
index 00000000000..62e1324a22b
--- /dev/null
+++ b/sim/testsuite/sim/frv/cld.cgs
@@ -0,0 +1,126 @@
+# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond
+# mach: all
+
+	.include "testutils.inc"
+
+	start
+
+	.global cld
+cld:
+	set_spr_immed	0x1b1b,cccr
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc0,1
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc0,1
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc4,1
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc0,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc0,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc4,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc1,0
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc1,0
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc5,0
+	test_gr_limmed	0xdead,0xbeef,gr8
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc1,1
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc1,1
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc5,1
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc2,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc2,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc6,1
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_mem_limmed	0xdead,0xbeef,sp
+	set_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_immed	0,gr7
+	cld 		@(sp,gr7),gr8,cc3,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	-4,sp
+	set_gr_immed	4,gr7
+	cld 		@(sp,gr7),gr8,cc3,0
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	set_gr_limmed	0xbeef,0xdead,gr8
+	inc_gr_immed	8,sp
+	set_gr_immed	-4,gr7
+	cld 		@(sp,gr7),gr8,cc7,1
+	test_gr_limmed	0xbeef,0xdead,gr8
+
+	pass
-- 
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