1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
|
# Hitachi H8 testcase 'exts.w, extu.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 2
pos: .word 0xff01
neg: .word 0x0080
.text
exts_w_reg16_p:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #1, r0l
exts.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a50001 er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
exts_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #0xff, r0l
exts.w r0
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5ffff er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
extu_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w rn16
mov.b #0xff, r0l
extu.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a500ff er0 ; result of zero extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
exts_w_ind_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #pos, er1
exts.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswindp
fail
.Lswindp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #neg, er1
exts.w @er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswindn
fail
.Lswindn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern
mov.l #neg, er1
extu.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwindn
fail
.Luwindn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #pos, er1
exts.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostincp
fail
.Lswpostincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #neg, er1
exts.w @er1+
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostincn
fail
.Lswpostincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern+
mov.l #neg, er1
extu.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostincn
fail
.Luwpostincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postdec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #pos, er1
exts.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostdecp
fail
.Lswpostdecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #neg, er1
exts.w @er1-
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostdecn
fail
.Lswpostdecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern-
mov.l #neg, er1
extu.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostdecn
fail
.Luwpostdecn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_preinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #pos-2, er1
exts.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpreincp
fail
.Lswpreincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #neg-2, er1
exts.w @+er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpreincn
fail
.Lswpreincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @+ern
mov.l #neg-2, er1
extu.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpreincn
fail
.Luwpreincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_predec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #pos+2, er1
exts.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpredecp
fail
.Lswpredecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #neg+2, er1
exts.w @-er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpredecn
fail
.Lswpredecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @-ern
mov.l #neg+2, er1
extu.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpredecn
fail
.Luwpredecn:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp2_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:2, ern)
mov.l #neg-1, er1
extu.w @(1:2, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-1 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp2n
fail
.Luwdisp2n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:16, ern)
mov.l #neg-44, er1
extu.w @(44:16, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-44 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp16n
fail
.Luwdisp16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:32, ern)
mov.l #neg+444, er1
extu.w @(-444:32, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+444 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp32n
fail
.Luwdisp32n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:16
extu.w @neg:16
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs16n
fail
.Luwabs16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:32
extu.w @neg:32
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs32n
fail
.Luwabs32n:
;; Note: leave the value as 0x0080, like it started out.
.endif
pass
exit 0
|
