* config/tc-mips.c (append_insn): Remove cop_interlocks test from

	branch delay code.

10 files changed, 1497 insertions, 304 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 160fb722b2..d020a8f551 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
 
+	* config/tc-mips.c (append_insn): Remove cop_interlocks test from
+	branch delay code.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
 	* config/tc-mips.h (mips_flush_pending_output): Delete.
 	(mips_emit_delays): Declare.
 	(md_flush_pending_output): Use mips_emit_delays.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 021dd4030b..c16125bf13 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -557,9 +557,14 @@ static int mips_optimize = 2;
    equivalent to seeing no -g option at all.  */
 static int mips_debug = 0;
 
-/* The maximum number of NOPs needed to satisfy a hardware hazard
-   or processor errata.  */
-#define MAX_NOPS 2
+/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata.  */
+#define MAX_VR4130_NOPS 4
+
+/* The maximum number of NOPs needed to fill delay slots.  */
+#define MAX_DELAY_NOPS 2
+
+/* The maximum number of NOPs needed for any purpose.  */
+#define MAX_NOPS 4
 
 /* A list of previous instructions, with index 0 being the most recent.
    We need to look back MAX_NOPS instructions when filling delay slots
@@ -659,6 +664,9 @@ static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
 /* True if -mfix-vr4120 is in force.  */
 static int mips_fix_vr4120;
 
+/* ...likewise -mfix-vr4130.  */
+static int mips_fix_vr4130;
+
 /* We don't relax branches by default, since this causes us to expand
    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
    fail to compute the offset before expanding the macro to the most
@@ -2011,6 +2019,48 @@ insns_between (const struct mips_cl_insn *insn1,
   return 0;
 }
 
+/* Return the number of nops that would be needed to work around the
+   VR4130 mflo/mfhi errata if instruction INSN immediately followed
+   the MAX_VR4130_NOPS instructions described by HISTORY.  */
+
+static int
+nops_for_vr4130 (const struct mips_cl_insn *history,
+		 const struct mips_cl_insn *insn)
+{
+  int i, j, reg;
+
+  /* Check if the instruction writes to HI or LO.  MTHI and MTLO
+     are not affected by the errata.  */
+  if (insn != 0
+      && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
+	  || strcmp (insn->insn_mo->name, "mtlo") == 0
+	  || strcmp (insn->insn_mo->name, "mthi") == 0))
+    return 0;
+
+  /* Search for the first MFLO or MFHI.  */
+  for (i = 0; i < MAX_VR4130_NOPS; i++)
+    if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
+      {
+	/* Extract the destination register.  */
+	if (mips_opts.mips16)
+	  reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
+	else
+	  reg = EXTRACT_OPERAND (RD, history[i]);
+
+	/* No nops are needed if INSN reads that register.  */
+	if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
+	  return 0;
+
+	/* ...or if any of the intervening instructions do.  */
+	for (j = 0; j < i; j++)
+	  if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
+	    return 0;
+
+	return MAX_VR4130_NOPS - i;
+      }
+  return 0;
+}
+
 /* Return the number of nops that would be needed if instruction INSN
    immediately followed the MAX_NOPS instructions given by HISTORY,
    where HISTORY[0] is the most recent instruction.  If INSN is null,
@@ -2023,13 +2073,21 @@ nops_for_insn (const struct mips_cl_insn *history,
   int i, nops, tmp_nops;
 
   nops = 0;
-  for (i = 0; i < MAX_NOPS; i++)
+  for (i = 0; i < MAX_DELAY_NOPS; i++)
     if (!history[i].noreorder_p)
       {
 	tmp_nops = insns_between (history + i, insn) - i;
 	if (tmp_nops > nops)
 	  nops = tmp_nops;
       }
+
+  if (mips_fix_vr4130)
+    {
+      tmp_nops = nops_for_vr4130 (history, insn);
+      if (tmp_nops > nops)
+	nops = tmp_nops;
+    }
+
   return nops;
 }
 
@@ -9966,9 +10024,13 @@ struct option md_longopts[] =
 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
   {"mfix-vr4120",    no_argument, NULL, OPTION_FIX_VR4120},
   {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
+#define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
+#define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
+  {"mfix-vr4130",    no_argument, NULL, OPTION_FIX_VR4130},
+  {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
 
   /* Miscellaneous options.  */
-#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
+#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
   {"trap", no_argument, NULL, OPTION_TRAP},
   {"no-break", no_argument, NULL, OPTION_TRAP},
@@ -10211,6 +10273,14 @@ md_parse_option (int c, char *arg)
       mips_fix_vr4120 = 0;
       break;
 
+    case OPTION_FIX_VR4130:
+      mips_fix_vr4130 = 1;
+      break;
+
+    case OPTION_NO_FIX_VR4130:
+      mips_fix_vr4130 = 0;
+      break;
+
     case OPTION_RELAX_BRANCH:
       mips_relax_branch = 1;
       break;
@@ -13886,6 +13956,7 @@ MIPS options:\n\
 -no-mips16		do not generate mips16 instructions\n"));
   fprintf (stream, _("\
 -mfix-vr4120		work around certain VR4120 errata\n\
+-mfix-vr4130		work around VR4130 mflo/mfhi errata\n\
 -mgp32			use 32-bit GPRs, regardless of the chosen ISA\n\
 -mfp32			use 32-bit FPRs, regardless of the chosen ISA\n\
 -mno-shared		optimize output for executables\n\
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6ce90b0a43..793640dcf3 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/relax-swap1-mips[12].d: Expect the delay slots of
+	bc1f and bc1t to be filled.
+	* gas/mips/branch-misc-3.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
 2005-03-08  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/ia64/no-fit.[ls]: New.
diff --git a/gas/testsuite/gas/mips/branch-misc-3.d b/gas/testsuite/gas/mips/branch-misc-3.d
new file mode 100644
index 0000000000..754ed20e7b
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-3.d
@@ -0,0 +1,59 @@
+#as: -march=mips1 -32
+#objdump: -dz
+#name: MIPS coprocessor branches
+
+.*file format .*
+
+Disassembly .*:
+
+0+00 <.*>:
+.*	ctc1	a0,\$31
+.*	b	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	nop
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	b	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	addiu	a2,a2,1
+.*	bc1t	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	addiu	a1,a1,1
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	addiu	a2,a2,1
+.*	bc1t	.*
+.*	addiu	a3,a3,1
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	addiu	a1,a1,1
+.*	bc1t	.*
+.*	addiu	a2,a2,1
+#
+.*	bc1t	.*
+.*	addiu	a3,a3,1
+#pass
diff --git a/gas/testsuite/gas/mips/branch-misc-3.s b/gas/testsuite/gas/mips/branch-misc-3.s
new file mode 100644
index 0000000000..7a025a7c00
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-3.s
@@ -0,0 +1,44 @@
+	# ctc1s and compares shouldn't appear in a branch delay slot.
+	ctc1	$4,$31
+	b	1f
+1:
+	ctc1	$4,$31
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	b	1f
+1:
+	c.eq.s	$f0,$f2
+	bc1t	1f
+1:
+
+	# The next three branches should have nop-filled slots.
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	bc1t	1f
+1:
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	addiu	$5,$5,1
+	bc1t	1f
+1:
+
+	# ...but a swap is possible in these three.
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	addiu	$7,$7,1
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	bc1t	1f
+1:
+	addiu	$7,$7,1
+	bc1t	1f
+1:
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 3a1fc128f1..508fc8079a 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -429,6 +429,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1]
     run_list_test_arches "branch-misc-2" "-32 -non_shared" [mips_arch_list_matching mips1]
     run_list_test_arches "branch-misc-2pic" "-32 -call_shared" [mips_arch_list_matching mips1]
+    run_dump_test "branch-misc-3"
     run_dump_test "branch-swap"
 
     if $ilocks {
diff --git a/gas/testsuite/gas/mips/relax-swap1-mips1.d b/gas/testsuite/gas/mips/relax-swap1-mips1.d
index 772300b49f..4a0f7b35e1 100644
--- a/gas/testsuite/gas/mips/relax-swap1-mips1.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips1.d
@@ -12,7 +12,7 @@ Disassembly of section \.text:
 0+0008 <[^>]*> lw	at,2\(gp\)
 [ 	]*8: R_MIPS_GOT16	\.text
 0+000c <[^>]*> nop
-0+0010 <[^>]*> addiu	at,at,1000
+0+0010 <[^>]*> addiu	at,at,992
 [ 	]*10: R_MIPS_LO16	\.text
 0+0014 <[^>]*> jr	at
 0+0018 <[^>]*> move	v0,a0
@@ -23,7 +23,7 @@ Disassembly of section \.text:
 0+002c <[^>]*> lw	at,2\(gp\)
 [ 	]*2c: R_MIPS_GOT16	\.text
 0+0030 <[^>]*> nop
-0+0034 <[^>]*> addiu	at,at,1000
+0+0034 <[^>]*> addiu	at,at,992
 [ 	]*34: R_MIPS_LO16	\.text
 0+0038 <[^>]*> jr	at
 0+003c <[^>]*> nop
@@ -32,7 +32,7 @@ Disassembly of section \.text:
 0+0048 <[^>]*> lw	at,2\(gp\)
 [ 	]*48: R_MIPS_GOT16	\.text
 0+004c <[^>]*> nop
-0+0050 <[^>]*> addiu	at,at,1000
+0+0050 <[^>]*> addiu	at,at,992
 [ 	]*50: R_MIPS_LO16	\.text
 0+0054 <[^>]*> jr	at
 0+0058 <[^>]*> sw	v0,0\(a0\)
@@ -45,7 +45,7 @@ Disassembly of section \.text:
 0+0074 <[^>]*> lw	at,2\(gp\)
 [ 	]*74: R_MIPS_GOT16	\.text
 0+0078 <[^>]*> nop
-0+007c <[^>]*> addiu	at,at,1000
+0+007c <[^>]*> addiu	at,at,992
 [ 	]*7c: R_MIPS_LO16	\.text
 0+0080 <[^>]*> jr	at
 0+0084 <[^>]*> nop
@@ -56,7 +56,7 @@ Disassembly of section \.text:
 0+0098 <[^>]*> lw	at,2\(gp\)
 [ 	]*98: R_MIPS_GOT16	\.text
 0+009c <[^>]*> nop
-0+00a0 <[^>]*> addiu	at,at,1000
+0+00a0 <[^>]*> addiu	at,at,992
 [ 	]*a0: R_MIPS_LO16	\.text
 0+00a4 <[^>]*> jr	at
 0+00a8 <[^>]*> move	v0,a0
@@ -69,7 +69,7 @@ Disassembly of section \.text:
 0+00c4 <[^>]*> lw	at,2\(gp\)
 [ 	]*c4: R_MIPS_GOT16	\.text
 0+00c8 <[^>]*> nop
-0+00cc <[^>]*> addiu	at,at,1000
+0+00cc <[^>]*> addiu	at,at,992
 [ 	]*cc: R_MIPS_LO16	\.text
 0+00d0 <[^>]*> jr	at
 0+00d4 <[^>]*> nop
@@ -80,7 +80,7 @@ Disassembly of section \.text:
 0+00e8 <[^>]*> lw	at,2\(gp\)
 [ 	]*e8: R_MIPS_GOT16	\.text
 0+00ec <[^>]*> nop
-0+00f0 <[^>]*> addiu	at,at,1000
+0+00f0 <[^>]*> addiu	at,at,992
 [ 	]*f0: R_MIPS_LO16	\.text
 0+00f4 <[^>]*> jr	at
 0+00f8 <[^>]*> addiu	v0,a0,1
@@ -95,7 +95,7 @@ Disassembly of section \.text:
 0+011c <[^>]*> lw	at,2\(gp\)
 [ 	]*11c: R_MIPS_GOT16	\.text
 0+0120 <[^>]*> nop
-0+0124 <[^>]*> addiu	at,at,1000
+0+0124 <[^>]*> addiu	at,at,992
 [ 	]*124: R_MIPS_LO16	\.text
 0+0128 <[^>]*> jr	at
 0+012c <[^>]*> nop
@@ -108,7 +108,7 @@ Disassembly of section \.text:
 0+0148 <[^>]*> lw	at,2\(gp\)
 [ 	]*148: R_MIPS_GOT16	\.text
 0+014c <[^>]*> nop
-0+0150 <[^>]*> addiu	at,at,1000
+0+0150 <[^>]*> addiu	at,at,992
 [ 	]*150: R_MIPS_LO16	\.text
 0+0154 <[^>]*> jr	at
 0+0158 <[^>]*> nop
@@ -119,7 +119,7 @@ Disassembly of section \.text:
 0+016c <[^>]*> lw	at,2\(gp\)
 [ 	]*16c: R_MIPS_GOT16	\.text
 0+0170 <[^>]*> nop
-0+0174 <[^>]*> addiu	at,at,1000
+0+0174 <[^>]*> addiu	at,at,992
 [ 	]*174: R_MIPS_LO16	\.text
 0+0178 <[^>]*> jr	at
 0+017c <[^>]*> sw	v0,0\(a0\)
@@ -130,7 +130,7 @@ Disassembly of section \.text:
 0+0190 <[^>]*> lw	at,2\(gp\)
 [ 	]*190: R_MIPS_GOT16	\.text
 0+0194 <[^>]*> nop
-0+0198 <[^>]*> addiu	at,at,1000
+0+0198 <[^>]*> addiu	at,at,992
 [ 	]*198: R_MIPS_LO16	\.text
 0+019c <[^>]*> jr	at
 0+01a0 <[^>]*> sw	v0,0\(a0\)
@@ -145,7 +145,7 @@ Disassembly of section \.text:
 0+01c4 <[^>]*> lw	at,2\(gp\)
 [ 	]*1c4: R_MIPS_GOT16	\.text
 0+01c8 <[^>]*> nop
-0+01cc <[^>]*> addiu	at,at,1000
+0+01cc <[^>]*> addiu	at,at,992
 [ 	]*1cc: R_MIPS_LO16	\.text
 0+01d0 <[^>]*> jr	at
 0+01d4 <[^>]*> nop
@@ -158,154 +158,152 @@ Disassembly of section \.text:
 0+01f0 <[^>]*> lw	at,2\(gp\)
 [ 	]*1f0: R_MIPS_GOT16	\.text
 0+01f4 <[^>]*> nop
-0+01f8 <[^>]*> addiu	at,at,1000
+0+01f8 <[^>]*> addiu	at,at,992
 [ 	]*1f8: R_MIPS_LO16	\.text
 0+01fc <[^>]*> jr	at
 0+0200 <[^>]*> move	a2,a3
-0+0204 <[^>]*> move	v0,a0
-0+0208 <[^>]*> bc1t	00000000 <foo>
-0+020c <[^>]*> nop
-0+0210 <[^>]*> move	v0,a0
-0+0214 <[^>]*> bc1f	0000022c <foo\+0x22c>
+0+0204 <[^>]*> bc1t	00000000 <foo>
+0+0208 <[^>]*> move	v0,a0
+0+020c <[^>]*> bc1f	00000224 <foo\+0x224>
+0+0210 <[^>]*> nop
+0+0214 <[^>]*> lw	at,2\(gp\)
+[ 	]*214: R_MIPS_GOT16	\.text
 0+0218 <[^>]*> nop
-0+021c <[^>]*> lw	at,2\(gp\)
-[ 	]*21c: R_MIPS_GOT16	\.text
-0+0220 <[^>]*> nop
-0+0224 <[^>]*> addiu	at,at,1000
-[ 	]*224: R_MIPS_LO16	\.text
-0+0228 <[^>]*> jr	at
-0+022c <[^>]*> nop
-0+0230 <[^>]*> move	v0,a0
-0+0234 <[^>]*> b	00000000 <foo>
-0+0238 <[^>]*> nop
-0+023c <[^>]*> move	v0,a0
-0+0240 <[^>]*> lw	at,2\(gp\)
-[ 	]*240: R_MIPS_GOT16	\.text
-0+0244 <[^>]*> nop
-0+0248 <[^>]*> addiu	at,at,1000
-[ 	]*248: R_MIPS_LO16	\.text
-0+024c <[^>]*> jr	at
-0+0250 <[^>]*> nop
-0+0254 <[^>]*> move	v0,a0
-0+0258 <[^>]*> b	00000000 <foo>
-0+025c <[^>]*> nop
-0+0260 <[^>]*> move	v0,a0
-0+0264 <[^>]*> lw	at,2\(gp\)
-[ 	]*264: R_MIPS_GOT16	\.text
-0+0268 <[^>]*> nop
-0+026c <[^>]*> addiu	at,at,1000
-[ 	]*26c: R_MIPS_LO16	\.text
-0+0270 <[^>]*> jr	at
-0+0274 <[^>]*> nop
-0+0278 <[^>]*> move	a2,a3
-0+027c <[^>]*> move	v0,a0
-0+0280 <[^>]*> b	00000000 <foo>
-0+0284 <[^>]*> nop
-0+0288 <[^>]*> move	a2,a3
-0+028c <[^>]*> move	v0,a0
-0+0290 <[^>]*> lw	at,2\(gp\)
-[ 	]*290: R_MIPS_GOT16	\.text
-0+0294 <[^>]*> nop
-0+0298 <[^>]*> addiu	at,at,1000
-[ 	]*298: R_MIPS_LO16	\.text
-0+029c <[^>]*> jr	at
+0+021c <[^>]*> addiu	at,at,992
+[ 	]*21c: R_MIPS_LO16	\.text
+0+0220 <[^>]*> jr	at
+0+0224 <[^>]*> move	v0,a0
+0+0228 <[^>]*> move	v0,a0
+0+022c <[^>]*> b	00000000 <foo>
+0+0230 <[^>]*> nop
+0+0234 <[^>]*> move	v0,a0
+0+0238 <[^>]*> lw	at,2\(gp\)
+[ 	]*238: R_MIPS_GOT16	\.text
+0+023c <[^>]*> nop
+0+0240 <[^>]*> addiu	at,at,992
+[ 	]*240: R_MIPS_LO16	\.text
+0+0244 <[^>]*> jr	at
+0+0248 <[^>]*> nop
+0+024c <[^>]*> move	v0,a0
+0+0250 <[^>]*> b	00000000 <foo>
+0+0254 <[^>]*> nop
+0+0258 <[^>]*> move	v0,a0
+0+025c <[^>]*> lw	at,2\(gp\)
+[ 	]*25c: R_MIPS_GOT16	\.text
+0+0260 <[^>]*> nop
+0+0264 <[^>]*> addiu	at,at,992
+[ 	]*264: R_MIPS_LO16	\.text
+0+0268 <[^>]*> jr	at
+0+026c <[^>]*> nop
+0+0270 <[^>]*> move	a2,a3
+0+0274 <[^>]*> move	v0,a0
+0+0278 <[^>]*> b	00000000 <foo>
+0+027c <[^>]*> nop
+0+0280 <[^>]*> move	a2,a3
+0+0284 <[^>]*> move	v0,a0
+0+0288 <[^>]*> lw	at,2\(gp\)
+[ 	]*288: R_MIPS_GOT16	\.text
+0+028c <[^>]*> nop
+0+0290 <[^>]*> addiu	at,at,992
+[ 	]*290: R_MIPS_LO16	\.text
+0+0294 <[^>]*> jr	at
+0+0298 <[^>]*> nop
+0+029c <[^>]*> lw	at,0\(gp\)
+[ 	]*29c: R_MIPS_GOT16	\.text
 0+02a0 <[^>]*> nop
-0+02a4 <[^>]*> lw	at,0\(gp\)
-[ 	]*2a4: R_MIPS_GOT16	\.text
-0+02a8 <[^>]*> nop
-0+02ac <[^>]*> addiu	at,at,692
-[ 	]*2ac: R_MIPS_LO16	\.text
-0+02b0 <[^>]*> sw	v0,0\(at\)
-0+02b4 <[^>]*> b	00000000 <foo>
+0+02a4 <[^>]*> addiu	at,at,684
+[ 	]*2a4: R_MIPS_LO16	\.text
+0+02a8 <[^>]*> sw	v0,0\(at\)
+0+02ac <[^>]*> b	00000000 <foo>
+0+02b0 <[^>]*> nop
+0+02b4 <[^>]*> lw	at,0\(gp\)
+[ 	]*2b4: R_MIPS_GOT16	\.text
 0+02b8 <[^>]*> nop
-0+02bc <[^>]*> lw	at,0\(gp\)
-[ 	]*2bc: R_MIPS_GOT16	\.text
-0+02c0 <[^>]*> nop
-0+02c4 <[^>]*> addiu	at,at,716
-[ 	]*2c4: R_MIPS_LO16	\.text
-0+02c8 <[^>]*> sw	v0,0\(at\)
-0+02cc <[^>]*> lw	at,2\(gp\)
-[ 	]*2cc: R_MIPS_GOT16	\.text
-0+02d0 <[^>]*> nop
-0+02d4 <[^>]*> addiu	at,at,1000
-[ 	]*2d4: R_MIPS_LO16	\.text
-0+02d8 <[^>]*> jr	at
-0+02dc <[^>]*> nop
-0+02e0 <[^>]*> lwc1	\$f0,0\(a0\)
-0+02e4 <[^>]*> b	00000000 <foo>
-0+02e8 <[^>]*> nop
-0+02ec <[^>]*> lwc1	\$f0,0\(a0\)
-0+02f0 <[^>]*> lw	at,2\(gp\)
-[ 	]*2f0: R_MIPS_GOT16	\.text
-0+02f4 <[^>]*> nop
-0+02f8 <[^>]*> addiu	at,at,1000
-[ 	]*2f8: R_MIPS_LO16	\.text
-0+02fc <[^>]*> jr	at
-0+0300 <[^>]*> nop
-0+0304 <[^>]*> cfc1	v0,\$31
-0+0308 <[^>]*> b	00000000 <foo>
-0+030c <[^>]*> nop
-0+0310 <[^>]*> cfc1	v0,\$31
-0+0314 <[^>]*> lw	at,2\(gp\)
-[ 	]*314: R_MIPS_GOT16	\.text
-0+0318 <[^>]*> nop
-0+031c <[^>]*> addiu	at,at,1000
-[ 	]*31c: R_MIPS_LO16	\.text
-0+0320 <[^>]*> jr	at
-0+0324 <[^>]*> nop
-0+0328 <[^>]*> ctc1	v0,\$31
-0+032c <[^>]*> b	00000000 <foo>
-0+0330 <[^>]*> nop
-0+0334 <[^>]*> ctc1	v0,\$31
-0+0338 <[^>]*> lw	at,2\(gp\)
-[ 	]*338: R_MIPS_GOT16	\.text
-0+033c <[^>]*> nop
-0+0340 <[^>]*> addiu	at,at,1000
-[ 	]*340: R_MIPS_LO16	\.text
-0+0344 <[^>]*> jr	at
-0+0348 <[^>]*> nop
-0+034c <[^>]*> mtc1	v0,\$f31
-0+0350 <[^>]*> b	00000000 <foo>
-0+0354 <[^>]*> nop
-0+0358 <[^>]*> mtc1	v0,\$f31
-0+035c <[^>]*> lw	at,2\(gp\)
-[ 	]*35c: R_MIPS_GOT16	\.text
-0+0360 <[^>]*> nop
-0+0364 <[^>]*> addiu	at,at,1000
-[ 	]*364: R_MIPS_LO16	\.text
-0+0368 <[^>]*> jr	at
-0+036c <[^>]*> nop
-0+0370 <[^>]*> mfhi	v0
-0+0374 <[^>]*> b	00000000 <foo>
-0+0378 <[^>]*> nop
-0+037c <[^>]*> mfhi	v0
-0+0380 <[^>]*> lw	at,2\(gp\)
-[ 	]*380: R_MIPS_GOT16	\.text
-0+0384 <[^>]*> nop
-0+0388 <[^>]*> addiu	at,at,1000
-[ 	]*388: R_MIPS_LO16	\.text
-0+038c <[^>]*> jr	at
-0+0390 <[^>]*> nop
-0+0394 <[^>]*> move	v0,a0
-0+0398 <[^>]*> jr	v0
-0+039c <[^>]*> nop
-0+03a0 <[^>]*> jr	a0
-0+03a4 <[^>]*> move	v0,a0
-0+03a8 <[^>]*> move	v0,a0
-0+03ac <[^>]*> jalr	v0
-0+03b0 <[^>]*> nop
-0+03b4 <[^>]*> jalr	a0
-0+03b8 <[^>]*> move	v0,a0
-0+03bc <[^>]*> move	v0,ra
-0+03c0 <[^>]*> jalr	v1
-0+03c4 <[^>]*> nop
-0+03c8 <[^>]*> move	ra,a0
-0+03cc <[^>]*> jalr	a1
-0+03d0 <[^>]*> nop
-0+03d4 <[^>]*> jalr	v0,v1
-0+03d8 <[^>]*> move	ra,a0
-0+03dc <[^>]*> move	v0,ra
-0+03e0 <[^>]*> jalr	v0,v1
-0+03e4 <[^>]*> nop
+0+02bc <[^>]*> addiu	at,at,708
+[ 	]*2bc: R_MIPS_LO16	\.text
+0+02c0 <[^>]*> sw	v0,0\(at\)
+0+02c4 <[^>]*> lw	at,2\(gp\)
+[ 	]*2c4: R_MIPS_GOT16	\.text
+0+02c8 <[^>]*> nop
+0+02cc <[^>]*> addiu	at,at,992
+[ 	]*2cc: R_MIPS_LO16	\.text
+0+02d0 <[^>]*> jr	at
+0+02d4 <[^>]*> nop
+0+02d8 <[^>]*> lwc1	\$f0,0\(a0\)
+0+02dc <[^>]*> b	00000000 <foo>
+0+02e0 <[^>]*> nop
+0+02e4 <[^>]*> lwc1	\$f0,0\(a0\)
+0+02e8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2e8: R_MIPS_GOT16	\.text
+0+02ec <[^>]*> nop
+0+02f0 <[^>]*> addiu	at,at,992
+[ 	]*2f0: R_MIPS_LO16	\.text
+0+02f4 <[^>]*> jr	at
+0+02f8 <[^>]*> nop
+0+02fc <[^>]*> cfc1	v0,\$31
+0+0300 <[^>]*> b	00000000 <foo>
+0+0304 <[^>]*> nop
+0+0308 <[^>]*> cfc1	v0,\$31
+0+030c <[^>]*> lw	at,2\(gp\)
+[ 	]*30c: R_MIPS_GOT16	\.text
+0+0310 <[^>]*> nop
+0+0314 <[^>]*> addiu	at,at,992
+[ 	]*314: R_MIPS_LO16	\.text
+0+0318 <[^>]*> jr	at
+0+031c <[^>]*> nop
+0+0320 <[^>]*> ctc1	v0,\$31
+0+0324 <[^>]*> b	00000000 <foo>
+0+0328 <[^>]*> nop
+0+032c <[^>]*> ctc1	v0,\$31
+0+0330 <[^>]*> lw	at,2\(gp\)
+[ 	]*330: R_MIPS_GOT16	\.text
+0+0334 <[^>]*> nop
+0+0338 <[^>]*> addiu	at,at,992
+[ 	]*338: R_MIPS_LO16	\.text
+0+033c <[^>]*> jr	at
+0+0340 <[^>]*> nop
+0+0344 <[^>]*> mtc1	v0,\$f31
+0+0348 <[^>]*> b	00000000 <foo>
+0+034c <[^>]*> nop
+0+0350 <[^>]*> mtc1	v0,\$f31
+0+0354 <[^>]*> lw	at,2\(gp\)
+[ 	]*354: R_MIPS_GOT16	\.text
+0+0358 <[^>]*> nop
+0+035c <[^>]*> addiu	at,at,992
+[ 	]*35c: R_MIPS_LO16	\.text
+0+0360 <[^>]*> jr	at
+0+0364 <[^>]*> nop
+0+0368 <[^>]*> mfhi	v0
+0+036c <[^>]*> b	00000000 <foo>
+0+0370 <[^>]*> nop
+0+0374 <[^>]*> mfhi	v0
+0+0378 <[^>]*> lw	at,2\(gp\)
+[ 	]*378: R_MIPS_GOT16	\.text
+0+037c <[^>]*> nop
+0+0380 <[^>]*> addiu	at,at,992
+[ 	]*380: R_MIPS_LO16	\.text
+0+0384 <[^>]*> jr	at
+0+0388 <[^>]*> nop
+0+038c <[^>]*> move	v0,a0
+0+0390 <[^>]*> jr	v0
+0+0394 <[^>]*> nop
+0+0398 <[^>]*> jr	a0
+0+039c <[^>]*> move	v0,a0
+0+03a0 <[^>]*> move	v0,a0
+0+03a4 <[^>]*> jalr	v0
+0+03a8 <[^>]*> nop
+0+03ac <[^>]*> jalr	a0
+0+03b0 <[^>]*> move	v0,a0
+0+03b4 <[^>]*> move	v0,ra
+0+03b8 <[^>]*> jalr	v1
+0+03bc <[^>]*> nop
+0+03c0 <[^>]*> move	ra,a0
+0+03c4 <[^>]*> jalr	a1
+0+03c8 <[^>]*> nop
+0+03cc <[^>]*> jalr	v0,v1
+0+03d0 <[^>]*> move	ra,a0
+0+03d4 <[^>]*> move	v0,ra
+0+03d8 <[^>]*> jalr	v0,v1
+0+03dc <[^>]*> nop
 	\.\.\.
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/relax-swap1-mips2.d b/gas/testsuite/gas/mips/relax-swap1-mips2.d
index 070ea3af1c..17d010b91b 100644
--- a/gas/testsuite/gas/mips/relax-swap1-mips2.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips2.d
@@ -11,7 +11,7 @@ Disassembly of section \.text:
 0+0004 <[^>]*> move	v0,a0
 0+0008 <[^>]*> lw	at,2\(gp\)
 [ 	]*8: R_MIPS_GOT16	\.text
-0+000c <[^>]*> addiu	at,at,868
+0+000c <[^>]*> addiu	at,at,860
 [ 	]*c: R_MIPS_LO16	\.text
 0+0010 <[^>]*> jr	at
 0+0014 <[^>]*> move	v0,a0
@@ -19,7 +19,7 @@ Disassembly of section \.text:
 0+001c <[^>]*> lw	v0,0\(a0\)
 0+0020 <[^>]*> lw	at,2\(gp\)
 [ 	]*20: R_MIPS_GOT16	\.text
-0+0024 <[^>]*> addiu	at,at,868
+0+0024 <[^>]*> addiu	at,at,860
 [ 	]*24: R_MIPS_LO16	\.text
 0+0028 <[^>]*> jr	at
 0+002c <[^>]*> lw	v0,0\(a0\)
@@ -27,7 +27,7 @@ Disassembly of section \.text:
 0+0034 <[^>]*> sw	v0,0\(a0\)
 0+0038 <[^>]*> lw	at,2\(gp\)
 [ 	]*38: R_MIPS_GOT16	\.text
-0+003c <[^>]*> addiu	at,at,868
+0+003c <[^>]*> addiu	at,at,860
 [ 	]*3c: R_MIPS_LO16	\.text
 0+0040 <[^>]*> jr	at
 0+0044 <[^>]*> sw	v0,0\(a0\)
@@ -39,7 +39,7 @@ Disassembly of section \.text:
 0+005c <[^>]*> nop
 0+0060 <[^>]*> lw	at,2\(gp\)
 [ 	]*60: R_MIPS_GOT16	\.text
-0+0064 <[^>]*> addiu	at,at,868
+0+0064 <[^>]*> addiu	at,at,860
 [ 	]*64: R_MIPS_LO16	\.text
 0+0068 <[^>]*> jr	at
 0+006c <[^>]*> nop
@@ -49,7 +49,7 @@ Disassembly of section \.text:
 0+007c <[^>]*> nop
 0+0080 <[^>]*> lw	at,2\(gp\)
 [ 	]*80: R_MIPS_GOT16	\.text
-0+0084 <[^>]*> addiu	at,at,868
+0+0084 <[^>]*> addiu	at,at,860
 [ 	]*84: R_MIPS_LO16	\.text
 0+0088 <[^>]*> jr	at
 0+008c <[^>]*> move	v0,a0
@@ -61,7 +61,7 @@ Disassembly of section \.text:
 0+00a4 <[^>]*> nop
 0+00a8 <[^>]*> lw	at,2\(gp\)
 [ 	]*a8: R_MIPS_GOT16	\.text
-0+00ac <[^>]*> addiu	at,at,868
+0+00ac <[^>]*> addiu	at,at,860
 [ 	]*ac: R_MIPS_LO16	\.text
 0+00b0 <[^>]*> jr	at
 0+00b4 <[^>]*> nop
@@ -71,7 +71,7 @@ Disassembly of section \.text:
 0+00c4 <[^>]*> nop
 0+00c8 <[^>]*> lw	at,2\(gp\)
 [ 	]*c8: R_MIPS_GOT16	\.text
-0+00cc <[^>]*> addiu	at,at,868
+0+00cc <[^>]*> addiu	at,at,860
 [ 	]*cc: R_MIPS_LO16	\.text
 0+00d0 <[^>]*> jr	at
 0+00d4 <[^>]*> addiu	v0,a0,1
@@ -83,7 +83,7 @@ Disassembly of section \.text:
 0+00ec <[^>]*> nop
 0+00f0 <[^>]*> lw	at,2\(gp\)
 [ 	]*f0: R_MIPS_GOT16	\.text
-0+00f4 <[^>]*> addiu	at,at,868
+0+00f4 <[^>]*> addiu	at,at,860
 [ 	]*f4: R_MIPS_LO16	\.text
 0+00f8 <[^>]*> jr	at
 0+00fc <[^>]*> nop
@@ -93,7 +93,7 @@ Disassembly of section \.text:
 0+010c <[^>]*> nop
 0+0110 <[^>]*> lw	at,2\(gp\)
 [ 	]*110: R_MIPS_GOT16	\.text
-0+0114 <[^>]*> addiu	at,at,868
+0+0114 <[^>]*> addiu	at,at,860
 [ 	]*114: R_MIPS_LO16	\.text
 0+0118 <[^>]*> jr	at
 0+011c <[^>]*> lw	v0,0\(a0\)
@@ -103,7 +103,7 @@ Disassembly of section \.text:
 0+012c <[^>]*> nop
 0+0130 <[^>]*> lw	at,2\(gp\)
 [ 	]*130: R_MIPS_GOT16	\.text
-0+0134 <[^>]*> addiu	at,at,868
+0+0134 <[^>]*> addiu	at,at,860
 [ 	]*134: R_MIPS_LO16	\.text
 0+0138 <[^>]*> jr	at
 0+013c <[^>]*> sw	v0,0\(a0\)
@@ -113,7 +113,7 @@ Disassembly of section \.text:
 0+014c <[^>]*> nop
 0+0150 <[^>]*> lw	at,2\(gp\)
 [ 	]*150: R_MIPS_GOT16	\.text
-0+0154 <[^>]*> addiu	at,at,868
+0+0154 <[^>]*> addiu	at,at,860
 [ 	]*154: R_MIPS_LO16	\.text
 0+0158 <[^>]*> jr	at
 0+015c <[^>]*> sw	v0,0\(a0\)
@@ -127,7 +127,7 @@ Disassembly of section \.text:
 0+017c <[^>]*> nop
 0+0180 <[^>]*> lw	at,2\(gp\)
 [ 	]*180: R_MIPS_GOT16	\.text
-0+0184 <[^>]*> addiu	at,at,868
+0+0184 <[^>]*> addiu	at,at,860
 [ 	]*184: R_MIPS_LO16	\.text
 0+0188 <[^>]*> jr	at
 0+018c <[^>]*> nop
@@ -139,140 +139,138 @@ Disassembly of section \.text:
 0+01a4 <[^>]*> nop
 0+01a8 <[^>]*> lw	at,2\(gp\)
 [ 	]*1a8: R_MIPS_GOT16	\.text
-0+01ac <[^>]*> addiu	at,at,868
+0+01ac <[^>]*> addiu	at,at,860
 [ 	]*1ac: R_MIPS_LO16	\.text
 0+01b0 <[^>]*> jr	at
 0+01b4 <[^>]*> move	a2,a3
-0+01b8 <[^>]*> move	v0,a0
-0+01bc <[^>]*> bc1t	00000000 <foo>
-0+01c0 <[^>]*> nop
-0+01c4 <[^>]*> move	v0,a0
-0+01c8 <[^>]*> bc1f	000001dc <foo\+0x1dc>
-0+01cc <[^>]*> nop
-0+01d0 <[^>]*> lw	at,2\(gp\)
-[ 	]*1d0: R_MIPS_GOT16	\.text
-0+01d4 <[^>]*> addiu	at,at,868
-[ 	]*1d4: R_MIPS_LO16	\.text
-0+01d8 <[^>]*> jr	at
-0+01dc <[^>]*> nop
-0+01e0 <[^>]*> move	v0,a0
-0+01e4 <[^>]*> b	00000000 <foo>
-0+01e8 <[^>]*> nop
-0+01ec <[^>]*> move	v0,a0
-0+01f0 <[^>]*> lw	at,2\(gp\)
-[ 	]*1f0: R_MIPS_GOT16	\.text
-0+01f4 <[^>]*> addiu	at,at,868
-[ 	]*1f4: R_MIPS_LO16	\.text
-0+01f8 <[^>]*> jr	at
-0+01fc <[^>]*> nop
-0+0200 <[^>]*> move	v0,a0
-0+0204 <[^>]*> b	00000000 <foo>
-0+0208 <[^>]*> nop
-0+020c <[^>]*> move	v0,a0
-0+0210 <[^>]*> lw	at,2\(gp\)
-[ 	]*210: R_MIPS_GOT16	\.text
-0+0214 <[^>]*> addiu	at,at,868
-[ 	]*214: R_MIPS_LO16	\.text
-0+0218 <[^>]*> jr	at
-0+021c <[^>]*> nop
-0+0220 <[^>]*> move	a2,a3
-0+0224 <[^>]*> move	v0,a0
-0+0228 <[^>]*> b	00000000 <foo>
-0+022c <[^>]*> nop
-0+0230 <[^>]*> move	a2,a3
-0+0234 <[^>]*> move	v0,a0
-0+0238 <[^>]*> lw	at,2\(gp\)
-[ 	]*238: R_MIPS_GOT16	\.text
-0+023c <[^>]*> addiu	at,at,868
-[ 	]*23c: R_MIPS_LO16	\.text
-0+0240 <[^>]*> jr	at
-0+0244 <[^>]*> nop
-0+0248 <[^>]*> lw	at,0\(gp\)
-[ 	]*248: R_MIPS_GOT16	\.text
-0+024c <[^>]*> addiu	at,at,596
-[ 	]*24c: R_MIPS_LO16	\.text
-0+0250 <[^>]*> sw	v0,0\(at\)
-0+0254 <[^>]*> b	00000000 <foo>
-0+0258 <[^>]*> nop
-0+025c <[^>]*> lw	at,0\(gp\)
-[ 	]*25c: R_MIPS_GOT16	\.text
-0+0260 <[^>]*> addiu	at,at,616
-[ 	]*260: R_MIPS_LO16	\.text
-0+0264 <[^>]*> sw	v0,0\(at\)
-0+0268 <[^>]*> lw	at,2\(gp\)
-[ 	]*268: R_MIPS_GOT16	\.text
-0+026c <[^>]*> addiu	at,at,868
-[ 	]*26c: R_MIPS_LO16	\.text
-0+0270 <[^>]*> jr	at
-0+0274 <[^>]*> nop
-0+0278 <[^>]*> b	00000000 <foo>
-0+027c <[^>]*> lwc1	\$f0,0\(a0\)
-0+0280 <[^>]*> lw	at,2\(gp\)
-[ 	]*280: R_MIPS_GOT16	\.text
-0+0284 <[^>]*> addiu	at,at,868
-[ 	]*284: R_MIPS_LO16	\.text
-0+0288 <[^>]*> jr	at
-0+028c <[^>]*> lwc1	\$f0,0\(a0\)
-0+0290 <[^>]*> cfc1	v0,\$31
-0+0294 <[^>]*> b	00000000 <foo>
-0+0298 <[^>]*> nop
-0+029c <[^>]*> cfc1	v0,\$31
-0+02a0 <[^>]*> lw	at,2\(gp\)
-[ 	]*2a0: R_MIPS_GOT16	\.text
-0+02a4 <[^>]*> addiu	at,at,868
-[ 	]*2a4: R_MIPS_LO16	\.text
-0+02a8 <[^>]*> jr	at
-0+02ac <[^>]*> nop
-0+02b0 <[^>]*> ctc1	v0,\$31
-0+02b4 <[^>]*> b	00000000 <foo>
-0+02b8 <[^>]*> nop
-0+02bc <[^>]*> ctc1	v0,\$31
-0+02c0 <[^>]*> lw	at,2\(gp\)
-[ 	]*2c0: R_MIPS_GOT16	\.text
-0+02c4 <[^>]*> addiu	at,at,868
-[ 	]*2c4: R_MIPS_LO16	\.text
-0+02c8 <[^>]*> jr	at
-0+02cc <[^>]*> nop
-0+02d0 <[^>]*> mtc1	v0,\$f31
-0+02d4 <[^>]*> b	00000000 <foo>
-0+02d8 <[^>]*> nop
-0+02dc <[^>]*> mtc1	v0,\$f31
-0+02e0 <[^>]*> lw	at,2\(gp\)
-[ 	]*2e0: R_MIPS_GOT16	\.text
-0+02e4 <[^>]*> addiu	at,at,868
-[ 	]*2e4: R_MIPS_LO16	\.text
-0+02e8 <[^>]*> jr	at
-0+02ec <[^>]*> nop
-0+02f0 <[^>]*> mfhi	v0
-0+02f4 <[^>]*> b	00000000 <foo>
-0+02f8 <[^>]*> nop
-0+02fc <[^>]*> mfhi	v0
-0+0300 <[^>]*> lw	at,2\(gp\)
-[ 	]*300: R_MIPS_GOT16	\.text
-0+0304 <[^>]*> addiu	at,at,868
-[ 	]*304: R_MIPS_LO16	\.text
-0+0308 <[^>]*> jr	at
-0+030c <[^>]*> nop
-0+0310 <[^>]*> move	v0,a0
-0+0314 <[^>]*> jr	v0
-0+0318 <[^>]*> nop
-0+031c <[^>]*> jr	a0
-0+0320 <[^>]*> move	v0,a0
-0+0324 <[^>]*> move	v0,a0
-0+0328 <[^>]*> jalr	v0
-0+032c <[^>]*> nop
-0+0330 <[^>]*> jalr	a0
-0+0334 <[^>]*> move	v0,a0
-0+0338 <[^>]*> move	v0,ra
-0+033c <[^>]*> jalr	v1
-0+0340 <[^>]*> nop
-0+0344 <[^>]*> move	ra,a0
-0+0348 <[^>]*> jalr	a1
-0+034c <[^>]*> nop
-0+0350 <[^>]*> jalr	v0,v1
-0+0354 <[^>]*> move	ra,a0
-0+0358 <[^>]*> move	v0,ra
-0+035c <[^>]*> jalr	v0,v1
-0+0360 <[^>]*> nop
+0+01b8 <[^>]*> bc1t	00000000 <foo>
+0+01bc <[^>]*> move	v0,a0
+0+01c0 <[^>]*> bc1f	000001d4 <foo\+0x1d4>
+0+01c4 <[^>]*> nop
+0+01c8 <[^>]*> lw	at,2\(gp\)
+[ 	]*1c8: R_MIPS_GOT16	\.text
+0+01cc <[^>]*> addiu	at,at,860
+[ 	]*1cc: R_MIPS_LO16	\.text
+0+01d0 <[^>]*> jr	at
+0+01d4 <[^>]*> move	v0,a0
+0+01d8 <[^>]*> move	v0,a0
+0+01dc <[^>]*> b	00000000 <foo>
+0+01e0 <[^>]*> nop
+0+01e4 <[^>]*> move	v0,a0
+0+01e8 <[^>]*> lw	at,2\(gp\)
+[ 	]*1e8: R_MIPS_GOT16	\.text
+0+01ec <[^>]*> addiu	at,at,860
+[ 	]*1ec: R_MIPS_LO16	\.text
+0+01f0 <[^>]*> jr	at
+0+01f4 <[^>]*> nop
+0+01f8 <[^>]*> move	v0,a0
+0+01fc <[^>]*> b	00000000 <foo>
+0+0200 <[^>]*> nop
+0+0204 <[^>]*> move	v0,a0
+0+0208 <[^>]*> lw	at,2\(gp\)
+[ 	]*208: R_MIPS_GOT16	\.text
+0+020c <[^>]*> addiu	at,at,860
+[ 	]*20c: R_MIPS_LO16	\.text
+0+0210 <[^>]*> jr	at
+0+0214 <[^>]*> nop
+0+0218 <[^>]*> move	a2,a3
+0+021c <[^>]*> move	v0,a0
+0+0220 <[^>]*> b	00000000 <foo>
+0+0224 <[^>]*> nop
+0+0228 <[^>]*> move	a2,a3
+0+022c <[^>]*> move	v0,a0
+0+0230 <[^>]*> lw	at,2\(gp\)
+[ 	]*230: R_MIPS_GOT16	\.text
+0+0234 <[^>]*> addiu	at,at,860
+[ 	]*234: R_MIPS_LO16	\.text
+0+0238 <[^>]*> jr	at
+0+023c <[^>]*> nop
+0+0240 <[^>]*> lw	at,0\(gp\)
+[ 	]*240: R_MIPS_GOT16	\.text
+0+0244 <[^>]*> addiu	at,at,588
+[ 	]*244: R_MIPS_LO16	\.text
+0+0248 <[^>]*> sw	v0,0\(at\)
+0+024c <[^>]*> b	00000000 <foo>
+0+0250 <[^>]*> nop
+0+0254 <[^>]*> lw	at,0\(gp\)
+[ 	]*254: R_MIPS_GOT16	\.text
+0+0258 <[^>]*> addiu	at,at,608
+[ 	]*258: R_MIPS_LO16	\.text
+0+025c <[^>]*> sw	v0,0\(at\)
+0+0260 <[^>]*> lw	at,2\(gp\)
+[ 	]*260: R_MIPS_GOT16	\.text
+0+0264 <[^>]*> addiu	at,at,860
+[ 	]*264: R_MIPS_LO16	\.text
+0+0268 <[^>]*> jr	at
+0+026c <[^>]*> nop
+0+0270 <[^>]*> b	00000000 <foo>
+0+0274 <[^>]*> lwc1	\$f0,0\(a0\)
+0+0278 <[^>]*> lw	at,2\(gp\)
+[ 	]*278: R_MIPS_GOT16	\.text
+0+027c <[^>]*> addiu	at,at,860
+[ 	]*27c: R_MIPS_LO16	\.text
+0+0280 <[^>]*> jr	at
+0+0284 <[^>]*> lwc1	\$f0,0\(a0\)
+0+0288 <[^>]*> cfc1	v0,\$31
+0+028c <[^>]*> b	00000000 <foo>
+0+0290 <[^>]*> nop
+0+0294 <[^>]*> cfc1	v0,\$31
+0+0298 <[^>]*> lw	at,2\(gp\)
+[ 	]*298: R_MIPS_GOT16	\.text
+0+029c <[^>]*> addiu	at,at,860
+[ 	]*29c: R_MIPS_LO16	\.text
+0+02a0 <[^>]*> jr	at
+0+02a4 <[^>]*> nop
+0+02a8 <[^>]*> ctc1	v0,\$31
+0+02ac <[^>]*> b	00000000 <foo>
+0+02b0 <[^>]*> nop
+0+02b4 <[^>]*> ctc1	v0,\$31
+0+02b8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2b8: R_MIPS_GOT16	\.text
+0+02bc <[^>]*> addiu	at,at,860
+[ 	]*2bc: R_MIPS_LO16	\.text
+0+02c0 <[^>]*> jr	at
+0+02c4 <[^>]*> nop
+0+02c8 <[^>]*> mtc1	v0,\$f31
+0+02cc <[^>]*> b	00000000 <foo>
+0+02d0 <[^>]*> nop
+0+02d4 <[^>]*> mtc1	v0,\$f31
+0+02d8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2d8: R_MIPS_GOT16	\.text
+0+02dc <[^>]*> addiu	at,at,860
+[ 	]*2dc: R_MIPS_LO16	\.text
+0+02e0 <[^>]*> jr	at
+0+02e4 <[^>]*> nop
+0+02e8 <[^>]*> mfhi	v0
+0+02ec <[^>]*> b	00000000 <foo>
+0+02f0 <[^>]*> nop
+0+02f4 <[^>]*> mfhi	v0
+0+02f8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2f8: R_MIPS_GOT16	\.text
+0+02fc <[^>]*> addiu	at,at,860
+[ 	]*2fc: R_MIPS_LO16	\.text
+0+0300 <[^>]*> jr	at
+0+0304 <[^>]*> nop
+0+0308 <[^>]*> move	v0,a0
+0+030c <[^>]*> jr	v0
+0+0310 <[^>]*> nop
+0+0314 <[^>]*> jr	a0
+0+0318 <[^>]*> move	v0,a0
+0+031c <[^>]*> move	v0,a0
+0+0320 <[^>]*> jalr	v0
+0+0324 <[^>]*> nop
+0+0328 <[^>]*> jalr	a0
+0+032c <[^>]*> move	v0,a0
+0+0330 <[^>]*> move	v0,ra
+0+0334 <[^>]*> jalr	v1
+0+0338 <[^>]*> nop
+0+033c <[^>]*> move	ra,a0
+0+0340 <[^>]*> jalr	a1
+0+0344 <[^>]*> nop
+0+0348 <[^>]*> jalr	v0,v1
+0+034c <[^>]*> move	ra,a0
+0+0350 <[^>]*> move	v0,ra
+0+0354 <[^>]*> jalr	v0,v1
+0+0358 <[^>]*> nop
 	\.\.\.
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/vr4130.d b/gas/testsuite/gas/mips/vr4130.d
new file mode 100644
index 0000000000..4933d4d9d2
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4130.d
@@ -0,0 +1,705 @@
+#as: -mfix-vr4130 -march=vr4130 -mabi=o64
+#objdump: -dz
+#name: MIPS VR4130 workarounds
+
+.*file format.*
+
+Disassembly.*
+
+.* <foo>:
+#
+# PART A
+#
+.*	mfhi	.*
+.*	mult	.*
+#
+.*	mflo	.*
+.*	mult	.*
+#
+# PART B
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART C
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART D
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+# PART E
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+# PART F
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	addiu	.*
+#
+# PART G
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART H
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART I
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	multu	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmultu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	div	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	divu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddiv	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddivu	.*
+#
+# PART J
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macc	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchi	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchis	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchiu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchius	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccs	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccus	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacc	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchi	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchis	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchiu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchius	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccs	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccus	.*
+#
+# PART K
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	mtlo	.*
+#
+.*	mflo	.*
+.*	mthi	.*
+#
+.*	mfhi	.*
+.*	mtlo	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mthi	.*
+
+.* <bar>:
+#
+# PART A
+#
+.*	mfhi	.*
+.*	mult	.*
+#
+.*	mflo	.*
+.*	mult	.*
+#
+# PART B
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART C
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART D
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+# PART E
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+#
+# PART F
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+#
+# PART G
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART H
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART I
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	multu	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmultu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	div	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	divu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddiv	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddivu	.*
+#pass
diff --git a/gas/testsuite/gas/mips/vr4130.s b/gas/testsuite/gas/mips/vr4130.s
new file mode 100644
index 0000000000..1f1dfcf04f
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4130.s
@@ -0,0 +1,305 @@
+	.macro	check2 insn
+	mflo	$2
+	\insn	$3,$3
+	.endm
+
+	.macro	check3 insn
+	mfhi	$2
+	\insn	$0,$3,$3
+	.endm
+
+	.macro	main func
+
+	.ent	\func
+	.type	\func,@function
+\func:
+
+	# PART A
+	#
+	# Check that mfhis and mflos in .set noreorder blocks are not
+	# considered.
+
+	.set	noreorder
+	mfhi	$2
+	.set	reorder
+	mult	$3,$3
+
+	.set	noreorder
+	mflo	$2
+	.set	reorder
+	mult	$3,$3
+
+	# PART B
+	#
+	# Check for simple instances.
+
+	mfhi	$2
+	mult	$3,$3	# 4 nops
+
+	mfhi	$2
+	addiu	$3,1
+	mult	$4,$4	# 3 nops
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	mult	$7,$7	# 0 nops
+
+	# PART C
+	#
+	# Check that no nops are inserted after the result has been read.
+
+	mfhi	$2
+	addiu	$2,1
+	addiu	$3,1
+	addiu	$4,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$2,1
+	addiu	$4,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$2,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$2,$2
+
+	# PART D
+	#
+	# Check that we still insert the usual interlocking nops in cases
+	# where the VR4130 errata doesn't apply.
+
+	mfhi	$2
+	mult	$2,$2	# 2 nops
+
+	mfhi	$2
+	addiu	$2,1
+	mult	$3,$3	# 1 nop
+
+	mfhi	$2
+	addiu	$3,1
+	mult	$2,$2	# 1 nop
+
+	# PART E
+	#
+	# Check for branches whose targets might be affected.
+
+	mfhi	$2
+	bnez	$3,1f	# 2 nops for normal mode, 3 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	bnez	$3,1f	# 1 nop for normal mode, 2 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$3,1
+	bnez	$3,1f	# 0 nops for normal mode, 1 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$3,1
+	addiu	$3,1
+	bnez	$3,1f	# 0 nops
+
+	# PART F
+	#
+	# As above, but with no dependencies between the branch and
+	# the previous instruction.  The final branch can use the
+	# preceding addiu as its delay slot.
+
+	mfhi	$2
+	addiu	$3,1
+	bnez	$4,1f	# 1 nop for normal mode, 2 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	bnez	$5,1f	# 0 nops for normal mode, 1 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	bnez	$6,1f	# 0 nops, fill delay slot in normal mode
+1:
+
+	# PART G
+	#
+	# Like part B, but check that intervening .set noreorders don't
+	# affect the number of nops.
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	.set	reorder
+	mult	$4,$4	# 3 nops
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	.set	reorder
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	.set	reorder
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	.set	reorder
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	.set	reorder
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	.set	reorder
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	.set	reorder
+	mult	$7,$7	# 0 nops
+
+	# PART H
+	#
+	# Like part B, but the mult occurs in a .set noreorder block.
+
+	mfhi	$2
+	.set	noreorder
+	mult	$3,$3	# 4 nops
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	mult	$4,$4	# 3 nops
+	.set	reorder
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	mult	$7,$7	# 0 nops
+	.set	reorder
+
+	# PART I
+	#
+	# Check every affected multiplication and division instruction.
+
+	check2	mult
+	check2	multu
+	check2	dmult
+	check2	dmultu
+
+	check3	div
+	check3	divu
+	check3	ddiv
+	check3	ddivu
+
+	.end	\func
+	.endm
+
+	.set	nomips16
+	main	foo
+
+	# PART J
+	#
+	# Check every affected multiply-accumulate instruction.
+
+	check3	macc
+	check3	macchi
+	check3	macchis
+	check3	macchiu
+	check3	macchius
+	check3	maccs
+	check3	maccu
+	check3	maccus
+
+	check3	dmacc
+	check3	dmacchi
+	check3	dmacchis
+	check3	dmacchiu
+	check3	dmacchius
+	check3	dmaccs
+	check3	dmaccu
+	check3	dmaccus
+
+	# PART K
+	#
+	# Check that mtlo and mthi are exempt from the VR4130 errata,
+	# although the usual interlocking delay applies.
+
+	mflo	$2
+	mtlo	$3
+
+	mflo	$2
+	mthi	$3
+
+	mfhi	$2
+	mtlo	$3
+
+	mfhi	$2
+	mthi	$3
+
+	.set	mips16
+	main	bar