diff options
| author | mgretton <mgretton> | 2012-08-24 08:06:35 +0000 |
|---|---|---|
| committer | mgretton <mgretton> | 2012-08-24 08:06:35 +0000 |
| commit | de0acea0f7ccd050a5e98d8564ff27fe2ba4a76d (patch) | |
| tree | 27635c4950f984b51af39f067223ef8af85efa8b /gas/config | |
| parent | f1327221eda36e14e008b2049376e5466752fb87 (diff) | |
| download | binutils-redhat-de0acea0f7ccd050a5e98d8564ff27fe2ba4a76d.tar.gz | |
* gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
(NEON_ENC_FPV8_): New define.
(do_vfp_nsyn_fpv8): New function.
(do_vsel): Likewise.
(insns): Add VSEL instructions.
* gas/testsuite/gas/arm/armv8-a+fp.d: New testcase.
* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VSEL.
(print_insn_coprocessor): Add new %<>c bitfield format
specifier.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 93542e3e91..5612d7e58c 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -12341,7 +12341,11 @@ struct neon_tab_entry X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ - X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) + X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \ + X(vseleq, 0xe000a00, N_INV, N_INV), \ + X(vselvs, 0xe100a00, N_INV, N_INV), \ + X(vselge, 0xe200a00, N_INV, N_INV), \ + X(vselgt, 0xe300a00, N_INV, N_INV) enum neon_opc { @@ -12371,6 +12375,8 @@ NEON_ENC_TAB ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) #define NEON_ENC_DOUBLE_(X) \ ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) +#define NEON_ENC_FPV8_(X) \ + ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000)) #define NEON_ENCODE(type, inst) \ do \ @@ -15841,6 +15847,33 @@ do_neon_ldx_stx (void) else inst.instruction |= 0xf4000000; } + +/* FP v8. */ +static void +do_vfp_nsyn_fpv8 (enum neon_shape rs) +{ + NEON_ENCODE (FPV8, inst); + + if (rs == NS_FFF) + do_vfp_sp_dyadic (); + else + do_vfp_dp_rd_rn_rm (); + + if (rs == NS_DDD) + inst.instruction |= 0x100; + + inst.instruction |= 0xf0000000; +} + +static void +do_vsel (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); + + if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS) + first_error (_("invalid instruction shape")); +} + /* Overall per-instruction processing. */ @@ -18044,6 +18077,17 @@ static const struct asm_opcode insns[] = TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs), TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs), + /* FP for ARMv8. */ +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_armv8 +#undef THUMB_VARIANT +#define THUMB_VARIANT & fpu_vfp_ext_armv8 + + nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel), + nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), + nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), + nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ #undef THUMB_VARIANT |