diff options
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 10 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips16-opc.c | 28 |
6 files changed, 39 insertions, 14 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 10bcdda8b4..fb3e49c3d0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * config/tc-mips.c (mips16_ip): Handle "I". + 2013-07-12 Maciej W. Rozycki <macro@codesourcery.com> * config/tc-mips.c (mips_flag_nan2008): New variable. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 7fb870eaed..ef5c466e6e 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -14223,6 +14223,16 @@ mips16_ip (char *str, struct mips_cl_insn *ip) s = expr_end; continue; + case 'I': + my_getExpression (&imm_expr, s); + if (imm_expr.X_op != O_big + && imm_expr.X_op != O_constant) + insn_error = _("absolute expression required"); + if (HAVE_32BIT_GPRS) + normalize_constant_expr (&imm_expr); + s = expr_end; + continue; + case 'a': /* 26 bit address */ case 'i': my_getExpression (&offset_expr, s); diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4d57384529..a96a4ab1ba 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Document MIPS16 "I" opcode. + 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 89ea3e9a71..21128892a9 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1305,6 +1305,8 @@ extern int bfd_mips_num_opcodes; "l" register list for entry instruction "L" register list for exit instruction + "I" an immediate value used for macros + The remaining codes may be extended. Except as otherwise noted, the full extended operand is a 16 bit signed value. "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6478052a59..aa4d0f4606 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands + in macros. + +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for ADDA.S, MULA.S and SUBA.S. diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 357fcc1f82..1e03402117 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -89,26 +89,26 @@ const struct mips_opcode mips16_opcodes[] = {"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, {"b", "q", 0x1000, 0xf800, UBR, 0, I1 }, {"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 }, -{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, {"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 }, {"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, -{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, {"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, -{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, {"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, -{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, {"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, -{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, {"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, -{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, {"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, -{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, {"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, -{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, {"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, -{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, {"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 }, -{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, {"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 }, {"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 }, {"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 }, @@ -155,8 +155,8 @@ const struct mips_opcode mips16_opcodes[] = {"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 }, {"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, {"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 }, -{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 }, -{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 }, +{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 }, +{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 }, {"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 }, {"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 }, {"exit", "", 0xef09, 0xffff, TRAP, 0, I1 }, @@ -230,8 +230,8 @@ const struct mips_opcode mips16_opcodes[] = {"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1 }, {"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, {"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1 }, -{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, -{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 }, +{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 }, {"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 }, {"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 }, {"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 }, |