summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* Remove GOTOFF in ld-i386/nogot1.s.H.J. Lu2010-09-242-1/+6
| | | | | | | 2010-09-23 H.J. Lu <hongjiu.lu@intel.com> PR ld/11812 * ld-i386/nogot1.s: Don't use GOTOFF.
* * scripttempl/armcoff.sc: Revert 2010-09-22 change.Dave Korn2010-09-242-26/+5
|
* daily updateAlan Modra2010-09-241-1/+1
|
* bfd/Bernd Schmidt2010-09-234-0/+97
| | | | | | | | * elf32-tic6x.c (elf32_tic6x_fake_sections): New function. (elf_backend_fake_sections): Define. ld/testsuite/ * ld-tic6x/pcrel-reloc-local-r-rel-rela.d: New test.
* * bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value.mgretton2010-09-2315-51/+676
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * gas/config/tc-arm.c (arm_ext_virt): New variable. (arm_reg_type): Add REG_TYPE_RNB for banked registers. (reg_entry): Allow registers to be larger than a byte. (reg_alias): Fix type warning. (parse_operands): Parse banked registers when appropriate. (do_mrs): Add support for Virtualization Extensions. (do_hvc): New function. (do_t_mrs): Add support for Virtualization Extensions. (do_t_msr): Likewise. (do_t_hvc): New function. (SPLRBANK): New define. (reg_names): Add banked registers. (insns): Add support for Virtualization Extensions. (md_apply_fixup): Likewise. (arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions. (arm_extensions): Add 'virt' extension. (aeabi_set_public_attributes): Add support for Virtualization Extensions. * gas/doc/c-arm.texi: Document 'virt' extension. * gas/testsuite/gas/arm/armv7-a+virt.d: New test. * gas/testsuite/gas/arm/armv7-a+virt.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions. * gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test. * gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise. * include/opcode/arm.h (ARM_EXT_VIRT): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization Extensions. * opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. (thumb32_opcodes): Likewise. (banked_regname): New function. (print_insn_arm): Add Virtualization Extensions support. (print_insn_thumb32): Likewise.
* * gas/config/tc-arm.c (arm_ext_adiv): New variable.mgretton2010-09-2312-10/+112
| | | | | | | | | | | | | | | | | | (do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.
* * config/tc-arm.c (arm_ext_v6m): New variable.mgretton2010-09-2312-3/+104
| | | | | | | | | | | | | | | | | | | | | | (arm_ext_m): Add support for OS extension. (arm_ext_os): New variable. (do_t_swi): In v6-M ensure we have the OS extension. (arm_cpus): The cortex-m1 and cortex-m0 options have the OS extension by default. (arm_archs): Add armv6s-m. (arm_extensions): Add 'os' extension. (cpu_arch_ver): Add support for v6S-M. * gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m architecture options. * gas/testsuite/gas/arm/archv6s-m-bad.d: New test. * gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise. * gas/testsuite/gas/arm/archv6s-m.d: Likewise. * gas/testsuite/gas/arm/archv6s-m.s: Likewise. * gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise. * include/opcode/arm.h (ARM_EXT_OS): New define. (ARM_AEXT_V6SM): Likewise. (ARM_ARCH_V6SM): Likewise.
* * gas/config/tc-arm.c (arm_ext_v6z): Remove.mgretton2010-09-2322-19/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (arm_ext_sec): New variable. (do_t_smc): In Thumb state SMC requires v7-A. (insns): Make SMC depend on Security Extensions. (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. (arm_extensions): Add 'sec' extension. (cpu_arch_ver): Reorder. (aeabi_set_public_attributes): Emit Tag_Virtualization_use as appropriate. * gas/doc/c-arm.texi: Document Security Extensions. * gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions.. * gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test. * gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions. * gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test. * gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions. * gas/testsuite/gas/arm/thumb32.d: Likewise. * gas/testsuite/gas/arm/thumb32.s: Likewise. * include/opcode/arm.h (ARM_EXT_V6Z): Remove. (ARM_EXT_SEC): New define. (ARM_AEXT_V6Z): Use Security Extensions. (ARM_AEXT_V6ZK): Likeiwse. (ARM_AEXT_V6ZT2): Likewise. (ARM_AEXT_V6ZKT2): Likewise. (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. (ARM_ARCH_V7A_SEC): New define. (ARM_ARCH_V7A_MP): Rename... (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. * ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions. (thumb32_opcodes): Likewise.
* * gas/config/tc-arm.c (arm_ext_mp): Add.mgretton2010-09-2316-5/+197
| | | | | | | | | | | | | | | | | | | | | | | (do_pld): Update comment. (insns): Add support for pldw. (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support MP extension. (arm_extensions): Add 'mp' extension. (aeabi_set_public_attributes): Emit correct build attribute when MP extension is enabled. * gas/doc/c-arm.texi: Update for MP extensions. * gas/testsuite/gas/arm/arch7a-mp.d: Add. * gas/testsuite/gas/arm/arch7ar-mp.s: Likewise. * gas/testsuite/gas/arm/arch7r-mp.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension. * gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add. * gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise. * include/opcode/arm.h (ARM_EXT_MP): Add. (ARM_ARCH_V7A_MP): Likewise. * opcodes/arm-dis.c (arm_opcodes): Add support for pldw. (thumb32_opcodes): Likewise.
* * gas/config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.mgretton2010-09-233-23/+199
| | | | | | | | | | | | | | (arm_option_extension_value_table): Add. (arm_extensions): Change type. (arm_option_cpu_table): Rename... (arm_option_fpu_table): ...to this. (arm_fpus): Change type. (arm_parse_extension): Enforce alphabetical order. Allow extensions to be removed. (arm_parse_arch): Allow extensions to be specified with -march. (s_arm_arch_extension): Add. (s_arm_fpu): Update for type changes. * gas/doc/c-arm.texi: Document changes to infrastructure.
* * ld-elf/elf.exp: Don't run --gc-sections tls var test on v850.Alan Modra2010-09-2310-35/+85
| | | | | | | | | | | | | * ld-elf/group2.d: xfail xstormy. * ld-elf/group4.d: Likewise. * ld-elf/group5.d: Likewise. * ld-elf/group6.d: Likewise. * ld-elf/init-fini-arrays.d: xfail cr16 and crx. * ld-elf/orphan2.d: xfail xstormy. * ld-elf/sec64k.exp: Don't run on targets using generic linker. Allow a larger range for ld -r expected bar_1 section. Don't run final link test on a number of targets. Select avr6 for avr targets. * ld-elfcomm/elfcomm.exp: Don't attempt on hpux.
* * gas/all/gas.exp: Update "forward" and "redef3" xfails.Alan Modra2010-09-234-7/+15
| | | | | * gas/m68k/all.exp: Don't xfail pcrel on uclinux. * gas/sh/arch/arch.exp: Don't pass dashes to send_log.
* * config/tc-mn10300.c (tc_gen_reloc): Replace absolute symbolsAlan Modra2010-09-232-8/+14
| | | | with the absolute section symbol.
* * binutils-all/ar.exp: Don't run unique_symbol on msp or hpux.Alan Modra2010-09-235-4/+18
| | | | | | | * binutils-all/copy-2.d: Update not-target list. * binutils-all/note-1.d: Don't run on h8300. * binutils-all/objcopy.exp: Don't run strip-10 on msp or hpux. (objcopy_test): Remove h8300-rtems from xfails.
* * ld-d10v/reloc-007.d: Don't error.Alan Modra2010-09-236-7/+19
| | | | | | | * ld-d10v/reloc-008.d: Likewise. * ld-d10v/reloc-015.d: Likewise. * ld-d10v/reloc-016.d: Likewise. * ld-d10v/reloc-012.ld: Use a sane offset.
* * cpu-d10v.c: Make bits_per_address 18 for all arch_info entries.Alan Modra2010-09-232-10/+14
|
* ld/Alan Modra2010-09-234-4/+14
| | | | | | | | * ldlang.c (lang_add_section): Don't copy SEC_RELOC from input to output section on a final link. bfd/ * elf.c (_bfd_elf_init_private_section_data): Allow for SEC_RELOC difference between input and output section.
* * gas/mips/jal.d: Remove duplicate pattern.Maciej W. Rozycki2010-09-232-1/+5
|
* daily updateAlan Modra2010-09-231-1/+1
|
* opcodes: blackfin: fix decoding of 32bit addresses on 64bit systemsMike Frysinger2010-09-222-0/+7
| | | | | | | | | | | | The Blackfin ISA is very exact with regards to address truncation when under/over flowing its 32bit range. On a 32bit system, things work the same and so addresses are decoded properly. On a 64bit system though, the decoded addresses may include the bits that are supposed to have been truncated. So force a 32bit truncation after the address has been calculated. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of all register move insnsMike Frysinger2010-09-222-12/+34
| | | | | | | | Many register move insns were not being decoded properly, so rewrite the whole function to be a bit more manageable in terms of valid combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of many invalid insnsMike Frysinger2010-09-222-21/+127
| | | | | | | | | | | | | | The Blackfin disassembler was originally based on the premise of parsing valid opcodes all the time, so some of the opcode checking can be a bit fuzzy. This is exemplified in decoding of parallel insns where many times things are decoded as invalid when in reality, they may not be used in parallel combinations. So add parallel checking to most insn decoding routines so we see ILLEGAL and not just whatever insn happens to be close to a valid mnemonic, as well as some additional sub-opcode checks. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegalMike Frysinger2010-09-222-0/+7
| | | | | | | | The push/pop multiple insn has a 3 bit field for the P register range, but only values of 0...5 are valid (P0 - P5). There is no such P6 or P7 register, so mark these insns as illegal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of vector shift insn w/saturationMike Frysinger2010-09-222-1/+5
| | | | | | | | The saturation bit was missed when decoding a vector shift insn leading to the output looking the same as the non-saturating insn. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode all ASTAT bitsMike Frysinger2010-09-222-8/+25
| | | | | | | | All ASTAT bits work in the hardware even though they aren't part of the official Blackfin ISA. So decode every ASTAT field to make the output a bit nicer when working with hand generated opcodes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode insns with invalid register as illegalMike Frysinger2010-09-222-14/+28
| | | | | | | | | Sometimes the encoding in the opcode is a 4 bit field which defines a register number. However, register numbers are only 0-7, so make sure we call illegal for when the opcode register number is greater than 8. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* MAINTAINERS: add myself for Blackfin partsMike Frysinger2010-09-222-0/+5
| | | | | | | | I know a thing or two about Blackfin parts, and if I can't find the answer, I can usually locate someone who does. Especially since Jie and Bernd no longer work for ADI :(. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix typo in BYTEOP16P commentMike Frysinger2010-09-222-1/+5
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: reject multiple store insns in parallel insnsMike Frysinger2010-09-222-0/+38
| | | | | | | | Check for & reject attempts to use multiple store insns in a single parallel insn combination. These are illegal per the Blackfin ISA. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: add missing register move insnsMike Frysinger2010-09-223-2/+10
| | | | | | | | The Blackfin ISA supports moving just about anything to/from EMUDAT, so make sure the assembler accepts these insns too. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: clarify some errors with register usage in insnsMike Frysinger2010-09-224-4/+12
| | | | | | | | Using "Register mismatch" everywhere can be a bit vague, so clarify why exactly we're barfing on these unsupported insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger2010-09-228-3/+193
| | | | | | | | | Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: handle multibyte symbolsMike Frysinger2010-09-222-1/+5
| | | | | | | | | | Accept any 8bit char with the high bit set so as to support multibyte characters. Also use the locale safe regular expressions to match chars/digits. This brings the Blackfin assembler inline with the behavior of other assemblers. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: handle more ASTAT flagsMike Frysinger2010-09-225-5/+28
| | | | | | | | Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: support OUTC debug insnMike Frysinger2010-09-228-4/+88
| | | | | | | | | The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of LSHIFT insnsMike Frysinger2010-09-228-14/+24
| | | | | | | | | | The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT, ASHIFT, or BXORSHIFT. So be specific when disassembling. As fall out of this change, we need to update some assembler tests. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: constify formatting related structuresMike Frysinger2010-09-222-22/+30
| | | | | | | No need for these local structures related to formatting of output to be writable, so constify the whole shebang. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: support ABORT debug insnMike Frysinger2010-09-223-1/+12
| | | | | | | | There is a pseudo debug insn named ABORT that is commonly used in simulation, so support it in the assembler too. The disassembler already supports it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: add support for BF51x-0.2 processorsMike Frysinger2010-09-222-0/+8
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: add support for BF592 processorsMike Frysinger2010-09-223-3/+14
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: allow end-of-line comments via #Mike Frysinger2010-09-222-2/+6
| | | | | | | We don't use the # character in the Blackfin assembly language, so let it start end-of-line comments like most other assemblers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 2010-09-22 Kai Tietz <kai.tietz@onevision.com>Kai Tietz2010-09-223-4/+22
| | | | | | | | * ldlang.c (lang_add_section): Allow for debugging section to be marked as noload but to keep content. (IGNORE_SECTION): Likewise. (lang_check_section_addresses): Likewise. * ldwrite.c (build_link_order): Likewise.
* 2010-09-22 Kai Tietz <kai.tietz@onevision.com>Kai Tietz2010-09-222-14/+36
| | | | | | | * coffcode.h (sec_to_styp_flags): Adjust debug sections to be conform to pe-coff specification and avoid marking them as excluded. (styp_to_sec_flags): Doing reverse mapping.
* 2010-09-22 Kai Tietz <kai.tietz@onevision.com>Kai Tietz2010-09-226-13/+76
| | | | | | | | | | * emultempl/pe.em (gld_${EMULATION_NAME}_place_orphan): Add idata to orphan set. * emultempl/pep.em: Likewise. * scripttempl/armcoff.sc: Separate idata and add __IAT_start__ and __IAT_end__ labels. * scripttempl/pe.sc: Likewise. * scripttempl/pep.sc: Likewise.
* 2010-09-22 Kai Tietz <kai.tietz@onevision.com>Kai Tietz2010-09-222-0/+48
| | | | | * peXXigen.c (_bfd_XXi_final_link_postscript): Add handling for setting IAT directory entry.
* daily updateAlan Modra2010-09-221-1/+1
|
* opcodes: blackfin: strip trailing whitespaceMike Frysinger2010-09-212-71/+75
|
* daily updateAlan Modra2010-09-211-1/+1
|
* * emulparams/elf32_sparc.sh: Set NOP to 0x01000000David S. Miller2010-09-202-0/+5
|
* * gas/config/tc-arm.c (arm_cpus): Correct canonical names for Cortex CPUs.mgretton2010-09-209-16/+35
| | | | | | | | | | | * gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical CPU name. * gas/testsuite/gas/arm/attr-mcpu.d: Likewise. * ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical CPU name. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * ld/testsuite/ld-arm/attr-merge-2.attr: Likewise. * ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
View Lorry Controller Status