From 46ed62ce546cc6546a1551ba7df47374f3a704ae Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Fri, 8 Mar 2013 17:25:11 +0000 Subject: PR binutils/15241 * lm32.cpu (Control and status registers): Add CFG2, PSW, TLBVADDR, TLBPADDR and TLBBADVADDR. * lm32-desc.c: Regenerate. --- cpu/ChangeLog | 6 ++++++ cpu/lm32.cpu | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ChangeLog b/cpu/ChangeLog index ee902521e9..e5a83617c3 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,9 @@ +2013-03-08 Yann Sionneau + + PR binutils/15241 + * lm32.cpu (Control and status registers): Add CFG2, PSW, + TLBVADDR, TLBPADDR and TLBBADVADDR. + 2012-11-30 Oleg Raikhman Joern Rennecke diff --git a/cpu/lm32.cpu b/cpu/lm32.cpu index 31b943d79e..83c839f339 100644 --- a/cpu/lm32.cpu +++ b/cpu/lm32.cpu @@ -1,5 +1,5 @@ ; Lattice Mico32 CPU description. -*- Scheme -*- -; Copyright 2008, 2009 Free Software Foundation, Inc. +; Copyright 2008-2013 Free Software Foundation, Inc. ; Contributed by Jon Beniston ; ; This file is part of the GNU Binutils. @@ -101,9 +101,11 @@ (EBA 7) (DC 8) (DEBA 9) + (CFG2 10) (JTX 14) (JRX 15) (BP0 16) (BP1 17) (BP2 18) (BP3 19) (WP0 24) (WP1 25) (WP2 26) (WP3 27) + (PSW 29) (TLBVADDR 30) (TLBPADDR 31) (TLBBADVADDR 31) ) ) () () -- cgit v1.2.1