From 12c5aa08f31c92313ce21dded5c0c9074fbb4042 Mon Sep 17 00:00:00 2001 From: mgretton Date: Fri, 17 Sep 2010 10:13:39 +0000 Subject: 2010-09-17 Tejas Belagod * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. --- gas/config/tc-arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gas/config/tc-arm.c') diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index f1ffe9c4a8..cebf2df813 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -16704,7 +16704,7 @@ static const struct asm_opcode insns[] = TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), - TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ -- cgit v1.2.1