From b1b7556e4d9d72a2a0b05a0408452cce2bb878c2 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 10 Jan 2013 19:51:53 +0000 Subject: Remove trailing white spaces on gas * app.c: Remove trailing white spaces. * as.c: Likewise. * as.h: Likewise. * cond.c: Likewise. * dw2gencfi.c: Likewise. * dwarf2dbg.h: Likewise. * ecoff.c: Likewise. * input-file.c: Likewise. * itbl-lex.h: Likewise. * output-file.c: Likewise. * read.c: Likewise. * sb.c: Likewise. * subsegs.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. * config/tc-i386.c: Likewise. * doc/Makefile.am: Likewise. * doc/Makefile.in: Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-alpha.texi: Likewise. * doc/c-arc.texi: Likewise. * doc/c-arm.texi: Likewise. * doc/c-avr.texi: Likewise. * doc/c-bfin.texi: Likewise. * doc/c-cr16.texi: Likewise. * doc/c-d10v.texi: Likewise. * doc/c-d30v.texi: Likewise. * doc/c-h8300.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-i860.texi: Likewise. * doc/c-m32c.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68hc11.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-microblaze.texi: Likewise. * doc/c-mips.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-mt.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-score.texi: Likewise. * doc/c-sh.texi: Likewise. * doc/c-sh64.texi: Likewise. * doc/c-tic54x.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xc16x.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * doc/c-z80.texi: Likewise. * doc/internals.texi: Likewise. --- gas/doc/Makefile.am | 6 +- gas/doc/Makefile.in | 12 ++-- gas/doc/c-aarch64.texi | 4 +- gas/doc/c-alpha.texi | 14 ++--- gas/doc/c-arc.texi | 26 ++++---- gas/doc/c-arm.texi | 62 +++++++++---------- gas/doc/c-avr.texi | 52 ++++++++-------- gas/doc/c-bfin.texi | 14 ++--- gas/doc/c-cr16.texi | 28 ++++----- gas/doc/c-d10v.texi | 36 +++++------ gas/doc/c-d30v.texi | 20 +++--- gas/doc/c-h8300.texi | 4 +- gas/doc/c-hppa.texi | 10 +-- gas/doc/c-i370.texi | 56 ++++++++--------- gas/doc/c-i386.texi | 12 ++-- gas/doc/c-i860.texi | 10 +-- gas/doc/c-m32c.texi | 14 ++--- gas/doc/c-m32r.texi | 20 +++--- gas/doc/c-m68hc11.texi | 4 +- gas/doc/c-m68k.texi | 6 +- gas/doc/c-microblaze.texi | 22 +++---- gas/doc/c-mips.texi | 2 +- gas/doc/c-msp430.texi | 50 +++++++-------- gas/doc/c-mt.texi | 2 +- gas/doc/c-s390.texi | 24 ++++---- gas/doc/c-score.texi | 56 ++++++++--------- gas/doc/c-sh.texi | 154 +++++++++++++++++++++++----------------------- gas/doc/c-sh64.texi | 2 +- gas/doc/c-tic54x.texi | 48 +++++++-------- gas/doc/c-tic6x.texi | 2 +- gas/doc/c-v850.texi | 10 +-- gas/doc/c-xc16x.texi | 4 +- gas/doc/c-xgate.texi | 2 +- gas/doc/c-xtensa.texi | 4 +- gas/doc/c-z80.texi | 36 +++++------ gas/doc/internals.texi | 2 +- 36 files changed, 415 insertions(+), 415 deletions(-) (limited to 'gas/doc') diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index e7e1be5b9e..b200378ba6 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -6,12 +6,12 @@ # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3 of the License, or # (at your option) any later version. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; see the file COPYING3. If not see # . @@ -32,7 +32,7 @@ POD2MAN = pod2man --center="GNU Development Tools" \ man_MANS = as.1 -info_TEXINFOS = as.texinfo +info_TEXINFOS = as.texinfo as_TEXINFOS = asconfig.texi $(CPU_DOCS) AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index 4d0eb6dd10..9969ff4d33 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -22,12 +22,12 @@ # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3 of the License, or # (at your option) any later version. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; see the file COPYING3. If not see # . @@ -279,7 +279,7 @@ POD2MAN = pod2man --center="GNU Development Tools" \ --release="binutils-$(VERSION)" --section=1 man_MANS = as.1 -info_TEXINFOS = as.texinfo +info_TEXINFOS = as.texinfo as_TEXINFOS = asconfig.texi $(CPU_DOCS) AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \ -I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc @@ -410,17 +410,17 @@ as.info: as.texinfo $(as_TEXINFOS) fi; \ rm -rf $$backupdir; exit $$rc -as.dvi: as.texinfo $(as_TEXINFOS) +as.dvi: as.texinfo $(as_TEXINFOS) TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \ $(TEXI2DVI) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo -as.pdf: as.texinfo $(as_TEXINFOS) +as.pdf: as.texinfo $(as_TEXINFOS) TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \ $(TEXI2PDF) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo -as.html: as.texinfo $(as_TEXINFOS) +as.html: as.texinfo $(as_TEXINFOS) rm -rf $(@:.html=.htp) if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \ -o $(@:.html=.htp) `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \ diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 5a59f449ac..3939fee5f0 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -104,7 +104,7 @@ Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} instructions can be generated by prefixing the label with @samp{#:pg_hi21:} and @samp{#:lo12:} respectively. -For example to use 33-bit (+/-4GB) pc-relative addressing to +For example to use 33-bit (+/-4GB) pc-relative addressing to load the address of @var{foo} into x0: @smallexample @@ -236,7 +236,7 @@ should only be done if it is really necessary. @cindex opcodes for AArch64 @code{@value{AS}} implements all the standard AArch64 opcodes. It also implements several pseudo opcodes, including several synthetic load -instructions. +instructions. @table @code diff --git a/gas/doc/c-alpha.texi b/gas/doc/c-alpha.texi index 8e2c11b464..dd484138ff 100644 --- a/gas/doc/c-alpha.texi +++ b/gas/doc/c-alpha.texi @@ -48,7 +48,7 @@ assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the @code{.arch} directive. -The following processor names are recognized: +The following processor names are recognized: @code{21064}, @code{21064a}, @code{21066}, @@ -167,7 +167,7 @@ The 32 floating-point registers are referred to as @samp{$f@var{n}}. @cindex relocations, Alpha Some of these relocations are available for ECOFF, but mostly -only for ELF. They are modeled after the relocation format +only for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions. The format is @samp{!@var{tag}} or @samp{!@var{tag}!@var{number}} @@ -243,13 +243,13 @@ jsr $26,($27),foo !lituse_jsr!1 @item !lituse_tlsgd!@var{N} Used with a register branch format instruction to indicate that the -literal is the call to @code{__tls_get_addr} used to compute the +literal is the call to @code{__tls_get_addr} used to compute the address of the thread-local storage variable whose descriptor was loaded with @code{!tlsgd!@var{N}}. @item !lituse_tlsldm!@var{N} Used with a register branch format instruction to indicate that the -literal is the call to @code{__tls_get_addr} used to compute the +literal is the call to @code{__tls_get_addr} used to compute the address of the base of the thread-local storage block for the current module. The descriptor for the module must have been loaded with @code{!tlsldm!@var{N}}. @@ -259,7 +259,7 @@ Used with @code{ldah} and @code{lda} to load the GP from the current address, a-la the @code{ldgp} macro. The source register for the @code{ldah} instruction must contain the address of the @code{ldah} instruction. There must be exactly one @code{lda} instruction paired -with the @code{ldah} instruction, though it may appear anywhere in +with the @code{ldah} instruction, though it may appear anywhere in the instruction stream. The immediate operands must be zero. @example @@ -401,8 +401,8 @@ used in some non-standard way and so the linker cannot elide the load of the procedure vector during relaxation. @item .usepv @var{function}, @var{which} -Used to indicate the use of the @code{$27} register, similar to -@code{.prologue}, but without the other semantics of needing to +Used to indicate the use of the @code{$27} register, similar to +@code{.prologue}, but without the other semantics of needing to be inside an open @code{.ent}/@code{.end} block. The @var{which} argument should be either @code{no}, indicating that diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi index ea0fa4eb52..ec7eff4e66 100644 --- a/gas/doc/c-arc.texi +++ b/gas/doc/c-arc.texi @@ -151,10 +151,10 @@ using this directive. The first parameter is the @var{name} of the new auxiallry register. The second parameter is the @var{address} of the register in the auxiliary register memory map for the variant of the ARC. The third parameter specifies the @var{mode} in which the -register can be operated is and it can be one of: +register can be operated is and it can be one of: @table @code -@item r (readonly) +@item r (readonly) @item w (write only) @item r|w (read or write) @end table @@ -178,7 +178,7 @@ specify extra condition codes with any values. For example: @smallexample .extCondCode is_busy,0x14 - + add.is_busy r1,r2,r3 bis_busy _main @end smallexample @@ -187,10 +187,10 @@ specify extra condition codes with any values. For example: @item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} Specifies an extension core register @var{name} for the application. This allows a register @var{name} with a valid @var{regnum} between 0 -and 60, with the following as valid values for @var{mode} +and 60, with the following as valid values for @var{mode} @table @samp -@item @emph{r} (readonly) +@item @emph{r} (readonly) @item @emph{w} (write only) @item @emph{r|w} (read or write) @end table @@ -222,7 +222,7 @@ by the user. The parameters are: @table @bullet @item @var{name} -Name of the extension instruction +Name of the extension instruction @item @var{opcode} Opcode to be used. (Bits 27:31 in the encoding). Valid values @@ -234,7 +234,7 @@ correct value also depends on @var{syntaxclass} @item @var{suffixclass} Determines the kinds of suffixes to be allowed. Valid values are -@code{SUFFIX_NONE}, @code{SUFFIX_COND}, +@code{SUFFIX_NONE}, @code{SUFFIX_COND}, @code{SUFFIX_FLAG} which indicates the absence or presence of conditional suffixes and flag setting by the extension instruction. It is also possible to specify that an instruction sets the flags and @@ -246,9 +246,9 @@ following values: @table @code @item @code{SYNTAX_2OP}: -2 Operand Instruction +2 Operand Instruction @item @code{SYNTAX_3OP}: -3 Operand Instruction +3 Operand Instruction @end table In addition there could be modifiers for the syntax class as described @@ -262,7 +262,7 @@ Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with SYNTAX_3OP as given in the example below. This could usually be used -to set the flags using specific instructions and not retain results. +to set the flags using specific instructions and not retain results. @item @code{OP1_IMM_IMPLIED}: Modifies syntax class SYNTAX_20P, it specifies that there is an @@ -270,7 +270,7 @@ implied immediate destination operand which does not appear in the syntax. For example, if the source code contains an instruction like: @smallexample -inst r1,r2 +inst r1,r2 @end smallexample it really means that the first argument is an implied immediate (that @@ -278,7 +278,7 @@ is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it with SYNTAX_20P. -@end itemize +@end itemize @end table For example, defining 64-bit multiplier with immediate operands: @@ -290,7 +290,7 @@ For example, defining 64-bit multiplier with immediate operands: The above specifies an extension instruction called mp64 which has 3 operands, sets the flags, can be used with a condition code, for which the -first operand is an immediate. (Equivalent to discarding the result +first operand is an immediate. (Equivalent to discarding the result of the operation). @smallexample diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 7d622efb65..983434f166 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -38,7 +38,7 @@ This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are -recognized: +recognized: @code{arm1}, @code{arm2}, @code{arm250}, @@ -131,25 +131,25 @@ recognized: @code{i80200} (Intel XScale processor) @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and -@code{xscale}. +@code{xscale}. The special name @code{all} may be used to allow the assembler to accept instructions valid for any ARM processor. -In addition to the basic instruction set, the assembler can be told to -accept various extension mnemonics that extend the processor using the +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, @code{-mcpu=arm920+maverick} -is equivalent to specifying @code{-mcpu=ep9312}. +is equivalent to specifying @code{-mcpu=ep9312}. -Multiple extensions may be specified, separated by a @code{+}. The +Multiple extensions may be specified, separated by a @code{+}. The extensions should be specified in ascending alphabetical order. -Some extensions may be restricted to particular architectures; this is +Some extensions may be restricted to particular architectures; this is documented in the list of extensions below. -Extension mnemonics may also be removed from those the assembler accepts. -This is done be prepending @code{no} to the option that adds the extension. -Extensions that are removed should be listed after all extensions which have -been added, again in ascending alphabetical order. For example, +Extension mnemonics may also be removed from those the assembler accepts. +This is done be prepending @code{no} to the option that adds the extension. +Extensions that are removed should be listed after all extensions which have +been added, again in ascending alphabetical order. For example, @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. @@ -164,7 +164,7 @@ The following extensions are currently supported: @code{os} (Operating System for v6M architecture), @code{sec} (Security Extensions for v6K and v7-A architectures), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), -@code{virt} (Virtualization Extensions for v7-A architecture, implies +@code{virt} (Virtualization Extensions for v7-A architecture, implies @code{idiv}), and @code{xscale}. @@ -173,8 +173,8 @@ and @item -march=@var{architecture}[+@var{extension}@dots{}] This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which -will not execute on the target architecture. The following architecture -names are recognized: +will not execute on the target architecture. The following architecture +names are recognized: @code{armv1}, @code{armv2}, @code{armv2a}, @@ -218,7 +218,7 @@ extension options as the @code{-mcpu} option. This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble -an instruction which will not execute on the target floating point unit. +an instruction which will not execute on the target floating point unit. The following format options are recognized: @code{softfpa}, @code{fpe}, @@ -260,14 +260,14 @@ In addition to determining which instructions are assembled, this option also affects the way in which the @code{.double} assembler directive behaves when assembling little-endian code. -The default is dependent on the processor selected. For Architecture 5 or -later, the default is to assembler for VFP instructions; for earlier +The default is dependent on the processor selected. For Architecture 5 or +later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions. @cindex @code{-mthumb} command line option, ARM @item -mthumb This option specifies that the assembler should start assembling Thumb -instructions; that is, it should behave as though the file starts with a +instructions; that is, it should behave as though the file starts with a @code{.code 16} directive. @cindex @code{-mthumb-interwork} command line option, ARM @@ -303,7 +303,7 @@ Calling Standard. @cindex @code{-matpcs} command line option, ARM @item -matpcs -This option specifies that the output generated by the assembler should +This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can @@ -546,13 +546,13 @@ boundary). This is for compatibility with ARM's own assembler. Select the target architecture. Valid values for @var{name} are the same as for the @option{-march} commandline option. -Specifying @code{.arch} clears any previously selected architecture +Specifying @code{.arch} clears any previously selected architecture extensions. @cindex @code{.arch_extension} directive, ARM @item .arch_extension @var{name} -Add or remove an architecture extension to the target architecture. Valid -values for @var{name} are the same as those accepted as architectural +Add or remove an architecture extension to the target architecture. Valid +values for @var{name} are the same as those accepted as architectural extensions by the @option{-mcpu} commandline option. @code{.arch_extension} may be used multiple times to add or remove extensions @@ -592,7 +592,7 @@ selects Thumb, with the value 32 selecting ARM. Select the target processor. Valid values for @var{name} are the same as for the @option{-mcpu} commandline option. -Specifying @code{.cpu} clears any previously selected architecture +Specifying @code{.cpu} clears any previously selected architecture extensions. @c DDDDDDDDDDDDDDDDDDDDDDDDDD @@ -658,7 +658,7 @@ The @var{value} is either a @code{number}, @code{"string"}, or @code{number, "string"} depending on the tag. Note - the following legacy values are also accepted by @var{tag}: -@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, +@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, @cindex @code{.even} directive, ARM @@ -950,7 +950,7 @@ used in favour of @code{.save} for saving VFP registers for ARMv6 and above. @cindex opcodes for ARM @code{@value{AS}} implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load -instructions. +instructions. @table @code @@ -964,7 +964,7 @@ This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0. @cindex @code{LDR reg,=