From d4a43bac050595a771afa3b7fafd3115d9603793 Mon Sep 17 00:00:00 2001 From: Joern Rennecke Date: Thu, 26 Feb 2004 16:14:42 +0000 Subject: 2004-02-23 Andrew Stubbs gas: * tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01 nibble types to assembler. opcodes: * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to ensure that double registers have even numbers. Add REG_N_B01 for nn01 (binary 01) nibble to ensure that reserved instruction 0xfffd does not decode the same as 0xfdfd (ftrv). * sh-opc.h: Add REG_N_D nibble type and use it whereever REG_N refers to a double register. Add REG_N_B01 nibble type and use it instead of REG_NM in ftrv. Adjust the bit patterns in a few comments. --- opcodes/sh-dis.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'opcodes/sh-dis.c') diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c index 70fdffb48e..2512f966d3 100644 --- a/opcodes/sh-dis.c +++ b/opcodes/sh-dis.c @@ -577,12 +577,21 @@ print_insn_sh (memaddr, info) case IMM1_8BY4: imm = ((nibs[2] << 4) | nibs[3]) << 2; goto ok; + case REG_N_D: + if ((nibs[n] & 1) != 0) + goto fail; + /* fall through */ case REG_N: rn = nibs[n]; break; case REG_M: rm = nibs[n]; break; + case REG_N_B01: + if ((nibs[n] & 0x3) != 1 /* binary 01 */) + goto fail; + rn = (nibs[n] & 0xc) >> 2; + break; case REG_NM: rn = (nibs[n] & 0xc) >> 2; rm = (nibs[n] & 0x3); -- cgit v1.2.1