From 5500a97a2ad1735db5b35bc51cfb825c1f4c38df Mon Sep 17 00:00:00 2001 From: Lorry Tar Creator Date: Tue, 23 Dec 2014 14:38:46 +0000 Subject: Imported from /home/lorry/working-area/delta_binutils-tarball/binutils-2.25.tar.bz2. --- cpu/ChangeLog | 879 ++++ cpu/cris.cpu | 4553 +++++++++++++++++++ cpu/epiphany.cpu | 2936 ++++++++++++ cpu/epiphany.opc | 416 ++ cpu/fr30.cpu | 1861 ++++++++ cpu/fr30.opc | 253 ++ cpu/frv.cpu | 9803 +++++++++++++++++++++++++++++++++++++++++ cpu/frv.opc | 1921 ++++++++ cpu/ip2k.cpu | 1480 +++++++ cpu/ip2k.opc | 633 +++ cpu/iq10.cpu | 1112 +++++ cpu/iq2000.cpu | 1196 +++++ cpu/iq2000.opc | 320 ++ cpu/iq2000m.cpu | 631 +++ cpu/lm32.cpu | 934 ++++ cpu/lm32.opc | 235 + cpu/m32c.cpu | 10521 ++++++++++++++++++++++++++++++++++++++++++++ cpu/m32c.opc | 1182 +++++ cpu/m32r.cpu | 2437 ++++++++++ cpu/m32r.opc | 347 ++ cpu/mep-avc.cpu | 1423 ++++++ cpu/mep-avc2.cpu | 1987 +++++++++ cpu/mep-c5.cpu | 281 ++ cpu/mep-core.cpu | 3082 +++++++++++++ cpu/mep-default.cpu | 27 + cpu/mep-ext-cop.cpu | 25 + cpu/mep-fmax.cpu | 340 ++ cpu/mep-h1.cpu | 49 + cpu/mep-ivc2.cpu | 9777 ++++++++++++++++++++++++++++++++++++++++ cpu/mep-rhcop.cpu | 342 ++ cpu/mep-sample-ucidsp.cpu | 120 + cpu/mep.cpu | 21 + cpu/mep.opc | 1669 +++++++ cpu/mt.cpu | 1352 ++++++ cpu/mt.opc | 472 ++ cpu/or1k.cpu | 131 + cpu/or1k.opc | 421 ++ cpu/or1kcommon.cpu | 360 ++ cpu/or1korbis.cpu | 1145 +++++ cpu/or1korfpx.cpu | 222 + cpu/sh.cpu | 369 ++ cpu/sh.opc | 77 + cpu/sh64-compact.cpu | 1748 ++++++++ cpu/sh64-media.cpu | 1733 ++++++++ cpu/simplify.inc | 218 + cpu/xc16x.cpu | 3146 +++++++++++++ cpu/xc16x.opc | 290 ++ cpu/xstormy16.cpu | 1965 +++++++++ cpu/xstormy16.opc | 168 + 49 files changed, 76610 insertions(+) create mode 100644 cpu/ChangeLog create mode 100644 cpu/cris.cpu create mode 100644 cpu/epiphany.cpu create mode 100644 cpu/epiphany.opc create mode 100644 cpu/fr30.cpu create mode 100644 cpu/fr30.opc create mode 100644 cpu/frv.cpu create mode 100644 cpu/frv.opc create mode 100644 cpu/ip2k.cpu create mode 100644 cpu/ip2k.opc create mode 100644 cpu/iq10.cpu create mode 100644 cpu/iq2000.cpu create mode 100644 cpu/iq2000.opc create mode 100644 cpu/iq2000m.cpu create mode 100644 cpu/lm32.cpu create mode 100644 cpu/lm32.opc create mode 100644 cpu/m32c.cpu create mode 100644 cpu/m32c.opc create mode 100644 cpu/m32r.cpu create mode 100644 cpu/m32r.opc create mode 100644 cpu/mep-avc.cpu create mode 100644 cpu/mep-avc2.cpu create mode 100644 cpu/mep-c5.cpu create mode 100644 cpu/mep-core.cpu create mode 100644 cpu/mep-default.cpu create mode 100644 cpu/mep-ext-cop.cpu create mode 100644 cpu/mep-fmax.cpu create mode 100644 cpu/mep-h1.cpu create mode 100644 cpu/mep-ivc2.cpu create mode 100644 cpu/mep-rhcop.cpu create mode 100644 cpu/mep-sample-ucidsp.cpu create mode 100644 cpu/mep.cpu create mode 100644 cpu/mep.opc create mode 100644 cpu/mt.cpu create mode 100644 cpu/mt.opc create mode 100644 cpu/or1k.cpu create mode 100644 cpu/or1k.opc create mode 100644 cpu/or1kcommon.cpu create mode 100644 cpu/or1korbis.cpu create mode 100644 cpu/or1korfpx.cpu create mode 100644 cpu/sh.cpu create mode 100644 cpu/sh.opc create mode 100644 cpu/sh64-compact.cpu create mode 100644 cpu/sh64-media.cpu create mode 100644 cpu/simplify.inc create mode 100644 cpu/xc16x.cpu create mode 100644 cpu/xc16x.opc create mode 100644 cpu/xstormy16.cpu create mode 100644 cpu/xstormy16.opc (limited to 'cpu') diff --git a/cpu/ChangeLog b/cpu/ChangeLog new file mode 100644 index 0000000..0594cdf --- /dev/null +++ b/cpu/ChangeLog @@ -0,0 +1,879 @@ +2014-07-20 Stefan Kristiansson + + * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions. + +2014-06-12 Alan Modra + + * or1k.opc: Whitespace fixes. + +2014-05-08 Stefan Kristiansson + + * or1korbis.cpu (h-atomic-reserve): New hardware. + (h-atomic-address): Likewise. + (insn-opcode): Add opcodes for LWA and SWA. + (atomic-reserve): New operand. + (atomic-address): Likewise. + (l-lwa, l-swa): New instructions. + (l-lbs): Fix typo in comment. + (store-insn): Clear atomic reserve on store to atomic-address. + Fix register names in fmt field. + +2014-04-22 Christian Svensson + + * openrisc.cpu: Delete. + * openrisc.opc: Delete. + * or1k.cpu: New file. + * or1k.opc: New file. + * or1kcommon.cpu: New file. + * or1korbis.cpu: New file. + * or1korfpx.cpu: New file. + +2013-12-07 Mike Frysinger + + * epiphany.opc: Remove +x file mode. + +2013-03-08 Yann Sionneau + + PR binutils/15241 + * lm32.cpu (Control and status registers): Add CFG2, PSW, + TLBVADDR, TLBPADDR and TLBBADVADDR. + +2012-11-30 Oleg Raikhman + Joern Rennecke + + * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12. + (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l. + (testset-insn): Add NO_DIS attribute to t.l. + (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l. + (move-insns): Add NO-DIS attribute to cmov.l. + (op-mmr-movts): Add NO-DIS attribute to movts.l. + (op-mmr-movfs): Add NO-DIS attribute to movfs.l. + (op-rrr): Add NO-DIS attribute to .l. + (shift-rrr): Add NO-DIS attribute to .l. + (op-shift-rri): Add NO-DIS attribute to i32.l. + (bitrl, movtl): Add NO-DIS attribute. + (op-iextrrr): Add NO-DIS attribute to .l + (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l. + (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise. + +2012-02-27 Alan Modra + + * mt.opc (print_dollarhex): Trim values to 32 bits. + +2011-12-15 Nick Clifton + + * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit + hosts. + +2011-10-26 Joern Rennecke + + * epiphany.opc (parse_branch_addr): Fix type of valuep. + Cast value before printing it as a long. + (parse_postindex): Fix type of valuep. + +2011-10-25 Joern Rennecke + + * cpu/epiphany.cpu: New file. + * cpu/epiphany.opc: New file. + +2011-08-22 Nick Clifton + + * fr30.cpu: Newly contributed file. + * fr30.opc: Likewise. + * ip2k.cpu: Likewise. + * ip2k.opc: Likewise. + * mep-avc.cpu: Likewise. + * mep-avc2.cpu: Likewise. + * mep-c5.cpu: Likewise. + * mep-core.cpu: Likewise. + * mep-default.cpu: Likewise. + * mep-ext-cop.cpu: Likewise. + * mep-fmax.cpu: Likewise. + * mep-h1.cpu: Likewise. + * mep-ivc2.cpu: Likewise. + * mep-rhcop.cpu: Likewise. + * mep-sample-ucidsp.cpu: Likewise. + * mep.cpu: Likewise. + * mep.opc: Likewise. + * openrisc.cpu: Likewise. + * openrisc.opc: Likewise. + * xstormy16.cpu: Likewise. + * xstormy16.opc: Likewise. + +2010-10-08 Pierre Muller + + * frv.opc: #undef DEBUG. + +2010-07-03 DJ Delorie + + * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it. + +2010-02-11 Doug Evans + + * m32r.cpu (HASH-PREFIX): Delete. + (duhpo, dshpo): New pmacros. + (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo. + (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX + attribute, define with dshpo. + (uimm24): Delete HASH-PREFIX attribute. + * m32r.opc (CGEN_PRINT_NORMAL): Delete. + (print_signed_with_hash_prefix): New function. + (print_unsigned_with_hash_prefix): New function. + * xc16x.cpu (dowh): New pmacro. + (upof16): Define with dowh, specify print handler. + (qbit, qlobit, qhibit): Ditto. + (upag16): Ditto. + * xc16x.opc (CGEN_PRINT_NORMAL): Delete. + (print_with_dot_prefix): New functions. + (print_with_pof_prefix, print_with_pag_prefix): New functions. + +2010-01-24 Doug Evans + + * frv.cpu (floating-point-conversion): Update call to fp conv op. + (floating-point-dual-conversion, ne-floating-point-dual-conversion, + conditional-floating-point-conversion, ne-floating-point-conversion, + float-parallel-mul-add-double-semantics): Ditto. + +2010-01-05 Doug Evans + + * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. + (f-dsp-40-u20, f-dsp-40-u24): Ditto. + +2010-01-02 Doug Evans + + * m32c.opc (parse_signed16): Fix typo. + +2009-12-11 Nick Clifton + + * frv.opc: Fix shadowed variable warnings. + * m32c.opc: Fix shadowed variable warnings. + +2009-11-14 Doug Evans + + Must use VOID expression in VOID context. + * xc16x.cpu (mov4): Fix mode of `sequence'. + (mov9, mov10): Ditto. + (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'. + (callr, callseg, calls, trap, rets, reti): Ditto. + (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'. + (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'. + (exts, exts1, extsr, extsr1, prior): Ditto. + +2009-10-23 Doug Evans + + * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h. + cgen-ops.h -> cgen/basic-ops.h. + +2009-09-25 Alan Modra + + * m32r.cpu (stb-plus): Typo fix. + +2009-09-23 Doug Evans + + * m32r.cpu (sth-plus): Fix address mode and calculation. + (stb-plus): Ditto. + (clrpsw): Fix mask calculation. + (bset, bclr, btst): Make mode in bit calculation match expression. + + * xc16x.cpu (rtl-version): Set to 0.8. + (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix, + make uppercase. Remove unnecessary name-prefix spec. + (grb-names, conditioncode-names, extconditioncode-names): Ditto. + (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto. + (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto. + (h-cr): New hardware. + (muls): Comment out parts that won't compile, add fixme. + (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto. + (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto. + (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto. + +2009-07-16 Doug Evans + + * cpu/simplify.inc (*): One line doc strings don't need \n. + (df): Invoke define-full-ifield instead of claiming it's an alias. + (dno): Define. + (dnop): Mark as deprecated. + +2009-06-22 Alan Modra + + * m32c.opc (parse_lab_5_3): Use correct enum. + +2009-01-07 Hans-Peter Nilsson + + * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI. + (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros. + (media-arith-sat-semantics): Explicitly sign- or zero-extend + arguments of "operation" to DI using "mode" and the new pmacros. + +2009-01-03 Hans-Peter Nilsson + + * cris.cpu (cris-implemented-writable-specregs-v32): Correct size + of number 2, PID. + +2008-12-23 Jon Beniston + + * lm32.cpu: New file. + * lm32.opc: New file. + +2008-01-29 Alan Modra + + * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change + to source. + +2007-10-22 Hans-Peter Nilsson + + * cris.cpu (movs, movu): Use result of extension operation when + updating flags. + +2007-07-04 Nick Clifton + + * cris.cpu: Update copyright notice to refer to GPLv3. + * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu, + m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu, + sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu, + xc16x.opc: Likewise. + * iq2000.cpu: Fix copyright notice to refer to FSF. + +2007-04-30 Mark Salter + + * frv.cpu (spr-names): Support new coprocessor SPR registers. + +2007-04-20 Nick Clifton + + * xc16x.cpu: Restore after accidentally overwriting this file with + xc16x.opc. + +2007-03-29 DJ Delorie + + * m32c.cpu (Imm-8-s4n): Fix print hook. + (Lab-24-8, Lab-32-8, Lab-40-8): Fix. + (arith-jnz-imm4-dst-defn): Make relaxable. + (arith-jnz16-imm4-dst-defn): Fix encodings. + +2007-03-20 DJ Delorie + + * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, + mem20): New. + (src16-16-20-An-relative-*): New. + (dst16-*-20-An-relative-*): New. + (dst16-16-16sa-*): New + (dst16-16-16ar-*): New + (dst32-16-16sa-Unprefixed-*): New + (jsri): Fix operands. + (setzx): Fix encoding. + +2007-03-08 Alan Modra + + * m32r.opc: Formatting. + +2006-05-22 Nick Clifton + + * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu. + +2006-04-10 DJ Delorie + + * m32c.opc (parse_unsigned_bitbase): Take a new parameter which + decides if this function accepts symbolic constants or not. + (parse_signed_bitbase): Likewise. + (parse_unsigned_bitbase8): Pass the new parameter. + (parse_unsigned_bitbase11): Likewise. + (parse_unsigned_bitbase16): Likewise. + (parse_unsigned_bitbase19): Likewise. + (parse_unsigned_bitbase27): Likewise. + (parse_signed_bitbase8): Likewise. + (parse_signed_bitbase11): Likewise. + (parse_signed_bitbase19): Likewise. + +2006-03-13 DJ Delorie + + * m32c.cpu (Bit3-S): New. + (btst:s): New. + * m32c.opc (parse_bit3_S): New. + + * m32c.cpu (decimal-subtraction16-insn): Add second operand. + (btst): Add optional :G suffix for MACH32. + (or.b:S): New. + (pop.w:G): Add optional :G suffix for MACH16. + (push.b.imm): Fix syntax. + +2006-03-10 DJ Delorie + + * m32c.cpu (mul.l): New. + (mulu.l): New. + +2006-03-03 Shrirang Khisti + + * m32c.cpu (RL_TYPE): New attribute, with macros. + (Lab-8-24): Add RELAX. + (unary-insn-defn-g, binary-arith-imm-dst-defn, + binary-arith-imm4-dst-defn): Add 1ADDR attribute. + (binary-arith-src-dst-defn): Add 2ADDR attribute. + (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, + jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP + attribute. + (jsri16, jsri32): Add 1ADDR attribute. + (jsr32.w, jsr32.a): Add JUMP attribute. + +2006-02-17 Shrirang Khisti + Anil Paranjape + Shilin Shakti + + * xc16x.cpu: New file containing complete CGEN specific XC16X CPU + description. + * xc16x.opc: New file containing supporting XC16C routines. + +2006-02-10 Nick Clifton + + * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits. + +2006-01-06 DJ Delorie + + * m32c.cpu (mov.w:q): Fix mode. + (push32.b.imm): Likewise, for the comment. + +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * mt.cpu (define-arch, define-isa): Set name to mt. + (define-mach): Adjust. + * mt.opc (CGEN_ASM_HASH): Update. + (mt_asm_hash, mt_cgen_insn_supported): Renamed. + (parse_loopsize, parse_imm16): Adjust. + +2005-12-13 DJ Delorie + + * m32c.cpu (jsri): Fix order so register names aren't treated as + symbols. + (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw, + indexwd, indexws): Fix encodings. + +2005-12-12 Nathan Sidwell + + * mt.cpu: Rename from ms1.cpu. + * mt.opc: Rename from ms1.opc. + +2005-12-06 Hans-Peter Nilsson + + * cris.cpu (simplecris-common-writable-specregs) + (simplecris-common-readable-specregs): Split from + simplecris-common-specregs. All users changed. + (cris-implemented-writable-specregs-v0) + (cris-implemented-readable-specregs-v0): Similar from + cris-implemented-specregs-v0. + (cris-implemented-writable-specregs-v3) + (cris-implemented-readable-specregs-v3) + (cris-implemented-writable-specregs-v8) + (cris-implemented-readable-specregs-v8) + (cris-implemented-writable-specregs-v10) + (cris-implemented-readable-specregs-v10) + (cris-implemented-writable-specregs-v32) + (cris-implemented-readable-specregs-v32): Similar. + (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New + insns and specializations. + +2005-11-08 Nathan Sidwell + + Add ms2 + * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and + model. + (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, + f-cb2incr, f-rc3): New fields. + (LOOP): New instruction. + (JAL-HAZARD): New hazard. + (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): + New operands. + (mul, muli, dbnz, iflush): Enable for ms2 + (jal, reti): Has JAL-HAZARD. + (ldctxt, ldfb, stfb): Only ms1. + (fbcb): Only ms1,ms1-003. + (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, + fbcbincrs, mfbcbincrs): Enable for ms2. + (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. + * ms1.opc (parse_loopsize): New. + (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. + (print_pcrel): New. + +2005-10-28 Dave Brolley + + Contribute the following change: + 2003-09-24 Dave Brolley + + * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of + CGEN_ATTR_VALUE_TYPE. + * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE. + Use cgen_bitset_intersect_p. + +2005-10-27 DJ Delorie + + * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New. + (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, + arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which + imm operand is needed. + (adjnz, sbjnz): Pass the right operands. + (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, + unary-insn): Add -g variants for opcodes that need to support :G. + (not.BW:G, push.BW:G): Call it. + (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, + stzx16-imm8-imm8-abs16): Fix operand typos. + * m32c.opc (m32c_asm_hash): Support bnCND. + (parse_signed4n, print_signed4n): New. + +2005-10-26 DJ Delorie + + * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. + (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn, + mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn): + dsp8[sp] is signed. + (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff). + (mov.BW:S r0,r1): Fix typo r1l->r1. + (tst): Allow :G suffix. + * m32c.opc (parse_signed24): New, for -0x800000..0xffffff. + +2005-10-26 Kazuhiro Inaoka + + * m32r.opc (parse_hi16): Do not assume a 32-bit host word size. + +2005-10-25 DJ Delorie + + * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by + making one a macro of the other. + +2005-10-21 DJ Delorie + + * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. + (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, + indexld, indexls): .w variants have `1' bit. + (rot32.b): QI, not SI. + (rot32.w): HI, not SI. + (xchg16): HI for .w variant. + +2005-10-19 Nick Clifton + + * m32r.opc (parse_slo16): Fix bad application of previous patch. + +2005-10-18 Andreas Schwab + + * m32r.opc (parse_slo16): Better version of previous patch. + +2005-10-14 Kazuhiro Inaoka + + * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word + size. + +2005-07-25 DJ Delorie + + * m32c.opc (parse_unsigned8): Add %dsp8(). + (parse_signed8): Add %hi8(). + (parse_unsigned16): Add %dsp16(). + (parse_signed16): Add %lo16() and %hi16(). + (parse_lab_5_3): Make valuep a bfd_vma *. + +2005-07-18 Nick Clifton + + * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode + components. + (f-lab32-jmp-s): Fix insertion sequence. + (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands. + (Dsp-40-s8): Make parameter be signed. + (Dsp-40-s16): Likewise. + (Dsp-48-s8): Likewise. + (Dsp-48-s16): Likewise. + (Imm-13-u3): Likewise. (Despite its name!) + (BitBase16-16-s8): Make the parameter be unsigned. + (BitBase16-8-u11-S): Likewise. + (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s, + jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow + relaxation. + + * m32c.opc: Fix formatting. + Use safe-ctype.h instead of ctype.h + Move duplicated code sequences into a macro. + Fix compile time warnings about signedness mismatches. + Remove dead code. + (parse_lab_5_3): New parser function. + +2005-07-16 Jim Blandy + + * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET, + to represent isa sets. + +2005-07-15 Jim Blandy + + * m32c.cpu, m32c.opc: Fix copyright. + +2005-07-14 Jim Blandy + + * m32c.cpu, m32c.opc: Machine description for the Renesas M32C. + +2005-07-14 Alan Modra + + * ms1.opc (print_dollarhex): Correct format string. + +2005-07-06 Alan Modra + + * iq2000.cpu: Include from binutils cpu dir. + +2005-07-05 Nick Clifton + + * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter + unsigned in order to avoid compile time warnings about sign + conflicts. + + * ms1.opc (parse_*): Likewise. + (parse_imm16): Use a "void *" as it is passed both signed and + unsigned arguments. + +2005-07-01 Nick Clifton + + * frv.opc: Update to ISO C90 function declaration style. + * iq2000.opc: Likewise. + * m32r.opc: Likewise. + * sh.opc: Likewise. + +2005-06-15 Dave Brolley + + Contributed by Red Hat. + * ms1.cpu: New file. Written by Nick Clifton, Stan Cox. + * ms1.opc: New file. Written by Stan Cox. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu, + m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu, + sh64-media.cpu, simplify.inc + +2005-02-24 Alan Modra + + * frv.opc (parse_A): Warning fix. + +2005-02-23 Nick Clifton + + * frv.opc: Fixed compile time warnings about differing signed'ness + of pointers passed to functions. + * m32r.opc: Likewise. + +2005-02-11 Nick Clifton + + * iq2000.opc (parse_jtargq10): Change type of valuep argument to + 'bfd_vma *' in order avoid compile time warning message. + +2005-01-28 Hans-Peter Nilsson + + * cris.cpu (mstep): Add missing insn. + +2005-01-25 Alexandre Oliva + + 2004-11-10 Alexandre Oliva + * frv.cpu: Add support for TLS annotations in loads and calll. + * frv.opc (parse_symbolic_address): New. + (parse_ldd_annotation): New. + (parse_call_annotation): New. + (parse_ld_annotation): New. + (parse_ulo16, parse_uslo16): Use parse_symbolic_address. + Introduce TLS relocations. + (parse_d12, parse_s12, parse_u12): Likewise. + (parse_uhi16): Likewise. Fix constant checking on 64-bit host. + (parse_call_label, print_at): New. + +2004-12-21 Mikael Starvik + + * cris.cpu (cris-set-mem): Correct integral write semantics. + +2004-11-29 Hans-Peter Nilsson + + * cris.cpu: New file. + +2004-11-15 Michael K. Lechner + + * iq2000.cpu: Added quotes around macro arguments so that they + will work with newer versions of guile. + +2004-10-27 Nick Clifton + + * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1, + wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index + operand. + * iq2000.cpu (dnop index): Rename to _index to avoid complications + with guile. + +2004-08-27 Richard Sandiford + + * frv.cpu (cfmovs): Change UNIT attribute to FMALL. + +2004-05-15 Nick Clifton + + * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const. + +2004-03-30 Kazuhiro Inaoka + + * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug. + +2004-03-01 Richard Sandiford + + * frv.cpu (define-arch frv): Add fr450 mach. + (define-mach fr450): New. + (define-model fr450): New. Add profile units to every fr450 insn. + (define-attr UNIT): Add MDCUTSSI. + (define-attr FR450-MAJOR): New enum. Add to every fr450 insn. + (define-attr AUDIO): New boolean. + (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL) + (f-LRA-null, f-TLBPR-null): New fields. + (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr) + (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs. + (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands. + (LRA-null, TLBPR-null): New macros. + (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr. + (load-real-address): New macro. + (lrai, lrad, tlbpr): New instructions. + (media-cut-acc, media-cut-acc-ss): Add fr450-major argument. + (mcut, mcuti, mcutss, mcutssi): Adjust accordingly. + (mdcutssi): Change UNIT attribute to MDCUTSSI. + (media-low-clear-semantics, media-scope-limit-semantics) + (media-quad-limit, media-quad-shift): New macros. + (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions. + * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major) + (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn) + (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450. + (fr450_unit_mapping): New array. + (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry + for new MDCUTSSI unit. + (fr450_check_insn_major_constraints): New function. + (check_insn_major_constraints): Use it. + +2004-03-01 Richard Sandiford + + * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. + (scutss): Change unit to I0. + (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. + (mqsaths): Fix FR400-MAJOR categorization. + (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) + (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. + * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) + combinations. + +2004-03-01 Richard Sandiford + + * frv.cpu (r-store, r-store-dual, r-store-quad): Delete. + (rstb, rsth, rst, rstd, rstq): Delete. + (rstbf, rsthf, rstf, rstdf, rstqf): Delete. + +2004-02-23 Nick Clifton + + * Apply these patches from Renesas: + + 2004-02-10 Kazuhiro Inaoka + + * cpu/m32r.opc (my_print_insn): Fixed incorrect output when + disassembling codes for 0x*2 addresses. + + 2003-12-15 Kazuhiro Inaoka + + * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction. + + 2003-12-03 Kazuhiro Inaoka + + * cpu/m32r.cpu : Add new model m32r2. + Add new instructions. + Replace occurrances of 'Mitsubishi' with 'Renesas'. + Changed PIPE attr of push from O to OS. + Care for Little-endian of M32R. + * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn): + Care for Little-endian of M32R. + (parse_slo16): signed extension for value. + +2004-02-20 Andrew Cagney + + * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick + Clifton, Ben Elliston, Matthew Green, and Andrew Haley. + + * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all + written by Ben Elliston. + +2004-01-14 Richard Sandiford + + * frv.cpu (UNIT): Add IACC. + (iacc-multiply-r-r): Use it. + * frv.opc (fr400_unit_mapping): Add entry for IACC. + (fr500_unit_mapping, fr550_unit_mapping): Likewise. + +2004-01-06 Alexandre Oliva + + 2003-12-19 Alexandre Oliva + * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some + cut&paste errors in shifting/truncating numerical operands. + 2003-08-08 Alexandre Oliva + * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. + (parse_d12): Parse gotoff12 and gotofffuncdesc12. + (parse_s12): Likewise. + 2003-08-04 Alexandre Oliva + * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gothi and gotfuncdeschi. + (parse_d12): Parse got12 and gotfuncdesc12. + (parse_s12): Likewise. + +2003-10-10 Dave Brolley + + * frv.cpu (dnpmop): New p-macro. + (GRdoublek): Use dnpmop. + (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto. + (store-double-r-r): Use (.sym regtype doublek). + (r-store-double): Ditto. + (store-double-r-r-u): Ditto. + (conditional-store-double): Ditto. + (conditional-store-double-u): Ditto. + (store-double-r-simm): Ditto. + (fmovs): Assign to UNIT FMALL. + +2003-10-06 Dave Brolley + + * frv.cpu, frv.opc: Add support for fr550. + +2003-09-24 Dave Brolley + + * frv.cpu (u-commit): New modelling unit for fr500. + (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand. + (commit-r): Use u-commit model for fr500. + (commit): Ditto. + (conditional-float-binary-op): Take profiling data as an argument. + Update callers. + (ne-float-binary-op): Ditto. + +2003-09-19 Michael Snyder + + * frv.cpu (nldqi): Delete unimplemented instruction. + +2003-09-12 Dave Brolley + + * frv.cpu (u-clrgr, u-clrfr): New units of model fr500. + (clear-ne-flag-r): Pass insn profiling in as an argument. Call + frv_ref_SI to get input register referenced for profiling. + (clear-ne-flag-all): Pass insn profiling in as an argument. + (clrgr,clrfr,clrga,clrfa): Add profiling information. + +2003-09-11 Michael Snyder + + * frv.cpu: Typographical corrections. + +2003-09-09 Dave Brolley + + * frv.cpu (media-dual-complex): Change UNIT to FMALL. + (conditional-media-dual-complex, media-quad-complex): Likewise. + +2003-09-04 Dave Brolley + + * frv.cpu (register-transfer): Pass in all attributes in on argument. + Update all callers. + (conditional-register-transfer): Ditto. + (cache-preload): Ditto. + (floating-point-conversion): Ditto. + (floating-point-neg): Ditto. + (float-abs): Ditto. + (float-binary-op-s): Ditto. + (conditional-float-binary-op): Ditto. + (ne-float-binary-op): Ditto. + (float-dual-arith): Ditto. + (ne-float-dual-arith): Ditto. + +2003-09-03 Dave Brolley + + * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers. + * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC, + MCLRACC-1. + (A): Removed operand. + (A0,A1): New operands replace operand A. + (mnop): Now a real insn + (mclracc): Removed insn. + (mclracc-0, mclracc-1): New insns replace mclracc. + (all insns): Use new UNIT attributes. + +2003-08-21 Nick Clifton + + * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand + and u-media-dual-btoh with output parameter. + (cmbtoh): Add profiling hack. + +2003-08-19 Michael Snyder + + * frv.cpu: Fix typo, Frintkeven -> FRintkeven + +2003-06-10 Doug Evans + + * frv.cpu: Add IDOC attribute. + +2003-06-06 Andrew Cagney + + Contributed by Red Hat. + * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston, + Stan Cox, and Frank Ch. Eigler. + * iq2000.opc: New file. Written by Ben Elliston, Frank + Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox. + * iq2000m.cpu: New file. Written by Jeff Johnston. + * iq10.cpu: New file. Written by Jeff Johnston. + +2003-06-05 Nick Clifton + + * frv.cpu (FRintieven): New operand. An even-numbered only + version of the FRinti operand. + (FRintjeven): Likewise for FRintj. + (FRintkeven): Likewise for FRintk. + (mdcutssi, media-dual-word-rotate-r-r, mqsaths, + media-quad-arith-sat-semantics, media-quad-arith-sat, + conditional-media-quad-arith-sat, mdunpackh, + media-quad-multiply-semantics, media-quad-multiply, + conditional-media-quad-multiply, media-quad-complex-i, + media-quad-multiply-acc-semantics, media-quad-multiply-acc, + conditional-media-quad-multiply-acc, munpackh, + media-quad-multiply-cross-acc-semantics, mdpackh, + media-quad-multiply-cross-acc, mbtoh-semantics, + media-quad-cross-multiply-cross-acc-semantics, + media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics, + media-quad-cross-multiply-acc-semantics, cmbtoh, + media-quad-cross-multiply-acc, media-quad-complex, mhtob, + media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd, + cmhtob): Use new operands. + * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define. + (parse_even_register): New function. + +2003-06-03 Nick Clifton + + * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit + immediate value not unsigned. + +2003-06-03 Andrew Cagney + + Contributed by Red Hat. + * frv.cpu: New file. Written by Dave Brolley, Catherine Moore, + and Eric Christopher. + * frv.opc: New file. Written by Catherine Moore, and Dave + Brolley. + * simplify.inc: New file. Written by Doug Evans. + +2003-05-02 Andrew Cagney + + * New file. + + +Copyright (C) 2003-2012 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/cpu/cris.cpu b/cpu/cris.cpu new file mode 100644 index 0000000..97b4458 --- /dev/null +++ b/cpu/cris.cpu @@ -0,0 +1,4553 @@ +; CRIS CPU description. -*- Scheme -*- +; +; Copyright 2003, 2004, 2007, 2009 Free Software Foundation, Inc. +; +; Contributed by Axis Communications AB. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +; MA 02110-1301, USA. + +(include "simplify.inc") + +;;;;;;;;;;;;;;;;;; -pmacro (generic ones) + +(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l)) +(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l)) +(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x) +(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x)) +(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x)) +(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x) +(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x)) +(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x)) +(define-pmacro + (define-pmacro-map x) + "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)" + (.splice + begin + (.unsplice + (.map + (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x))) +) + +;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model + +(define-arch + (name cris) + (comment "Axis Communications CRIS") + (default-alignment unaligned) + (insn-lsb0? #t) + (machs crisv0 crisv3 crisv8 crisv10 crisv32) + (isas cris) +) + +(define-isa + (name cris) + (base-insn-bitsize 16) + (liw-insns 1) + (parallel-insns 1) +) + +(define-pmacro + (define-cpu-cris x-suffix x-comment) + "Define a CRIS CPU family" + (define-cpu + (name (.sym cris x-suffix f)) + (comment x-comment) + (endian little) + ; CGEN-FIXME: Should be deduced from the default? + (word-bitsize 32) + (file-transform (.str x-suffix)) + ) +) + +; Useful when there's a need to iterate over all models. +(define-pmacro (cris-cpu-model-numbers) + "List of CRIS CPU model numbers (version register contents)" + (0 3 8 10 32) +) + +(define-pmacro (cris-cpu-models) + "List of CRIS CPU model names" + (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers)) +) + +; Mapping from model name to number. +(define-pmacro-map + (.map (.pmacro (n) ((.sym v n -number) n)) + (cris-cpu-model-numbers))) + +; FIXME: Rationalize these rules. +; CPU names must be distinct from the architecture name and machine names. +; The "b" suffix stands for "base" and is the convention. +; The "f" suffix stands for "family" and is the convention. +; We ignore the "b" convention, partly because v0 isn't really a "base", at +; least not for some aspects of v32. +(define-cpu-cris v0 "CRIS base family") +(define-cpu-cris v3 "CRIS v3 family") +(define-cpu-cris v8 "CRIS v8 family") +(define-cpu-cris v10 "CRIS v10 family") +(define-cpu-cris v32 "CRIS v32 family") + +(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10)) +(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32)) +(define-pmacro MACH-V32 (MACH crisv32)) +(define-pmacro MACH-PC MACH-PRE-V32) +(define-pmacro MACH-ACR MACH-V32) +(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32) +(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32) + +(define-pmacro + current-mach-is-v32 + "Whether the generated code is for V32. See comment at h-v32." + (reg h-v32) +) + +(define-pmacro (define-mach-cris x-suffix x-comment x-name) + "Define a CRIS mach" + (define-mach + (name (.sym cris x-suffix)) + ; They're all called "cris" in bfd. Watch out for breakages for some + ; uses. + (bfd-name x-name) + (comment x-comment) + (cpu (.sym cris x-suffix f))) +) + +(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris") +(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris") +(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris") +(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris") +(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32") + +(define-pmacro (define-model-simplecris x-name x-comment) + "Define a simple CRIS model" + (define-model + (name (.sym cris x-name)) + (comment x-comment) + (mach (.sym cris x-name)) + + (unit u-exec "Execution Unit" () 1 1 () () () ()) + (unit u-mem "Memory Unit" () 1 1 () () () ()) + + (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) + (unit u-const32 "Fetch 32-bit operand" () 1 1 + () () () ()) + ; Used in special-case insn, for example arithmetic with PC destination. + (unit u-stall "Stall unit" () 1 1 () () () ()) + (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) + (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ()) + (unit u-movem "Movem Unit" () 1 1 () + ((Rd INT -1)) + () ())) +) + +(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3") +(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4") +(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100") +(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX") + +; For some reason, we get an error: +; Generating arch.h ... +; ERROR: In procedure vector-ref: +; ERROR: Wrong type argument in position 1: () +; if we include timings for machs that we don't generate sims for. +; Last checked: CVS as of 2004-11-18. +; CGEN-FIXME: Looks like another CGEN bug. When it's fixed (or when +; generating sims for v0, v3 or v8), add 0, 3 and 8 to +; simplecris-timing-models. But before that, simplecris-timing-x has to +; be rewritten to work on a multiple-element-list, not assume a single +; element. (A change which seems likely to depend on lexical scoping for +; macros to be introduced: try the obvious implementation.) +(define-pmacro simplecris-timing-models (10)) +(define-pmacro (simplecris-common-timing x-units) + "Make timing models, using x-units for all simplecris-timing-models" + ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain + ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as + ; ((.splice (.sym crisv (.unsplice simplecris-timing-models)) + ; (.unsplice x-units))) + ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models)) + (.unsplice x-units))) +) + +(define-pmacro-map + ( + ; Timing for memory instructions running on a simple cris model. + ((simplecris-mem-timing) (simplecris-common-timing + ((unit u-mem) (unit u-exec)))) + ; Timing for movem instructions running on a simple cris model. + ((simplecris-movem-timing) (simplecris-common-timing + ((unit u-movem) (unit u-exec)))) + ; Similar, for an 8- or 16-bit constant ([PC+]) operand. + ((simplecris-const-timing-HI) + (simplecris-common-timing + ((unit u-const16) (unit u-exec)))) + ; Similar, for a 32-bit constant ([PC+]) operand. + ((simplecris-const-timing-SI) + (simplecris-common-timing + ((unit u-const32) (unit u-exec)))) + ; Similar, no particular operand. + ((simplecris-timing) (simplecris-common-timing + ((unit u-exec))))) +) + +(define-model + (name crisv32) + (comment "Model of CRISv32") + (mach crisv32) + + (state + ; Bitmask of h-gr register (0..15) and h-sr register (17..31) + ; modified by 3rd previous insn, updated by the u-exec unit. + ; Because there's no need to mark writes to special registers BZ and + ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark. + (prev-prev-prev-modf-regs UINT) + + ; Ditto for the 2nd previous insn. + (prev-prev-modf-regs UINT) + + ; Ditto for the previous insn. + (prev-modf-regs UINT) + + ; Bit-mask for regs modified by the current insn, propagated to + ; prev-modf-regs. + (modf-regs UINT) + + ; Registers loaded by movem are not forwarded to the execution + ; stage, so we need to insert stall-cycles for ordinary insns + ; accessing such registers. In addition to the *modf-regs + ; above, these are set to tell *ordinary* insns which registers + ; are inaccessible. + + (prev-prev-prev-movem-dest-regs UINT) + + ; Ditto for the 2nd previous insn. + (prev-prev-movem-dest-regs UINT) + + ; Ditto for the previous insn. + (prev-movem-dest-regs UINT) + + ; Bit-mask for regs modified by the current insn, propagated to + ; prev-movem-dest-regs. + (movem-dest-regs UINT)) + + ; It seems this pipeline description isn't used at all; this is just + ; for show. + ; Noteworthy is the placement of the memory stage before the execute stage. + (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback))) + + ; Units that contribute only a constant pipeline delay are not included. + (unit u-mem "Memory Unit" () 1 1 () + ((Rs INT -1)) + () ()) + + ; Artificial units for read/write-related hazard accounting. + (unit u-mem-r "Memory Unit Read" () 1 1 () () () ()) + (unit u-mem-w "Memory Unit Write" () 1 1 () () () ()) + + (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 () + ((Rs INT -1) (Rd INT -1)) + () ()) + (unit u-movem-mtor "Movem-to-register Unit" () 1 1 () + ((Rs INT -1) (Rd INT -1)) + () ()) + (unit u-multiply "Multiply Unit" () 1 1 () + ((Rs INT -1) (Rd INT -1)) + () ()) + (unit u-branch "Branch Unit" () 1 1 () + () + () ()) + (unit u-jump-r "Jump-to-register Unit" () 1 1 () + ((Rs INT -1)) + () ()) + (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 () + ((Ps INT -1)) + () ()) + (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 () + () + ((Pd INT -1)) ()) + + ; To keep track of PC; not really functional units. + (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) + (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ()) + (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) + + ; For v32, we need to keep track of inputs (for movem destination + ; cycle penalties) and output (for e.g. memory source and jump + ; source cycle penalties). + (unit u-exec "Execution Unit" () 1 1 () + ((Rd INT -1) (Rs INT -1)) + ((Rd INT -1)) + ()) + + ; Special case of u-exec for movem: don't treat Rd as an incoming + ; parameter. + (unit u-exec-movem "Execution Unit" () 1 1 () + ((Rs INT -1)) + ((Rd INT -1)) + ()) + + ; Special case of u-exec when the destination is a special + ; register. + (unit u-exec-to-sr "Execution Unit" () 1 1 () + ((Rs INT -1)) + ((Pd INT -1)) ()) +) + +(define-pmacro (crisv32-timing-destreg d) + "Timing for instructions running on a crisv32 model" + ((crisv32 + (.splice unit u-exec (.unsplice d)))) +) +(define-pmacro (crisv32-timing) (crisv32-timing-destreg ())) + +(define-pmacro (cris-timing-Rd-sfield) + (crisv32-timing-destreg ((out Rd Rd-sfield))) +) + +(define-pmacro (crisv32-timing-c-HI) + ((crisv32 (unit u-const16) (unit u-exec))) +) + +(define-pmacro-map + ((crisv32-timing-c-QI crisv32-timing-c-HI) + ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec)))) + ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr)))) + ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr)))) + ((crisv32-mem-sr-timing) + ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr)))) + ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec)))) + ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w))))) +) + +(define-pmacro-map + ( + ; Timing for instructions using memory operands. + ((cris-mem-timing) (.splice (.unsplice (simplecris-mem-timing)) + (.unsplice (crisv32-mem-timing)))) + ; Timing for instructions using memory operands. + ((cris-mem-write-timing) (.splice + (.unsplice (simplecris-mem-timing)) + (.unsplice (crisv32-mem-write-timing)))) + ; Timing for moves from general register to special register. + ((cris-reg-sr-timing) (.splice (.unsplice (simplecris-timing)) + (.unsplice (crisv32-reg-sr-timing)))) + ; Timing for moves from memory to special register. + ((cris-mem-sr-timing) (.splice (.unsplice (simplecris-mem-timing)) + (.unsplice (crisv32-mem-sr-timing)))) + ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions. + ((cris-timing) (.splice (.unsplice (simplecris-timing)) + (.unsplice (crisv32-timing)))) + ; Timing for instructions with 8- or 16-bit constant operand ([PC+]). + ((cris-timing-const-HI) (.splice + (.unsplice (simplecris-const-timing-HI)) + (.unsplice (crisv32-timing-c-HI)))) + ; Timing for instructions with a 32-bit constant operand ([PC+]). + ((cris-timing-const-SI) (.splice + (.unsplice (simplecris-const-timing-SI)) + (.unsplice (crisv32-timing-c-SI)))) + ; Like cris-timing-const-SI, but destination special register. + ((cris-timing-const-sr-SI) (.splice + (.unsplice (simplecris-const-timing-SI)) + (.unsplice (crisv32-timing-c-sr-SI)))) + ; Like cris-timing-const-HI, but destination special register. + ((cris-timing-const-sr-HI) (.splice + (.unsplice (simplecris-const-timing-HI)) + (.unsplice (crisv32-timing-c-sr-SI))))) +) + +(define-pmacro cris-timing-const-QI cris-timing-const-HI) +(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI) + +(define-pmacro (simplecris-common-writable-specregs) + "The common writable special registers in pre-v32 models." + ((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13)) +) + +(define-pmacro (simplecris-common-readable-specregs) + "The common readable special registers in pre-v32 models." + (.splice (.unsplice (simplecris-common-writable-specregs)) + (QI 0) (QI 1) (HI 4) (SI 8)) +) + +(define-pmacro (cris-implemented-writable-specregs-v0) + "Special writable registers in v0 and their sizes" + (.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7)) +) +(define-pmacro + cris-implemented-specregs-const-v0 + cris-implemented-writable-specregs-v0 +) +(define-pmacro (cris-implemented-readable-specregs-v0) + "Special readable registers in v0 and their sizes" + (.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7)) +) + +(define-pmacro (cris-implemented-writable-specregs-v3) + "Special writable registers in v3 and their sizes" + (.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14)) +) +(define-pmacro + cris-implemented-specregs-const-v3 + cris-implemented-writable-specregs-v3 +) +(define-pmacro (cris-implemented-readable-specregs-v3) + "Special readable registers in v3 and their sizes" + (.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14)) +) + +(define-pmacro (cris-implemented-writable-specregs-v8) + "Special writable registers in v8 and their sizes" + (.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14)) +) +(define-pmacro + cris-implemented-specregs-const-v8 + cris-implemented-writable-specregs-v8 +) +(define-pmacro (cris-implemented-readable-specregs-v8) + "Special readable registers in v8 and their sizes" + (.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14)) +) + +(define-pmacro (cris-implemented-writable-specregs-v10) + "Special writable registers in v10 and their sizes" + (.splice (.unsplice (simplecris-common-writable-specregs)) + (SI 7) (SI 14) (SI 15)) +) +(define-pmacro + cris-implemented-specregs-const-v10 + cris-implemented-writable-specregs-v10 +) +(define-pmacro (cris-implemented-readable-specregs-v10) + "Special registers in v10 and their sizes" + (.splice (.unsplice (simplecris-common-readable-specregs)) + (SI 7) (SI 14) (SI 15)) +) + +(define-pmacro (cris-implemented-writable-specregs-v32) + "Special writable registers in v32 and their sizes" + ((SI 2) (QI 3) + (SI 5) (SI 6) (SI 7) (SI 9) + (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15)) +) +(define-pmacro (cris-implemented-readable-specregs-v32) + "Special readable registers in v32 and their sizes" + (.splice (.unsplice (cris-implemented-writable-specregs-v32)) + (QI 0) (QI 1) (HI 4) (SI 8)) +) + +; For v32, all special register operations on constants (that is, +; move) take 32-bit operands, not the real size of the register, as in +; other move operations. +(define-pmacro (cris-implemented-specregs-const-v32) + (.map (.pmacro (x) (SI (.cadr2 x))) + (cris-implemented-writable-specregs-v32)) +) + +(define-pmacro cris-swap-codes + "CRIS Swap codes in numeric order (no zero)" + ( r b br w wr wb wbr + n nr nb nbr nw nwr nwb nwbr) +) + +(define-pmacro cris-flagnames + "CRIS flag field values, dest and src fields concatenated" + (c v z n x i u p) ; ... b m for pre-v32 +) + +(define-pmacro-map + ; Bitnumber for each respective flag. + (.map (.pmacro (x num) ((.sym x -bitnumber) num)) + cris-flagnames (.iota 8)) +) + +; I give up. Here's a perl-script to get the values I want for this macro +; (not working along list principles, though). You can run this region. +; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = ""; +; for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) { +; $s .= substr ($x, $j, 1);}} +; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n " : " "); }' +(define-pmacro cris-flag-combinations + "Combinations of flags in numeric order" + (_ c v cv z cz vz cvz + n cn vn cvn zn czn vzn cvzn + x cx vx cvx zx czx vzx cvzx + nx cnx vnx cvnx znx cznx vznx cvznx + i ci vi cvi zi czi vzi cvzi + ni cni vni cvni zni czni vzni cvzni + xi cxi vxi cvxi zxi czxi vzxi cvzxi + nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi + u cu vu cvu zu czu vzu cvzu + nu cnu vnu cvnu znu cznu vznu cvznu + xu cxu vxu cvxu zxu czxu vzxu cvzxu + nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu + iu ciu viu cviu ziu cziu vziu cvziu + niu cniu vniu cvniu zniu czniu vzniu cvzniu + xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu + nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu + p cp vp cvp zp czp vzp cvzp + np cnp vnp cvnp znp cznp vznp cvznp + xp cxp vxp cvxp zxp czxp vzxp cvzxp + nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp + ip cip vip cvip zip czip vzip cvzip + nip cnip vnip cvnip znip cznip vznip cvznip + xip cxip vxip cvxip zxip czxip vzxip cvzxip + nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip + up cup vup cvup zup czup vzup cvzup + nup cnup vnup cvnup znup cznup vznup cvznup + xup cxup vxup cvxup zxup czxup vzxup cvzxup + nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup + iup ciup viup cviup ziup cziup vziup cvziup + niup cniup vniup cvniup zniup czniup vzniup cvzniup + xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup + nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup + ) +) + +(define-pmacro cc-condition (not cbit)) +(define-pmacro cs-condition cbit) +(define-pmacro ne-condition (not zbit)) +(define-pmacro eq-condition zbit) +(define-pmacro vc-condition (not vbit)) +(define-pmacro vs-condition vbit) +(define-pmacro pl-condition (not nbit)) +(define-pmacro mi-condition nbit) +(define-pmacro ls-condition (or cbit zbit)) +(define-pmacro hi-condition (not (or cbit zbit))) +(define-pmacro ge-condition (not (xor vbit nbit))) +(define-pmacro lt-condition (xor vbit nbit)) +(define-pmacro gt-condition (not (or (xor vbit nbit) zbit))) +(define-pmacro le-condition (or (xor vbit nbit) zbit)) +(define-pmacro a-condition 1) + +; FIXME: define this properly for v10 and pre-v10. +(define-pmacro wf-condition pbit) + +(define-pmacro (cris-condition condno) + "Return condition state for condition number CONDNO" + (sequence + BI + ((SI tmpcond) (BI condres)) + (set tmpcond condno) + (.splice + cond + (.unsplice + (.map + (.pmacro + (condn condc) + ((eq tmpcond condn) (set condres (.sym condc -condition)))) + (.iota 16) + cris-condition-codes))) + condres) +) + +;;;;;;;;;;;;;;;;;; -keyword + +; General registers. +(define-pmacro (cris-general-gregs) + (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15)))) +) + +; Can't keep more than one gr-names definition at the same time; +; generated enum declarations in sim/cris/cris-desc.h will collide. +; FIXME: (include "different-mach-parts") + +(define-keyword + (name gr-names-pcreg) + (attrs MACH-PC) + (print-name h-gr-real-pc) + ; Put PC first so it is preferred over r15. + (.splice values (PC 15) (.unsplice (cris-general-gregs))) +) + +(define-keyword + (name gr-names-acr) + (attrs MACH-ACR) + ; The print-name directive will control the enum prefix. With the + ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like + ; H_GR_ACR_R0 instead of H_GR_R0. Since we have to choose something for + ; unprefixed names, we use the CRISv32 names. FIXME: All users should + ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32. + (print-name h-gr) + ; Put ACR first so it is preferred over r15. + (.splice values (ACR 15) (.unsplice (cris-general-gregs))) +) + +(define-keyword + (name gr-names-v32) + (attrs MACH-V32) + ; In preparation for implementing the FIXME above. + (print-name h-gr-v32) + ; Put ACR first so it is preferred over r15. + (.splice values (ACR 15) (.unsplice (cris-general-gregs))) +) + +; Special registers with names common to all. +(define-pmacro (cris-general-pregs) + (.splice + (VR 1) + (SRP 11) + (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15)))) +) + +(define-keyword + (name p-names-v10) + (attrs MACH-PRE-V32) + (print-name h-sr-pre-v32) + (.splice + values + (CCR 5) + (MOF 7) + (IBR 9) + (IRP 10) + (BAR 12) + (DCCR 13) + (BRP 14) + (USP 15) + (.unsplice (cris-general-pregs))) +) + +(define-keyword + (name p-names-v32) + (attrs MACH-V32) + ; See comment for gr-names-acr. + (print-name h-sr) + (.splice + values + (BZ 0) + (PID 2) + (SRS 3) + (WZ 4) + (EXS 5) + (EDA 6) + (MOF 7) + (DZ 8) + (EBP 9) + (ERP 10) + (NRP 12) + (CCS 13) + (USP 14) + (SPC 15) + (.unsplice (cris-general-pregs))) +) + +; Similarly as for h-gr-v32, in preparation. +(define-keyword + (name p-names-v32-x) + (attrs MACH-V32) + ; See comment for gr-names-acr. + (print-name h-sr-v32) + (.splice + values + (BZ 0) + (PID 2) + (SRS 3) + (WZ 4) + (EXS 5) + (EDA 6) + (MOF 7) + (DZ 8) + (EBP 9) + (ERP 10) + (NRP 12) + (CCS 13) + (USP 14) + (SPC 15) + (.unsplice (cris-general-pregs))) +) + +(define-pmacro p0 (reg h-sr 0)) +(define-pmacro vr (reg h-sr 1)) +(define-pmacro pid (reg h-sr 2)) +(define-pmacro srs (reg h-sr 3)) +(define-pmacro p4 (reg h-sr 4)) +(define-pmacro ccr (reg h-sr 5)) +(define-pmacro mof (reg h-sr 7)) +(define-pmacro p8 (reg h-sr 8)) +(define-pmacro ibr (reg h-sr 9)) +(define-pmacro ebp (reg h-sr 9)) +(define-pmacro erp (reg h-sr 10)) +(define-pmacro srp (reg h-sr 11)) +(define-pmacro ccs (reg h-sr 13)) +(define-pmacro dccr (reg h-sr 13)) +(define-pmacro usp (reg h-sr 14)) +(define-pmacro spc (reg h-sr 15)) + +(define-pmacro sp (reg h-gr 14)) +(define-pmacro acr (reg h-gr 15)) + +(define-pmacro cris-condition-codes + "CRIS condition codes in numeric order" + (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf) +) + +; No use having different lists; this is the only CC that +; differs between v10 and v32, and mostly in the name. +(define-pmacro sb wf) + + +;;;;;;;;;;;;;;;;;; -hardware + +;; Various constant generators. + +(define-hardware + (name h-inc) + (comment "autoincrement-bit syntax specifier") + (type immediate (UINT 1)) + (values keyword "" (("" 0) ("+" 1))) +) + +(define-hardware + (name h-ccode) + (comment "Condition code specifier") + (type immediate (UINT 4)) + (values keyword "" + (.map (.pmacro (x y) ((.str x) y)) + cris-condition-codes (.iota 16))) +) + +(define-hardware + (name h-swap) + (comment "Swap option specifier") + (type immediate (UINT 4)) + (values + keyword "" + (.splice + (" " 0) + (.unsplice + (.map + (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1))))) +) + +(define-hardware + (name h-flagbits) + (comment "Flag bits specifier") + (type immediate (UINT 8)) + (values + keyword "" + (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256))) +) + +; Apparently, the semantic-name isn't used for accessors, so external +; users like the sim glue and SID sees the -v32 and -pre-v32 munged names. +; Defining "dispatchers"; virtual registers whose getter and setter works +; on the "real" mach variants, seems to help. CGEN-FIXME: Make +; semantic-name set the generated names. +(define-pmacro (cris-d-hwreg x-name x-type) + (define-hardware + (name x-name) + (comment (.str "Dispatcher for " x-name)) + (attrs VIRTUAL) + (type register x-type) + (get () (reg (.sym x-name -x))) + (set (val) (set (reg (.sym x-name -x)) val))) +) +(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs) + (define-hardware + (name x-name) + (comment (.str "Dispatcher for " x-name)) + (.splice attrs VIRTUAL (.unsplice x-attrs)) + (type register x-type (x-n)) + (get (index) (reg (.sym x-name -x) index)) + (set (index val) (set-quiet (reg (.sym x-name -x) index) val))) +) +(define-pmacro (cris-d-hwregf x-name x-type x-n) + (cris-d-hwregf-a x-name x-type x-n ()) +) +(define-pmacro (cris-d-hwregf-p x-name x-type x-n) + (cris-d-hwregf-a x-name x-type x-n (PROFILE)) +) + +; At first glance we could use (eq-attr (current-mach) ...) for +; everything, but that seems sometimes (always?) to yield false. For +; ifields, it causes noncompilable C-code. For the insn semantics code, +; it causes tests movei.ms and mulv32.ms to fail, apparently because the +; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or +; rather, misgenerated). Instead we use different definitions of a +; MACH-tagged virtual register yielding a constant, together with a +; pmacro. CGEN-FIXME: If eq-attr is someday fixed, we could just remove +; these h-v32 virtual register definitions and change the pmacro +; definition for current-mach-is-v32. +(define-hardware + (semantic-name h-v32) + (name h-v32-v32) + (attrs MACH-V32 VIRTUAL) + (type register BI) + (get () (const BI 1)) + (set (val) (error "Can't set h-v32")) +) +(define-hardware + (semantic-name h-v32) + (name h-v32-non-v32) + (attrs MACH-PRE-V32 VIRTUAL) + (type register BI) + (get () (const BI 0)) + (set (val) (error "Can't set h-v32")) +) + +;; "Real" hardware. + +(define-hardware + (name h-pc) + (comment "program counter") + (attrs PC PROFILE) + (type pc) + ; There's no bit 0 in PC, so just ignore it when jumping etc. + (set (val) (set (raw-reg h-pc) (and val (inv 1)))) +) + +; Note that setting register 15 isn't handled here, but in each insn, so +; the proper "jump" attributes and other special stuff for speedy +; execution can be present. +(cris-d-hwregf-p h-gr SI 16) +(define-hardware + (semantic-name h-gr-x) + (name h-gr-pc) + (attrs MACH-PC VIRTUAL) + (comment "General purpose registers, aborting on PC access") + (type register SI (16)) + (indices extern-keyword gr-names-pcreg) + (get + (index) + (if SI (eq index 15) + (error SI "General register read of PC is not implemented.") + (reg SI h-gr-real-pc index))) + (set + (index val) + (sequence + () + (if (eq index 15) + (error "General register write to PC is not implemented.")) + (set (reg SI h-gr-real-pc index) val))) +) +(define-hardware + (name h-gr-real-pc) + (attrs MACH-PC) + (comment "General purpose registers") + (type register SI (16)) + (indices extern-keyword gr-names-pcreg) +) + +; We have to use a virtual register trick to get the "raw", unaccounted +; contents of the global register; the raw-reg RTX only works for +; non-virtual register files. +(define-hardware + (semantic-name h-raw-gr) + (name h-raw-gr-pc) + (attrs MACH-PC VIRTUAL) + (comment "Unaccounted version of general purpose registers") + (type register SI (16)) + (get (index) (raw-reg h-gr-real-pc index)) + (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val)) +) +(define-hardware + (semantic-name h-gr-x) + (name h-gr-acr) + (attrs MACH-ACR) + (comment "General purpose registers") + (type register SI (16)) + (indices extern-keyword gr-names-acr) +) +(define-hardware + (semantic-name h-raw-gr) + (name h-raw-gr-acr) + (attrs MACH-ACR VIRTUAL) + (comment "Unaccounted version of general purpose registers") + (type register SI (16)) + (get (index) (raw-reg h-gr-x index)) + (set (index val) (set-quiet (raw-reg h-gr-x index) val)) +) + +; FIXME: get and set semantics? Unknown how to split semantics best; with +; get/set semantics or within the insn specification. Doing the former for +; now. Should use different names for pre-v10. +; FIXME: No dccr for v0 and v3. Different high flag bits. +(cris-d-hwregf-p h-sr SI 16) +(define-pmacro + (cris-h-sr machver) + (define-hardware + (semantic-name h-sr-x) + (name (.sym h-sr-v machver)) + (attrs (MACH (.sym crisv machver))) + (comment (.str "Special registers for v" machver)) + (type register SI (16)) + (indices extern-keyword p-names-v10) + (get + (index) + (cond + SI + ((orif (orif (eq index (regno p0)) (eq index (regno p4))) + (eq index (regno p8))) 0) + ((eq index (regno vr)) machver) + ((orif (eq index (regno ccr)) + (eq index (regno dccr))) + ; Return "P U I X N Z V C" for the low 8 bits. + ; FIXME: More bits. + (or SI + (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00) + (or + (zext SI (reg BI h-cbit)) + (or + (sll (zext SI (reg BI h-vbit)) 1) + (or + (sll (zext SI (reg BI h-zbit)) 2) + (or + (sll (zext SI (reg BI h-nbit)) 3) + (or + (sll (zext SI (reg BI h-xbit)) 4) + (or + (sll (zext SI (reg BI h-ibit)) 5) + (or + (sll (zext SI (reg BI h-ubit)) 6) + (or + (sll (zext SI (reg BI h-pbit)) 7) + 0)))))))))) + (else (raw-reg SI h-sr-x index)))) + (set + (index val) + (cond + ((orif (orif (eq index (regno p0)) (eq index (regno p4))) + (orif (eq index (regno p8)) (eq index (regno vr)))) + (nop)) + ((orif (eq index (regno ccr)) (eq index (regno dccr))) + (sequence + () + (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) + (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) + (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) + (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) + (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) + (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) + (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) + (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) + (set-quiet (raw-reg SI h-sr-x (regno ccr)) val) + (set-quiet (raw-reg SI h-sr-x (regno dccr)) val))) + (else (set-quiet (raw-reg SI h-sr-x index) val))))) +) + +(cris-h-sr 0) +(cris-h-sr 3) +(cris-h-sr 8) +(cris-h-sr 10) + +(define-hardware + (semantic-name h-sr-x) + (name h-sr-v32) + (attrs MACH-V32) + (comment "Special registers for v32") + (type register SI (16)) + (indices extern-keyword p-names-v32) + + (get + (index) + (cond + SI + ((orif (orif (eq index (regno p0)) (eq index (regno p4))) + (eq index (regno p8))) 0) + ((eq index (regno vr)) 32) + ((eq index (regno ccs)) + ; Return "S R P U I X N Z V C" for the low 10 bits. + (or SI + (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00) + (or + (zext SI (reg BI h-cbit)) + (or + (sll (zext SI (reg BI h-vbit)) 1) + (or + (sll (zext SI (reg BI h-zbit)) 2) + (or + (sll (zext SI (reg BI h-nbit)) 3) + (or + (sll (zext SI (reg BI h-xbit)) 4) + (or + (sll (zext SI (reg BI h-ibit)) 5) + (or + (sll (zext SI (reg BI h-ubit)) 6) + (or + (sll (zext SI (reg BI h-pbit)) 7) + (or + (sll (zext SI (reg BI h-rbit)) 8) + (or + (sll (zext SI (reg BI h-sbit)) 9) + (or + (sll (zext SI (reg BI h-mbit)) 30) + (or + (sll (zext SI (reg BI h-qbit)) 31) + 0)))))))))))))) + ((eq index (regno usp)) + ; In user mode, return general stack pointer. + (if BI (reg BI h-ubit) + (raw-reg SI h-gr-x (regno sp)) + (raw-reg SI h-sr-x (regno usp)))) + (else (raw-reg SI h-sr-x index)))) + + (set + (index val) + (cond + ((orif (orif (eq index (regno p0)) (eq index (regno p4))) + (orif (eq index (regno p8)) (eq index (regno vr)))) + (nop)) + ((eq index (regno ccs)) + (sequence + () + ; Protected bits are handled as such in the respective setter function. + (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) + (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) + (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) + (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) + (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) + (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) + (set (reg BI h-sbit) (if BI (ne SI (and val (sll 1 9)) 0) 1 0)) + (set (reg BI h-mbit) (if BI (ne SI (and val (sll 1 30)) 0) 1 0)) + (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) + (set (reg BI h-rbit) (if BI (ne SI (and val (sll 1 8)) 0) 1 0)) + (set (reg BI h-qbit) (if BI (ne SI (and val (sll 1 31)) 0) 1 0)) + ; Set the U bit last, so the setter functions for the other bits + ; don't see it as set from this operation. It is not cleared from + ; this operation, so we don't have to handle that; it's only + ; cleared "manually" from within simulator-specific context-switch + ; machinery. + (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) + (set-quiet (raw-reg SI h-sr-x index) val))) + ((eq index (regno usp)) + ; In user mode, set general register 14 too, whenever setting USP. + (sequence + () + (if (reg BI h-ubit) (set (raw-reg SI h-gr-x (regno sp)) val)) + (set (raw-reg SI h-sr-x (regno usp)) val))) + ((eq index (regno srs)) + (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno srs)) val))) + ((eq index (regno ebp)) + (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno ebp)) val))) + ((eq index (regno pid)) + (if (not (reg BI h-ubit)) + (sequence + () + (c-call VOID "@cpu@_write_pid_handler" val) + (set (raw-reg h-sr-x (regno pid)) val)))) + ((eq index (regno spc)) + (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno spc)) val))) + (else (set-quiet (raw-reg SI h-sr-x index) val)))) +) + +(define-hardware + (name h-supr) + (attrs MACH-V32 VIRTUAL) + (comment "Support registers") + (type register SI (16)) + (values keyword "" (.map (.pmacro (y) ((.str S y) y)) (.iota 16))) + (get (index) (c-call SI "@cpu@_read_supr" index)) + (set (index val) (c-call VOID "@cpu@_write_supr" index val)) +) + +(define-pmacro (cris-dsh semantic-name name comment attrs type) + "Like dsh, but the semantic-name is separate" + (define-full-hardware + name comment attrs semantic-name type () () () () () ()) +) + +; We define the condition codes that hold arithmetic flags separately +; and "or" them in, in the get and set methods of the special +; registers. We define arithmetic flags as any of C V Z N X. They +; thankfully have that order (zero-based) in all processor versions. + +; To avoid having two variants of most move-type instructions because V32 +; doesn't set C and V (and N and Z), we fake the setting to virtual +; registers which have two different implementations. +(define-pmacro (cris-move-flag f f-name f-whence) + "Flag set differently in pre-v32 and v32 in some cases" + (begin + (dsh (.sym h- f bit) (.str f-name " bit") () (register BI)) + (cris-d-hwreg (.sym h- f bit-move) BI) + (define-hardware + (semantic-name (.sym h- f bit-move-x)) + (name (.sym h- f bit-move-v32)) + (comment (.str f-name " bit set in " f-whence " instructions, ignored")) + (attrs MACH-V32 VIRTUAL) + (type register BI) + (get + () + (sequence BI () + (error (.str "Can't get h-" f "bit-move on CRISv32")) 0)) + (set (val) (nop))) + (define-hardware + (semantic-name (.sym h- f bit-move-x)) + (name (.sym h- f bit-move-pre-v32)) + (comment + (.str + f-name " bit set in " f-whence " instructions, same as " f "bit")) + (attrs MACH-PRE-V32 VIRTUAL) + (type register BI) + (get () (reg (.sym h- f bit))) + (set (val) (set (reg (.sym h- f bit)) val)))) +) + +(cris-move-flag c "carry" "move-type") +(cris-move-flag v "overflow" "move-type") +(cris-move-flag z "zero" "moveq") +(cris-move-flag n "sign" "moveq") + +(dsh h-xbit "extended-arithmetic bit" () (register BI)) +(cris-d-hwreg h-ibit BI) +(cris-dsh h-ibit-x h-ibit-pre-v32 + "interrupt-enable bit" (MACH-PRE-V32) (register BI)) +(dsh h-pbit "sequence-broken bit" ((MACH crisv10,crisv32)) (register BI)) +(dsh h-rbit "carry bit for MCP+restore-p bit" (MACH-V32) (register BI)) +(cris-d-hwreg h-ubit BI) +(cris-dsh h-ubit-x h-ubit-pre-v32 + "user mode bit" ((MACH crisv10)) (register BI)) +(dsh h-gbit "guru mode bit" (MACH-V32) (register BI)) + +; When doing a transition from kernel to user mode on V32, we save the +; stack pointer in an internal register and copy USP to R14, so we don't +; need non-trivial handlers for general registers. +(dsh + h-kernel-sp + "Kernel stack pointer during user mode" + (MACH-V32) + (register SI) +) + +(define-hardware + (semantic-name h-ubit-x) + (name h-ubit-v32) + (comment "User mode bit") + (attrs MACH-V32) + (type register BI) + (set + (val) + (sequence + () + (if (andif val (not (raw-reg BI h-ubit-x))) + (sequence + () + (set (reg SI h-kernel-sp) (raw-reg h-gr-x (regno sp))) + (set (raw-reg h-gr-x (regno sp)) (raw-reg h-sr-x (regno usp))) + (set (raw-reg BI h-ubit-x) val) + (c-call VOID "@cpu@_usermode_enabled"))))) +) + +(define-hardware + (semantic-name h-ibit-x) + (name h-ibit-v32) + (comment "Interrupt-enable bit") + (attrs MACH-V32) + (type register BI) + (set + (val) + (sequence + () + (if (not (reg BI h-ubit)) + (sequence + ((BI enabled)) + (set enabled (andif val (not (raw-reg BI h-ibit-x)))) + (set (raw-reg BI h-ibit-x) val) + ; Call handler when enabling. + (if enabled (c-call VOID "@cpu@_interrupts_enabled")))))) +) + +(define-hardware + (name h-mbit) + (comment "NMI enable bit") + (attrs MACH-V32) + (type register BI) + (set + (val) + (sequence + () + ; Don't allow clearing (through this handler) when once set. + (if (andif val (andif (not (raw-reg BI h-mbit)) (not (reg BI h-ubit)))) + (sequence + () + (set (raw-reg BI h-mbit) 1) + ; Call handler when enabling. + (c-call VOID "@cpu@_nmi_enabled"))))) +) + +(define-pmacro + (dsh-cond-bit-v32 x-name x-comment x-cond) + "dsh bit for MACH-V32, with bit only changeable when X-COND" + (define-hardware + (name x-name) + (comment x-comment) + (attrs MACH-V32) + (type register BI) + (set (val) (sequence () (if x-cond (set (raw-reg BI x-name) val))))) +) +(define-pmacro + (dsh-protected-bit-v32 x-name x-comment) + "dsh bit for MACH-V32, with bit only changeable in kernel mode" + (dsh-cond-bit-v32 x-name x-comment (not (reg BI h-ubit))) +) +(dsh-protected-bit-v32 h-qbit "Pending single-step bit") + +(define-hardware + (name h-sbit) + (comment "Cause single step exception on ... [see CRISv32 ref] bit") + (attrs MACH-V32) + (type register BI) + (set + (val) + (sequence + () + (if (not (reg BI h-ubit)) + (sequence + ((BI enabled)) + (set enabled (andif val (not (raw-reg BI h-sbit)))) + (set (raw-reg BI h-sbit) val) + ; Call handler when enabling. + (if enabled (c-call VOID "@cpu@_single_step_enabled")))))) +) + +(dnop cbit "" (SEM-ONLY) h-cbit f-nil) +(dnop cbit-move + "cbit for pre-V32, nothing for newer" (SEM-ONLY) h-cbit-move f-nil) +(dnop vbit "" (SEM-ONLY) h-vbit f-nil) +(dnop vbit-move + "vbit for pre-V32, nothing for newer" (SEM-ONLY) h-vbit-move f-nil) +(dnop zbit "" (SEM-ONLY) h-zbit f-nil) +(dnop zbit-move + "zbit for pre-V32, nothing for newer" (SEM-ONLY) h-zbit-move f-nil) +(dnop nbit "" (SEM-ONLY) h-nbit f-nil) +(dnop nbit-move + "nbit for pre-V32, nothing for newer" (SEM-ONLY) h-nbit-move f-nil) +(dnop xbit "" (SEM-ONLY) h-xbit f-nil) +(dnop ibit "" (SEM-ONLY) h-ibit f-nil) +(dnop ubit "" (SEM-ONLY (MACH crisv10,crisv32)) h-ubit f-nil) +(dnop pbit "" (SEM-ONLY (MACH crisv10,crisv32)) h-pbit f-nil) +(dnop + rbit "carry bit for MCP+restore-P flag bit" (SEM-ONLY MACH-V32) h-rbit f-nil) +(dnop sbit "" (SEM-ONLY MACH-V32) h-sbit f-nil) +(dnop mbit "" (SEM-ONLY MACH-V32) h-mbit f-nil) +(dnop qbit "" (SEM-ONLY MACH-V32) h-qbit f-nil) + +(cris-d-hwreg h-insn-prefixed-p BI) +(cris-dsh + h-insn-prefixed-p-x + h-insn-prefixed-p-pre-v32 + "instruction-is-prefixed bit" + (MACH-PRE-V32) + (register BI) +) + +; CRISv32 has no prefixing on memory accesses. CGEN-FIXME: [Once (eq-attr +; (current-mach) ...) works]: can we change andif and/or orif so it +; doesn't look too close at short-circuited operands and avoid defining an +; operand that doesn't apply to a certain mach? +(define-hardware + (semantic-name h-insn-prefixed-p-x) + (name h-insn-prefixed-p-v32) + (attrs MACH-V32 VIRTUAL) + (comment "instruction-is-prefixed bit") + (type register BI) + (get () (const BI 0)) + (set (val) (nop)) +) +(dnop + prefix-set + "Instruction-prefixed flag" + (SEM-ONLY) + h-insn-prefixed-p + f-nil +) + +(cris-dsh + h-prefixreg h-prefixreg-pre-v32 + "Prefix-address register" (MACH-PRE-V32) (register SI)) +(define-hardware + (semantic-name h-prefixreg) + (name h-prefixreg-v32) + (comment "Prefix-address register, redirecting to ACR") + (attrs MACH-V32 VIRTUAL) + (type register SI) + ; Why can't we have just a "acr" a.k.a "(reg h-gr 15)" here? + (get () acr) + (set (value) (set acr value)) +) + +(dnop + prefixreg + "Prefix address" + (SEM-ONLY) + h-prefixreg + f-nil +) + +;;;;;;;;;;;;;;;;;; -ifield + +; 15 0 +; +-----------+-----+-----------+-----+-----------+ +; | Operand2 | Mode| Opcode | Size| Operand1 | +; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +; +; Figure 5. General instruction format. +; +; Some deviations from this format exist, [see below]. + +; Field specifiers in CGEN specify the highest numbered bit followed by +; the number of bits. + +(dnf f-operand1 "Operand1" () 3 4) +(dnf f-size "Size" () 5 2) +(dnf f-opcode "Opcode" () 9 4) +(dnf f-mode "Mode" () 11 2) +(dnf f-operand2 "Operand2" () 15 4) + +; Subfields. FIXME: unfortunately there's some limitation in CGEN so we +; can't (as would be somewhat intuitive) make f-mode a multi-ifield +; consisting of these two, concatenated. +(dnf f-memmode "Indirect of autoincrement" () 10 1) +(dnf f-membit "Memory specifier" () 11 1) + +(dnf f-b5 "Bit 5 (zero for some quick operands)" () 5 1) + +; When the addressing mode is quick immediate, the low bits are +; part of the operand. +(dnf f-opcode-hi "Opcode field, high bits" () 9 2) + +; Common synonyms for those fields. +(define-pmacro f-source f-operand1) +(define-pmacro f-dest f-operand2) + +(dnmf + f-dstsrc "Dest and source fields concatenated" () UINT + (f-dest f-source) + ; Insert-code. + (sequence + ((SI tmpval)) + (set tmpval (ifield f-dstsrc)) + (set (ifield f-dest) (and (srl tmpval 4) #xf)) + (set (ifield f-source) (and tmpval #xf))) + ; Extract-code. + (set + (ifield f-dstsrc) + (and (or (ifield f-source) (sll (ifield f-dest) 4)) #xff)) +) + +;The 6-bit value may be sign or zero extended depending on the instruction. +; +; 15 0 +; +-----------+-----+-----------+-----+-----------+ +; | Operand2 | Mode| Opcode | Immediate value | +; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +; +; Figure 6. Quick immediate addressing mode instruction format. + +(dnf f-u6 "Quick immediate unsigned 6-bit" () 5 6) +(df f-s6 "Quick signed 6-bit" () 5 6 INT #f #f) + +; There's also a variant used with shift insns, with one bit larger opcode +; and one bit smaller immediate value, though it doesn't have a general +; graphic description. +(dnf f-u5 "Quick unsigned 5-bit" () 4 5) + +; Similarly, a four-bit immediate field. +(dnf f-u4 "Quick unsigned 4-bit" () 3 4) + +; An 8-bit signed value, which doesn't have a general graphic description. +(df f-s8 "Source signed byte" () 7 8 INT #f #f) + +; The 9-bit branch offset, with bit 0 in the field being bit 8 in the +; offset, and bit 0 in the offset always 0. +(df f-disp9-hi "PC-relative 9-bit offset, sign bit" () 0 1 INT #f #f) +(dnf f-disp9-lo "PC-relative 9-bit offset, low bits" () 7 7) + +; It would work to have this in two mach-specific variants, but +; considering that current-mach-is-v32 is a compile-time constant, we +; don't win any simulator performance. +(dnmf + f-disp9 "PC-relative 9-bit offset" + (PCREL-ADDR) + INT + (f-disp9-hi f-disp9-lo) + ; Insert-code. + (sequence + ((SI absval)) + (set absval (srl (sub (sub SI (ifield f-disp9) pc) + (if SI current-mach-is-v32 0 2)) 1)) + (set (ifield f-disp9-hi) (if (lt absval 0) 1 0)) + (set (ifield f-disp9-lo) (and absval) #x7f)) + ; Extract-code. + (sequence + ((SI abslo) (SI absval)) + (set abslo (sll (ifield f-disp9-lo) 1)) + (set absval + (or (if SI (ne (ifield f-disp9-hi) 0) + (inv SI #xff) + 0) + abslo)) + (set (ifield f-disp9) + (add SI (add SI pc absval) (if SI current-mach-is-v32 0 2)))) +) + +; The operand of LAPCQ is PC-relative, similar to f-disp9 but unsigned, +; and only four bits. +(df + f-qo + "PC-relative 4-bit unsigned offset, counted from start of insn" + (MACH-V32 PCREL-ADDR) + 3 4 + UINT + ; Insert-code. + ((value pc) (srl SI (sub SI value pc) 1)) + ; Extract-code. + ((value pc) (add SI pc (sll SI value 1))) +) + +; 8-bit, 16-bit and 32-bit immediates. The 8-bit values are constructed +; through encoding/decoding functions, since the PC increment is by a +; word. +(define-pmacro (dcrisf x-name x-comment x-attrs x-word-offset x-word-length + x-start x-length x-mode x-encode x-decode) + (define-ifield + (name x-name) + (comment x-comment) + (.splice attrs (.unsplice x-attrs)) + (word-offset x-word-offset) + (word-length x-word-length) + (start x-start) + (length x-length) + (mode x-mode) + (.splice encode (.unsplice x-encode)) + (.splice decode (.unsplice x-decode)) + ) +) + +(dcrisf + f-indir-pc+-byte "[PC+] 8-bit field" (SIGN-OPT) + 16 16 + 15 16 ; CGEN-FIXME: Should be 7 8 + INT (#f) (#f) +) + +(dcrisf + f-indir-pc+-word "[PC+] 16-bit field" (SIGN-OPT) + 16 16 15 16 INT (#f) (#f) +) + +; CGEN-FIXME: I shouldn't have to use trunc here, should I? +; Sign-extension should be implicit through use of SI (as opposed to USI) +; and additionally through SIGN-OPT. The ext isn't actually needed, but +; having it there rather than implicit makes more sense than to just have +; the trunc. +(dcrisf + f-indir-pc+-word-pcrel "[PC+] PC-relative 16-bit field" + (PCREL-ADDR SIGN-OPT) + 16 16 15 16 SI + ((value pc) (sub SI value (add SI pc (if SI current-mach-is-v32 0 4)))) + ((value pc) (add SI (ext SI (trunc HI value)) (add SI pc (if SI current-mach-is-v32 0 4)))) +) + +(dcrisf + f-indir-pc+-dword "PC autoincrement - 32-bit field" (SIGN-OPT) + 16 32 31 32 INT (#f) (#f) +) + +(dcrisf + f-indir-pc+-dword-pcrel + "[PC+] PC-relative 32-bit field, counted from start of insn" + (SIGN-OPT MACH-V32 PCREL-ADDR) + 16 32 31 32 INT + ((value pc) (sub SI value pc)) + ((value pc) (add SI pc value)) +) + +;;;;;;;;;;;;;;;;;; -insn-enum -normal-operand -normal-derived-operand + +;; How different fields are transformed into something we put in insns. + +; m := size modifier, byte (00), word (01) or dword (10) +; z := size modifier, byte (0) or word (1) +; (For the latter, the "higher" bit is always 0, mapping trivially on m.) + +(define-normal-insn-enum + insn-size + "Standard instruction operand size" + () + SIZE_ + f-size + ("BYTE" "WORD" "DWORD" "FIXED") +) + +; The mode field for insns with "s" operand (perhaps with a partial set of +; operand types). +(define-normal-insn-enum + insn-mode + "Standard instruction addressing modes" + () + MODE_ + f-mode + ("QUICK_IMMEDIATE" "REGISTER" "INDIRECT" "AUTOINCREMENT") +) + +(define-normal-insn-enum + insn-memoryness-mode + "Whether the operand is indirect" + () + MODEMEMP_ + f-membit + ("NO" "YES") +) + +; FIXME: Needed? +(define-normal-insn-enum + insn-memincness-mode + "Whether the indirect operand is autoincrement" + () + MODEINCP_ + f-memmode + ("NO" "YES") +) + +; Special semantics for multiply. +(define-pmacro MODE_MULU MODE_INDIRECT) +(define-pmacro MODE_MULS MODE_AUTOINCREMENT) + +(define-normal-insn-enum + insn-signed-size + "Signed instruction operand size" + () + SIGNED_ + f-size + ("UNDEF_SIZE_0" "UNDEF_SIZE_1" "BYTE" "WORD") +) + +(define-normal-insn-enum + insn-unsigned-size + "Unsigned instruction operand size" + () + UNSIGNED_ + f-size + ("BYTE" "WORD" "UNDEF_SIZE_2" "UNDEF_SIZE_3") +) + +; Rs := source operand, register addressing mode +(dnop Rs "Source general register" () h-gr f-source) + +; [Rs] := source operand, indirect addressing mode +; = MODE_INDIRECT Rs + +; [Rs+] := source operand, autoincrement addressing mode (see note!) +; = MODE_AUTOINCREMENT Rs + +; The union of [Rs] and [Rs(+)] +; = MODEMEMP_YES Rs + +; Whether an indirect operand is increment can be obtained as an operand by +; = inc +(dnop inc "Incrementness of indirect operand" () h-inc f-memmode) + +; or as an affirmative specifier +; = MODEINCP_YES +; (or MODEINCP_NO) + +; s := source operand, any of the modes Rs, [Rs] or [Rs+] +; No common operand; each are handled separately, using the above definitions. + +; Ps := source operand, special register +; It's in the field usually used for the destination. +(dnop Ps "Source special register" () h-sr f-dest) + +; Ss := source operand, support register +; It's in the field usually used for the destination. +(dnop Ss "Source support register" (MACH-V32) h-supr f-dest) + +; Sd := source operand, support register +(dnop Sd "Destination support register" (MACH-V32) h-supr f-dest) + +; i := 6-bit signed immediate operand +(dnop i "Quick signed 6-bit" () h-sint f-s6) + +; j := 6-bit unsigned immediate operand +(dnop j "Quick unsigned 6-bit" () h-uint f-u6) + +; c := 5-bit immediate shift value +(dnop c "Quick unsigned 5-bit" () h-uint f-u5) + +; qo := 4-bit unsigned immediate operand +(dnop qo "Quick unsigned 4-bit, PC-relative" (MACH-V32) h-addr f-qo) + +; Rd := destination operand, register addressing mode +(dnop Rd "Destination general register" () h-gr f-dest) +(define-pmacro Rd-sfield Rs) +(define-pmacro Rs-dfield Rd) + +; [Rd] := destination operand, indirect addressing mode +; = MODE_INDIRECT Rd + +; [Rd+] := destination operand, autoincrement addressing mode +; = MODE_AUTOINCREMENT Rd + +; [PC+] := destination operand PC, autoincrement addressing mode +; = MODE_AUTOINCREMENT (f-dest 15) X +; where X is one of sconst8, uconst8, sconst16, uconst16 or const32. +(dnop sconst8 "Signed byte [PC+]" () h-sint f-indir-pc+-byte) +(dnop uconst8 "Unsigned byte [PC+]" () h-uint f-indir-pc+-byte) +(dnop sconst16 "Signed word [PC+]" () h-sint f-indir-pc+-word) +(dnop uconst16 "Unsigned word [PC+]" () h-uint f-indir-pc+-word) +(dnop const32 "Dword [PC+]" () h-uint f-indir-pc+-dword) +(dnop const32-pcrel "Dword [PC+]" () h-addr f-indir-pc+-dword-pcrel) + +; d := destination operand, any of the modes Rd, [Rd] or [Rd+] +; No common operand; each are handled separately, using the above definitions. + +; Pd := destination operand, special register +(dnop Pd "Destination special register" () h-sr f-dest) + +; o := 8-bit immediate offset value +(dnop o "Signed 8-bit" () h-sint f-s8) + +; The division of operand semantics and insn fields in the CRIS +; instruction set reference doesn't permit a simple mapping to a +; simulator description, and the division of insn fields and +; semantics in CGEN is not between the define-normal-ifield +; vs. define-normal-operand. For example, the "o" operand is +; PC-relative for branch insns, as described by the CGEN f-disp9 +; field. +; See comment at f-disp9; thankfully the mach +; attribute works here to have two different definitions by the +; same name. +(dnop o-pcrel "9-bit signed immediate PC-rel" + () + h-iaddr f-disp9) + +(dnop o-word-pcrel "16-bit signed immediate PC-rel" + () + h-iaddr f-indir-pc+-word-pcrel) + +; cc := condition code +(dnop cc "Condition codes" () h-ccode f-dest) + +; n := 4 bit breakpoint exception vector index +(dnop n "Quick unsigned 4-bit" () h-uint f-u4) + +; The "option" in the SWAP insn. +(dnop swapoption "Swap option" () h-swap f-dest) + +(dnop list-of-flags "Flag bits as operand" () h-flagbits f-dstsrc) + +; Enumerations for insn codes, for use in insn definitions +; instead of raw numbers. See it as operand definitions for the +; opcode field. + +(define-normal-insn-enum + insn-qi-opc + "Insns for MODE_QUICK_IMMEDIATE" + () + Q_ + f-opcode + ("BCC_0" "BCC_1" "BCC_2" "BCC_3" + "BDAP_0" "BDAP_1" "BDAP_2" "BDAP_3" + "ADDQ" "MOVEQ" "SUBQ" "CMPQ" + "ANDQ" "ORQ" "ASHQ" "LSHQ") +) + +(define-normal-insn-enum + insn-qihi-opc + "Same as insn-qi-opc, though using only the high two bits of the opcode" + () + QHI_ + f-opcode-hi + ("BCC" "BDAP" "OTHER2" "OTHER3") +) +(define-pmacro QHI_ADDOQ QHI_BDAP) + +(define-normal-insn-enum + insn-r-opc + "Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" + () + R_ + f-opcode + ("ADDX" "MOVX" "SUBX" "LSL" + "ADDI" "BIAP" "NEG" "BOUND" + "ADD" "MOVE" "SUB" "CMP" + "AND" "OR" "ASR" "LSR") +) +(define-pmacro R_ADDI_ACR R_BIAP) + +(define-normal-insn-enum + insn-rfix-opc + "Insns for MODE_REGISTER and SIZE_FIXED" + () + RFIX_ + f-opcode + ("ADDX" "MOVX" "SUBX" "BTST" + "SCC" "ADDC" "SETF" "CLEARF" + "MOVE_R_S" "MOVE_S_R" "ABS" "DSTEP" + "LZ" "SWAP" "XOR" "MSTEP") +) +(define-pmacro RFIX_MCP RFIX_MSTEP) + +(define-normal-insn-enum + insn-indir-opc + "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" + () + INDIR_ + f-opcode + ("ADDX" "MOVX" "SUBX" "CMPX" + "MUL" "BDAP_M" "ADDC" "BOUND" + "ADD" "MOVE_M_R" "SUB" "CMP" + "AND" "OR" "TEST" "MOVE_R_M") +) +(define-pmacro INDIR_ADDO INDIR_BDAP_M) + +(define-normal-insn-enum + insn-infix-opc + "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED" + () + INFIX_ + f-opcode + ("ADDX" "MOVX" "SUBX" "CMPX" + "JUMP_M" "DIP" "JUMP_R" "BCC_M" + "MOVE_M_S" "MOVE_S_M" "BMOD" "BSTORE" + "RBF" "SBFS" "MOVEM_M_R" "MOVEM_R_M") +) + +(define-pmacro INFIX_MOVE_SS INFIX_SBFS) +(define-pmacro INFIX_LAPC INFIX_DIP) +(define-pmacro INFIX_RFE INFIX_JUMP_M) +(define-pmacro INFIX_RFN INFIX_JUMP_M) +(define-pmacro INFIX_HALT INFIX_JUMP_M) +(define-pmacro INFIX_SFE INFIX_JUMP_M) +(define-pmacro INFIX_RFG INFIX_JUMP_M) +(define-pmacro INFIX_JAS_R INFIX_JUMP_R) +(define-pmacro INFIX_JAS_M INFIX_JUMP_R) +(define-pmacro INFIX_JASC INFIX_RBF) +(define-pmacro INFIX_JUMP_P INFIX_BCC_M) +(define-pmacro INFIX_BAS INFIX_BMOD) +(define-pmacro INFIX_BASC INFIX_BSTORE) +(define-pmacro INFIX_BREAK INFIX_JUMP_M) +(define-pmacro INFIX_FIDXI INFIX_JUMP_M) +(define-pmacro INFIX_FIDXD INFIX_BAS) +(define-pmacro INFIX_FTAGI INFIX_JUMP_M) +(define-pmacro INFIX_FTAGD INFIX_BAS) + +; Classes of insns: +; Move-to-register, move-to-memory, move-to/from-other-register, +; logical, arithmetic, branch. +; Classes of operands: +; quick, register, memory-indirect, memory-postinc. + + +;;;;;;;;;;;;;;;;;; -normal-insn + +(define-pmacro (dni-bwd-attr name comment attr syntax fmt fsem timing) + (begin + (dni (.sym name .b) (.str "byte " comment) attr (.str name ".b " syntax) + (.splice (.unsplice fmt) SIZE_BYTE) + (fsem QI) + timing) + (dni (.sym name .w) (.str "word " comment) attr (.str name ".w " syntax) + (.splice (.unsplice fmt) SIZE_WORD) + (fsem HI) + timing) + (dni (.sym name .d) (.str "dword " comment) attr (.str name ".d " syntax) + (.splice (.unsplice fmt) SIZE_DWORD) + (fsem SI) + timing)) +) + +(define-pmacro (dni-cdt-attr name comment attr syntax fmt semantics) + "dni without specifying timing" + (dni name comment attr syntax fmt semantics (cris-timing)) +) + +(define-pmacro (dni-cdt-bwd-attr name comment attr syntax fmt fsem) + (begin + (dni-cdt-attr (.sym name .b-r) (.str "byte " comment) attr (.str name ".b " syntax) + (.splice (.unsplice fmt) SIZE_BYTE) + (fsem QI)) + (dni-cdt-attr (.sym name .w-r) (.str "word " comment) attr (.str name ".w " syntax) + (.splice (.unsplice fmt) SIZE_WORD) + (fsem HI)) + (dni-cdt-attr (.sym name .d-r) (.str "dword " comment) attr (.str name ".d " syntax) + (.splice (.unsplice fmt) SIZE_DWORD) + (fsem SI))) +) + +; Some convenience macros based on the above ones. +(define-pmacro (dni-cdt-bwd name comment syntax fmt fsem) + (dni-cdt-bwd-attr name comment () syntax fmt fsem) +) + +(define-pmacro (dni-bwd name comment syntax fmt fsem timing) + (dni-bwd-attr comment () syntax fmt fsem timing) +) + +(define-pmacro-map + (((dni-cdt name comment syntax fmt semantics) + (dni-cdt-attr name comment () syntax fmt semantics)) + ((dni-c-QI-attr name comment attr syntax fmt fsem) + (dni name comment attr syntax fmt fsem (cris-timing-const-QI))) + ((dni-c-HI-attr name comment attr syntax fmt fsem) + (dni name comment attr syntax fmt fsem (cris-timing-const-HI))) + ((dni-c-SI-attr name comment attr syntax fmt fsem) + (dni name comment attr syntax fmt fsem (cris-timing-const-SI)))) +) + +(define-pmacro-map + (((dni-c-QI name comment syntax fmt fsem) + (dni-c-QI-attr name comment () syntax fmt fsem)) + ((dni-c-HI name comment syntax fmt fsem) + (dni-c-HI-attr name comment () syntax fmt fsem)) + ((dni-c-SI name comment syntax fmt fsem) + (dni-c-SI-attr name comment () syntax fmt fsem))) +) + +; These flags are both cleared by all insns except prefixes (before +; CRISv32) and "setf x", so we put them in a handy macro. +(define-pmacro + (reset-x-p) + (sequence + () + (set xbit 0) + (set prefix-set 0)) +) + +; NOP | 0 0 0 0| 0 1| 0 1 0 0| 0 0| 1 1 1 1| +; (For V32, "SETF" (no flags) is used.) +(dni-cdt-attr + nop "nop" (MACH-PC) "nop" + (+ (f-operand2 0) R_ADDI MODE_REGISTER SIZE_BYTE (f-operand1 15)) + (reset-x-p) +) + +; Pre- and v32+ variants MOVE insns set flags differently. These two +; macros for flag settings are meant to be used in all MOVE insns. +(define-pmacro (setf-moveq value) + (sequence + () + (set-quiet nbit-move (lt SI value 0)) + (set-quiet zbit-move (andif BI (eq SI value 0) (if BI xbit zbit 1))) + (set-quiet cbit-move 0) + (set-quiet vbit-move 0) + (reset-x-p)) +) + +(define-pmacro (setf-move size value) + (sequence + () + (set nbit (lt size value 0)) + (set zbit (andif BI (eq size value 0) (if BI xbit zbit 1))) + (set-quiet cbit-move 0) + (set-quiet vbit-move 0) + (reset-x-p)) +) +; The CGEN binop-with-bit operations are not documented well enough that I +; trust their semantics to remain stable. Better define local ones: the +; semantics become explicit. +(define-pmacro-map + (((add-overflow size R D S carry) + (orif BI (andif BI (andif BI (lt size S 0) (lt size D 0)) (ge size R 0)) + (andif BI (andif BI (ge size S 0) (ge size D 0)) (lt size R 0)))) + ((add-carry size R D S carry) + (orif BI (andif BI (lt size S 0) (lt size D 0)) + (orif BI (andif BI (lt size D 0) (ge size R 0)) + (andif BI (lt size S 0) (ge size R 0))))) + ((sub-overflow size R D S carry) + (orif BI (andif BI (andif BI (ge size S 0) (lt size D 0)) (ge size R 0)) + (andif BI (andif BI (lt size S 0) (ge size D 0)) (lt size R 0)))) + ((sub-carry size R D S carry) + (orif BI (andif BI (lt size S 0) (ge size D 0)) + (orif BI (andif BI (ge size D 0) (lt size R 0)) + (andif BI (lt size S 0) (lt size R 0))))) + ; Only valid for size := DI + ((mulu-overflow size R D S carry) + (ne DI R (zext DI (trunc SI R)))) + ((mulu-carry size R D S carry) + (andif current-mach-is-v32 carry)) + ((muls-overflow size R D S carry) + (ne DI R (ext DI (trunc SI R)))) + ((muls-carry size R D S carry) + (andif current-mach-is-v32 carry))) +) + +(define-pmacro (setf-arit2 size op source1 source2 result carryin carryout) + "Set no-prefix, x=0, carryout, v, z and n according to operation OP in size SIZE" + (sequence + () + (set carryout ((.sym op -carry) size result source1 source2 carryin)) + (set nbit (lt size result 0)) + (set zbit (andif BI (eq size result 0) (orif BI zbit (not BI xbit)))) + (set vbit ((.sym op -overflow) size result source1 source2 carryin)) + (reset-x-p)) +) +(define-pmacro (setf-arit size op source1 source2 result carry) + "Set no-prefix, x=0, c, v, z and n according to operation OP in size SIZE" + (setf-arit2 size op source1 source2 result carry cbit) +) + +; Let's have convienence macros for arithmetic, including evaluation of the +; operation, destination modification, flag setting and carry propagation. +(define-pmacro + (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin) + "Core for performing some three-operand arithmetic with carry as parameter" + (sequence + ((size tmpopd) (size tmpops) (BI carry) (size newval)) + (set tmpops srcop2) + (set tmpopd srcop1) + (set carry carryin) + (set newval ((.sym arit c) tmpopd tmpops (if BI (eq xbit 0) 0 carry))) + (fdest size fdest_op newval) + (setf-arit2 size arit tmpopd tmpops newval carry carryout)) +) + +(define-pmacro + (cris-arit5-int arit size destregno srcop1 srcop2 carryout carryin) + "As cris-arit6-int, but to set a part of a general register" + (cris-arit6-int + arit + size + (.pmacro (sz regno val) (set-subreg-gr sz regno val)) + destregno + srcop1 + srcop2 + carryout + carryin) +) + +(define-pmacro (cris-arit5 arit size destreg srcop1 srcop2 carryout carryin) + "As cris-arit5-int, but takes a register as parameter, not register number" + (cris-arit5-int arit size (regno destreg) srcop1 srcop2 carryout carryin) +) +(define-pmacro (cris-arit3-int arit size destregno srcop1 srcop2) + "As cris-arit5-int, but with carry-in same as carry-out" + (cris-arit5-int arit size destregno srcop1 srcop2 cbit cbit) +) +(define-pmacro (cris-arit3 arit size destreg srcop1 srcop2) + "As cris-arit3-int, but takes a register as parameter, not register number" + (cris-arit3-int arit size (regno destreg) srcop1 srcop2) +) +(define-pmacro (cris-arit arit size destreg srcop) + "As cris-arit3, but with destination same as srcop1" + (cris-arit3 arit size destreg destreg srcop) +) +(define-pmacro (cris-arit-3op arit size destsrcop2 srcop1 dest-3op) + "Similar to cris-arit3-int, but for prefixed operand only" + (cris-arit3-int arit size + (if SI (andif prefix-set (not inc)) + (regno dest-3op) + (regno destsrcop2)) + destsrcop2 srcop1) +) + +; Convenience macros to select a part of a value and its complement, for +; the .b, .w and .d operations. +(define-pmacro (QI-part val) (and SI val #xff)) +(define-pmacro (non-QI-part val) (and SI val #xffffff00)) +(define-pmacro (HI-part val) (and SI val #xffff)) +(define-pmacro (non-HI-part val) (and SI val #xffff0000)) +(define-pmacro (SI-part val) val) +(define-pmacro (non-SI-part val) 0) +(define-pmacro + (set-subreg-gr-bw BWD gregno newval) + "Set a byte or word part or full dword of a general register" + (sequence + ((SI oldregval)) + (set oldregval (reg h-raw-gr gregno)) + (set (reg h-gr gregno) + (or SI ((.sym BWD -part) newval) ((.sym non- BWD -part) oldregval)))) +) +(define-pmacro (set-subreg-gr BWD gregno newval) + ((.sym set-subreg-gr- BWD) BWD gregno newval) +) +(define-pmacro (set-subreg-gr-SI SI gregno newval) + (set (reg h-gr gregno) newval) +) +(define-pmacro set-subreg-gr-HI set-subreg-gr-bw) +(define-pmacro set-subreg-gr-QI set-subreg-gr-bw) + +; MOVE.m Rs,Rd [ Rd | 011001mm | Rs ] +(dni-cdt-bwd + move "move.m r,R" + "move.m ${Rs},${Rd}" + (+ Rd MODE_REGISTER R_MOVE Rs) + (.pmacro + (BWD) + (sequence + ((BWD newval)) + (set newval Rs) + (set-subreg-gr BWD (regno Rd) newval) + (setf-move BWD newval))) +) + +; MOVE.D PC,Rd [ Rd | 01100110 | 1111 ] +; This insn is used in PIC code to find out the code address. It's an +; exception to the (guarded) non-implementation of PC operands in this +; file. +(dni-cdt-attr + movepcr "move.d PC,R" + (MACH-PC UNCOND-CTI) + "move.d PC,${Rd}" + (+ Rd MODE_REGISTER R_MOVE SIZE_DWORD (f-source 15)) + (sequence + ((SI pcval)) + (set pcval (add SI pc 2)) + (set Rd pcval) + (setf-move SI pcval)) +) + +; MOVEQ i,Rd [ Rd | 001001 | i ] +(dni-cdt + moveq "moveq" + "moveq $i,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_MOVEQ i) + (sequence + ((SI newval)) + (set newval i) + (set Rd newval) + (setf-moveq newval)) +) + +(define-pmacro (dni-cdt-sbw name comment syntax fmt fsem) + "Insn generator for insns with signed .b and .w variants" + (begin + (dni-cdt + (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) + (.splice (.unsplice fmt) SIGNED_BYTE) + (fsem QI)) + (dni-cdt + (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) + (.splice (.unsplice fmt) SIGNED_WORD) + (fsem HI))) +) + +; MOVS.z Rs,Rd [ Rd | 0100011z | Rs ] +(dni-cdt-sbw + movs "movs.m r,R" + "movs.m ${Rs},${Rd}" + (+ Rd MODE_REGISTER R_MOVX Rs) + (.pmacro + (BW) + (sequence + ((BW tmpops) (SI newval)) + (set tmpops Rs) + (set newval (ext SI tmpops)) + (set Rd newval) + (setf-move SI newval))) +) + +(define-pmacro (dni-cdt-ubw name comment syntax fmt fsem) + "Similar to dni-cdt-sbw but for unsigned operations" + (begin + (dni-cdt + (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) + (.splice (.unsplice fmt) UNSIGNED_BYTE) + (fsem QI)) + (dni-cdt + (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) + (.splice (.unsplice fmt) UNSIGNED_WORD) + (fsem HI))) +) + +; MOVU.z Rs,Rd [ Rd | 0100010z | Rs ] +(dni-cdt-ubw + movu "movu.m r,R" + "movu.m ${Rs},${Rd}" + (+ Rd MODE_REGISTER R_MOVX Rs) + (.pmacro + (BW) + (sequence + ((BW tmpops) (SI newval)) + (set tmpops Rs) + (set newval (zext SI tmpops)) + (set Rd newval) + (setf-move SI newval))) +) + +; (MOVE.m [PC+],Rd [ Rd | 111001mm | 1111 ]) +; For the moment, it doesn't seem worthwhile to make a dni-c-bwd macro; +; too many places to parametrize. +(dni-c-QI + movecbr "move.b [PC+],R" + "move.b ${sconst8},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_BYTE (f-source 15) sconst8) + (sequence + ((QI newval)) + (set newval sconst8) + (set-subreg-gr QI (regno Rd) newval) + (setf-move QI newval)) +) + +(dni-c-HI + movecwr "move.w [PC+],R" + "move.w ${sconst16},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_WORD (f-source 15) sconst16) + (sequence + ((HI newval)) + (set newval sconst16) + (set-subreg-gr HI (regno Rd) newval) + (setf-move HI newval)) +) + +(dni-c-SI + movecdr "move.d [PC+],R" + "move.d ${const32},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_DWORD (f-source 15) const32) + (sequence + ((SI newval)) + (set newval const32) + (set Rd newval) + (setf-move SI newval)) +) + +; (MOVS.z [PC+],Rd [ Rd | 1100011z | 1111 ]) +; Similarly, no likely net improvement for a dni-c-bw. +(dni-c-QI + movscbr "movs.b [PC+],R" + "movs.b ${sconst8},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_BYTE (f-source 15) sconst8) + (sequence + ((SI newval)) + ; FIXME: Make trunc unnecessary. + (set newval (ext SI (trunc QI sconst8))) + (set Rd newval) + (setf-move SI newval)) +) + +(dni-c-HI + movscwr "movs.w [PC+],R" + "movs.w ${sconst16},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_WORD (f-source 15) sconst16) + (sequence + ((SI newval)) + ; FIXME: Make trunc unnecessary. + (set newval (ext SI (trunc HI sconst16))) + (set Rd newval) + (setf-move SI newval)) +) + +; (MOVU.z [PC+],Rd [ Rd | 1100010z | 1111 ]) +(dni-c-QI + movucbr "movu.b [PC+],R" + "movu.b ${uconst8},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_BYTE (f-source 15) uconst8) + (sequence + ((SI newval)) + ; FIXME: Make trunc unnecessary. + (set newval (zext SI (trunc QI uconst8))) + (set Rd newval) + (setf-move SI newval)) +) + +(dni-c-HI + movucwr "movu.w [PC+],R" + "movu.w ${uconst16},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_WORD (f-source 15) uconst16) + (sequence + ((SI newval)) + ; FIXME: Make trunc unnecessary. + (set newval (zext SI (trunc HI uconst16))) + (set Rd newval) + (setf-move SI newval)) +) + +; ADDQ j,Rd [ Rd | 001000 | j ] +(dni-cdt + addq "addq j,Rd" + "addq $j,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_ADDQ j) + (cris-arit add SI Rd j) +) + +; SUBQ j,Rd [ Rd | 001010| j ] +(dni-cdt + subq "subq j,Rd" + "subq $j,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_SUBQ j) + (cris-arit sub SI Rd j) +) + +; Convenience macros for insns with a memory operand. +(define-pmacro + (dni-cmt-attr-tim name comment attr syntax fmt semantics timing) + "dni with memory-access" + (dni name comment attr syntax + ; Specifying MODE_INDIRECT and MODE_AUTOINCREMENT in this + ; manner makes the autoincrementness handily available. + ; It also effectively excludes non-memory use of dni-cmt. + (.splice (.unsplice fmt) MODEMEMP_YES inc) + semantics + timing) +) + +(define-pmacro (dni-cmt-attr name comment attr syntax fmt semantics) + "dni with read memory-access timing" + (dni-cmt-attr-tim name comment attr syntax fmt semantics + (cris-mem-timing)) +) + +(define-pmacro (dni-cmwt-attr name comment attr syntax fmt semantics) + "dni with write memory-access timing" + (dni-cmt-attr-tim name comment attr syntax fmt semantics + (cris-mem-write-timing)) +) + +(define-pmacro QI-size 1) +(define-pmacro HI-size 2) +(define-pmacro SI-size 4) + +(define-pmacro (cris-get-mem size regop) + "Handle reading memory in , with source address register\ + (read once, maybe set once) in or prefixed" + (sequence + size + ((SI addr) (size tmp-mem) (BI postinc)) + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; Get the address from somewhere. + (set addr + (if SI (eq prefix-set 0) + ; If the insn was prefixed, it's in the prefix-register. + regop + prefixreg)) + + ; Get the memory contents. + (set tmp-mem (mem size addr)) + + ; For non-prefixed post-increment, we increment the address by the + ; size of the memory access. + (if (ne postinc 0) + (sequence + () + (if (eq prefix-set 0) + (set addr (add addr (.sym size -size)))) + ; Update the source-register for post-increments. + (set regop addr))) + + ; Don't forget the return-value. + tmp-mem) +) + +(define-pmacro (cris-set-mem size regop value) + "Handle writing of to memory, with memory address register\ + (read once, maybe set once) in or prefixed." + (sequence + ((SI addr) (BI postinc)) + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; Get the address from somewhere. + (set addr + (if SI (eq prefix-set 0) + ; If the insn was prefixed, it's in the prefix-register. + regop + prefixreg)) + + ; Set the memory contents. Integral-write semantics apply. + ; FIXME: currently v32 only; when proper semantics needed, fix v10. + (if (andif current-mach-is-v32 (ne xbit 0)) + (if (eq pbit 0) + (sequence + () + (set (mem size addr) value) + ; Write failures are signalled (by whatever entity "sends + ; the signal") by setting P at time of the write above, if X + ; is set. Here, we just need to copy P into C. + (set cbit pbit)) + (set cbit 1)) + (set (mem size addr) value)) + + ; For non-prefixed post-increment, we increment the address by the + ; size of the memory access. As for the integral-write, this needs to + ; be tweaked for pre-v32: increment should have been performed if + ; there's a fault at the memory access above. + (if (ne postinc 0) + (sequence + () + (if (eq prefix-set 0) + (set addr (add addr (.sym size -size)))) + ; Update the source-register for post-increments. + (set regop addr)))) +) + +(define-pmacro + (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem timing) + "Core generator macro for insns with .b, .w and .d variants\ + and a memory operand." + (begin + (dni-cmt-attr-tim + (.sym name .b-m) + (.str "byte mem " comment) + attr + (.str name ".b " syntax) + (.splice (.unsplice fmt) SIZE_BYTE) + (fsem QI) + timing) + (dni-cmt-attr-tim + (.sym name .w-m) + (.str "word mem " comment) + attr + (.str name ".w " syntax) + (.splice (.unsplice fmt) SIZE_WORD) + (fsem HI) + timing) + (dni-cmt-attr-tim + (.sym name .d-m) + (.str "dword mem " comment) + attr + (.str name ".d " syntax) + (.splice (.unsplice fmt) SIZE_DWORD) + (fsem SI) + timing)) +) + +; Further refinement macros. +(define-pmacro (dni-cmt-bwd-attr name comment attr syntax fmt fsem) + (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem + (cris-mem-timing)) +) + +(define-pmacro (dni-cmwt-bwd name comment syntax fmt fsem) + (dni-cmt-bwd-attr-tim name comment () syntax fmt fsem + (cris-mem-write-timing)) +) + +(define-pmacro (dni-cmt-bwd name comment syntax fmt fsem) + (dni-cmt-bwd-attr name comment () syntax fmt fsem) +) + +(define-pmacro (dni-cmt-sbw name comment syntax fmt fsem) + "Core generator macro for insns with .b and .w variants\ + and a signed memory operand." + (begin + (dni-cmt-attr + (.sym name .b-m) (.str "byte mem " comment) + () + (.str name ".b " syntax) + (.splice (.unsplice fmt) SIGNED_BYTE) + (fsem QI)) + (dni-cmt-attr + (.sym name .w-m) (.str "word mem " comment) + () + (.str name ".w " syntax) + (.splice (.unsplice fmt) SIGNED_WORD) + (fsem HI))) +) + +(define-pmacro (dni-cmt-ubw name comment syntax fmt fsem) + "Core generator macro for insns with .b and .w variants\ + and an unsigned memory operand." + (begin + (dni-cmt-attr + (.sym name .b-m) (.str "byte mem " comment) + () + (.str name ".b " syntax) + (.splice (.unsplice fmt) UNSIGNED_BYTE) + (fsem QI)) + (dni-cmt-attr + (.sym name .w-m) (.str "word mem " comment) + () + (.str name ".w " syntax) + (.splice (.unsplice fmt) UNSIGNED_WORD) + (fsem HI))) +) + +; CMP.m Rs,Rd [ Rd | 011011mm | Rs ] +(dni-cdt-bwd + cmp-r "compare register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_CMP Rs) + (.pmacro + (BWD) + (cris-arit6-int + sub BWD (.pmacro (sz regno val) (nop)) 0 + Rd Rs cbit cbit)) +) + +; CMP.m [Rs],Rd [ Rd | 101011mm | Rs ] +; CMP.m [Rs+],Rd [ Rd | 111011mm | Rs ] +(dni-cmt-bwd + cmp-m "compare memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_CMP Rs Rd) + (.pmacro + (BWD) + (cris-arit6-int + sub BWD (.pmacro (sz regno val) (nop)) 0 + Rd (cris-get-mem BWD Rs) cbit cbit)) +) + +; (CMP.m [PC+],Rd [ Rd | 111011mm | 1111 ]) +(dni-c-QI + cmpcbr "cmp constant byte to register" + "cmp.b $sconst8,$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_BYTE (f-source 15) sconst8) + (cris-arit6-int + sub QI (.pmacro (sz regno val) (nop)) 0 + Rd (trunc QI sconst8) cbit cbit) +) + +(dni-c-HI + cmpcwr "cmp constant word to register" + "cmp.w $sconst16,$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_WORD (f-source 15) sconst16) + (cris-arit6-int + sub HI (.pmacro (sz regno val) (nop)) 0 + Rd (trunc HI sconst16) cbit cbit) +) + +(dni-c-SI + cmpcdr "cmp constant dword to register" + "cmp.d $const32,$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_DWORD (f-source 15) const32) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd const32 cbit cbit) +) + +; CMPQ i,Rd [ Rd | 001011 | i ] +(dni-cdt + cmpq "cmpq i,Rd" + "cmpq $i,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_CMPQ i) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd i cbit cbit) +) + +; CMPS.z [Rs],Rd [ Rd | 1000111z | Rs ] +; CMPS.z [Rs+],Rd [ Rd | 1100111z | Rs ] +(dni-cmt-sbw + cmps-m "cmp sign-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_CMPX Rs) + (.pmacro + (BW) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit)) +) + +; (CMPS.z [PC+],Rd [ Rd | 1100111z | 1111 ]) +(dni-c-QI + cmpscbr "cmp sign-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_BYTE (f-source 15) sconst8) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd (ext SI (trunc QI sconst8)) cbit cbit) +) +(dni-c-HI + cmpscwr "cmp sign-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_WORD (f-source 15) sconst16) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd (ext SI (trunc HI sconst16)) cbit cbit) +) + +; CMPU.z [Rs],Rd [ Rd | 1000110z | Rs ] +; CMPU.z [Rs+],Rd [ Rd | 1100110z | Rs ] +(dni-cmt-ubw + cmpu-m "cmp zero-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_CMPX Rs) + (.pmacro + (BW) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit)) +) + +; (CMPU.z [PC+],Rd [ Rd | 1100110z | 1111 ]) +(dni-c-QI + cmpucbr "cmp zero-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_BYTE (f-source 15) uconst8) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd (zext SI (trunc QI uconst8)) cbit cbit) +) +(dni-c-HI + cmpucwr "cmp zero-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_WORD (f-source 15) uconst16) + (cris-arit6-int + sub SI (.pmacro (sz regno val) (nop)) 0 + Rd (zext SI (trunc HI uconst16)) cbit cbit) +) + +; MOVE.m [Rs],Rd [ Rd | 101001mm | Rs ] +; MOVE.m [Rs+],Rd [ Rd | 111001mm | Rs ] +(dni-cmt-bwd + move-m "move from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_MOVE_M_R Rs Rd) + (.pmacro + (BWD) + (sequence + ((SI tmp)) + (set tmp (cris-get-mem BWD Rs)) + (set-subreg-gr + BWD + (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) + tmp) + (setf-move BWD tmp))) +) + +; MOVS.z [Rs],Rd [ Rd | 1000011z | Rs ] +; MOVS.z [Rs+],Rd [ Rd | 1100011z | Rs ] +(dni-cmt-sbw + movs-m "movs from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_MOVX Rs Rd) + (.pmacro + (BW) + (sequence + ((SI tmp)) + (set tmp (ext SI (cris-get-mem BW Rs))) + (if (andif prefix-set (not inc)) + (set Rs tmp) + (set Rd tmp)) + (setf-move SI tmp))) +) + +; MOVU.z [Rs],Rd [ Rd | 1000010z | Rs ] +; MOVU.z [Rs+],Rd [ Rd | 1100010z | Rs ] +(dni-cmt-ubw + movu-m "movu from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_MOVX Rs Rd) + (.pmacro + (BW) + (sequence + ((SI tmp)) + (set tmp (zext SI (cris-get-mem BW Rs))) + (if (andif prefix-set (not inc)) + (set Rs tmp) + (set Rd tmp)) + (setf-move SI tmp))) +) + +; MOVE Rs,Pd [ Pd | 01100011 | Rs ] +(.splice + begin + (.unsplice + (.map + (.pmacro + (VER) + (dni + (.sym move-r-spr VER) + "Move from general register to special register" + ((MACH (.sym cris VER))) + "move ${Rs},${Pd}" + (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd) + (sequence + ((SI tmp) (SI rno)) + (set tmp Rs) + (set rno (regno Pd)) + (cond + ; See reg-sr setter for most of the special-register semantics. + ; The sanity check for known read-only registers is for program + ; debug help; the real insn would be harmless and have no effect. + ; CGEN-FIXME: regno of symbolic h-sr names doesn't work here. + ((orif (orif (eq rno 0) (eq rno 1)) (orif (eq rno 4) (eq rno 8))) + (error "move-r-spr: trying to set a read-only special register")) + (else (set Pd tmp))) + (reset-x-p)) + (cris-reg-sr-timing))) + (cris-cpu-models))) +) + +(define-pmacro (dni-cdt-ver-attr name comment fattr syntax fmt fsem) + "Generator for each MACH, using default timing." + (.splice + begin + (.unsplice + (.map + (.pmacro (v) (dni-cdt-attr name comment (fattr v) syntax fmt (fsem v))) + (cris-cpu-models)))) +) + +; MOVE Ps,Rd [ Ps | 01100111 | Rd ] +; Note that in the insn format, the Rd operand is in the Rs field (the +; Rd field by the definition used everywhere else is the Ps position in +; this insn). +; It gets a little weird here because we can't get this insn into a +; define-pmacro unless we make named pmacros for e.g. a separate attr +; function and a semantics function: a .pmacro can't refer to the +; parameters of the outer define-pmacro. (The manual refers to this as +; not implementing "lexical scoping"). +(.splice + begin + (.unsplice + (.map + (.pmacro + (VER) + (dni-cdt-attr + (.sym move-spr-r VER) + "Move from special register to general register" + ((MACH (.sym cris VER))) + "move ${Ps},${Rd-sfield}" + (+ Ps RFIX_MOVE_S_R MODE_REGISTER SIZE_FIXED Rd-sfield) + (sequence + ((SI grno) (SI prno) (SI newval)) + (set prno (regno Ps)) + ; CGEN-FIXME: Can't use the following and then "grno" below because + ; CGEN will emit a "tmp_grno" *also* in decodev32.c:crisv32f_decode + ; (set grno (regno Rd-sfield)) + (set newval Ps) + (.splice + cond + (.unsplice + (.map + (.pmacro + (r) + ((eq prno (.cadr2 r)) + (set-subreg-gr (.car2 r) (regno Rd-sfield) newval))) + ((.sym cris-implemented-readable-specregs- VER)))) + (else (error "move-spr-r from unimplemented register"))) + (reset-x-p)))) + (cris-cpu-models))) +) + +; MOVE Ps,PC [ Ps | 01100111 | 1111 ] +; The move-special-register-to-pc insns are return-type instructions and +; have to be special-cased to get the delay-slot and avoid being indicated +; as invalid. +(dni-cdt-attr + ret-type + "ret-type" + (MACH-PC) + "ret/reti/retb" + (+ Ps MODE_REGISTER RFIX_MOVE_S_R SIZE_FIXED (f-source 15)) + (sequence + ((SI retaddr)) + (set retaddr Ps) + (reset-x-p) + (delay 1 (set pc retaddr))) +) + +; MOVE [Rs],Pd [ Pd | 10100011 | Rs ] +; MOVE [Rs+],Pd [ Pd | 11100011 | Rs ] +; We make variants that loads constants or memory for each MACH version, +; since each consider some subset of the "special registers" to have +; different sizes. FIXME: Should be able to simplify this. +(.splice + begin + (.unsplice + (.map + (.pmacro + (VER) + (dni + (.sym move-m-spr VER) + "Move from memory to special register" + ((MACH (.sym cris VER))) + "move [${Rs}${inc}],${Pd}" + (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs) + (sequence + ((SI rno) (SI newval)) + (set rno (regno Pd)) + (.splice + cond + ; No sanity check for constant special register here, since the + ; memory read side-effect or post-increment may be the goal, or + ; for pre-v32 a prefix assignment side-effect. + (.unsplice + (.map + (.pmacro + (r) + ((eq rno (.cadr2 r)) + (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs))))) + ((.sym cris-implemented-writable-specregs- VER)))) + (else (error "Trying to set unimplemented special register"))) + (set Pd newval) + (reset-x-p)) + (cris-mem-sr-timing))) + (cris-cpu-models))) +) + +(define-pmacro QI-operand sconst8) +(define-pmacro HI-operand sconst16) +(define-pmacro SI-operand const32) + +(define-pmacro + (cris-move-c-spr VER VERFN) + "Generator for loading constant into special register" + (.splice + begin + (.unsplice + (.map + (.pmacro + (srdef v) + (dni + (.sym move-c-spr v -p (.cadr2 srdef)) + (.str "Move constant to special register p" (.cadr2 srdef)) + ((MACH (.sym cris v))) + (.str "move ${" (.sym (.car2 srdef) -operand) "},${Pd}") + ; We use Pd in semantics without naming it in the format (which + ; would CGEN-FIXME: cause a CGEN error for some reason, likely + ; related to specifying an insn field multiple times). This + ; currently works and is guarded with test-cases (specifically + ; wrt. the timing model) but may need to be tweaked in the future. + ; Note that using instead (ifield f-dest) causes incorrect timing + ; model to be generated; the timing model requires that Pd is set. + (+ (f-dest (.cadr2 srdef)) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED + (f-source 15) (.sym (.car2 srdef) -operand)) + (sequence + () + (set Pd (.sym (.car2 srdef) -operand)) ; (reg h-sr (.cadr2 srdef)) + (reset-x-p)) + ((.sym cris-timing-const-sr- (.car2 srdef))))) + ((.sym cris-implemented-specregs-const- VER)) + (.map VERFN ((.sym cris-implemented-specregs-const- VER)))))) +) + +; CGEN-FIXME: +; Unfortunately we can't iterate over the list of models due to the +; problem with referring to the parameters of a surrounding pmacro from +; within an enclosed .pmacro (perhaps related to "lexical scoping"). +; We get e.g. 'insn already defined:: (move-c-sprvn-p0)' with this: +;(.splice +; begin (.unsplice (.map (.pmacro (vn) (cris-move-c-spr vn (.pmacro (x) vn))) +; (cris-cpu-models))) +;) +(cris-move-c-spr v0 (.pmacro (x) v0)) +(cris-move-c-spr v3 (.pmacro (x) v3)) +(cris-move-c-spr v8 (.pmacro (x) v8)) +(cris-move-c-spr v10 (.pmacro (x) v10)) +(cris-move-c-spr v32 (.pmacro (x) v32)) + +; MOVE Ps,[Rd] [ Ps | 10100111 | Rd ] +; MOVE Ps,[Rd+] [ Ps | 11100111 | Rd ] +(.splice + begin + (.unsplice + (.map + (.pmacro + (VER) + (dni-cmwt-attr + (.sym move-spr-m VER) + "Move from special register to memory" + ((MACH (.sym cris VER))) + "move ${Ps},[${Rd-sfield}${inc}]" + (+ INFIX_MOVE_S_M SIZE_FIXED Rd-sfield Ps) + (sequence + ((SI rno)) + (set rno (regno Ps)) + (.splice + cond + (.unsplice + (.map + (.pmacro + (r) + ((eq rno (.cadr2 r)) + (cris-set-mem (.car2 r) Rd-sfield Ps))) + ((.sym cris-implemented-readable-specregs- VER)))) + (else (error "write from unimplemented special register"))) + (reset-x-p)))) + (cris-cpu-models))) +) + +; SBFS [Rs(+)] +; Instruction format: |0 0 1 1 1 m 1 1 0 1 1 1| Dest. | +(dni-cdt-attr + sbfs + "sbfs" + ((MACH crisv10)) + "sbfs [${Rd-sfield}${inc}]" + (+ (f-dest 3) INFIX_SBFS SIZE_FIXED MODEMEMP_YES inc Rd-sfield) + (error "SBFS isn't implemented") +) + +; MOVE Ss,Rd [ Ss | 11110111 | Rd ] +(dni-cdt-attr + move-ss-r + "move from support register to general register" + (MACH-V32) + "move ${Ss},${Rd-sfield}" + (+ Ss INFIX_MOVE_SS SIZE_FIXED (f-mode 3) Rd-sfield) + (sequence + () + (set Rd-sfield Ss) + (reset-x-p)) +) + +; MOVE Rs,Sd [ Sd | 10110111 | Rs ] +(dni-cdt-attr + move-r-ss + "move from general register to support register" + (MACH-V32) + "move ${Rs},${Sd}" + (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs) + (sequence + () + (set Sd Rs) + (reset-x-p)) +) + +; MOVEM Rs,[Rd] [ Rs | 10111111 | Rd ] +; MOVEM Rs,[Rd+] [ Rs | 11111111 | Rd ] + +(define-pmacro (movem-to-mem-step regn) + ; Without the SI attribute, UINT is generated, which isn't supported by + ; the sim framework. + (if (ge SI (regno Rs-dfield) regn) + (sequence + ((SI tmp)) + (set tmp (reg h-gr regn)) + (set (mem SI addr) tmp) + (set addr (add addr 4)))) +) + +(dni + movem-r-m + "movem to memory" + (MACH-PRE-V32) + "movem ${Rs-dfield},[${Rd-sfield}${inc}]" + (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) + (sequence + ((SI addr) (BI postinc)) + ; FIXME: A copy of what's in cris-get-mem. + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; CGEN-FIXME: Kludge to work around a CGEN bug: it doesn't see that + ; Rs-dfield is used as an input, causing the timing model to be wrong. + (sequence ((SI dummy)) (set dummy Rs-dfield)) + + ; Get the address from somewhere. If the insn was prefixed, it's in + ; the prefix-register. + (set addr + (if SI (eq prefix-set 0) + Rd-sfield + prefixreg)) + + (.splice + sequence () + (.unsplice (.map movem-to-mem-step (.iota 16 15 -1)))) + + ; Update the source-register for post-increments. + (if (ne postinc 0) + (set Rd-sfield + (if SI (eq prefix-set 0) addr prefixreg))) + (reset-x-p)) + (simplecris-movem-timing) +) + +(dni + movem-r-m-v32 + "movem to memory" + (MACH-V32) + "movem ${Rs-dfield},[${Rd-sfield}${inc}]" + (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) + (sequence + ((SI addr) (BI postinc)) + ; FIXME: Mostly a copy of what's in cris-get-mem. + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; CGEN-FIXME: See movem-r-m. + (sequence ((SI dummy)) (set dummy Rs-dfield)) + + (set addr Rd-sfield) + + (.splice + sequence () + (.unsplice (.map movem-to-mem-step (.iota 16)))) + + ; Update the source-register for post-increments. + (if (ne postinc 0) + (set Rd-sfield addr)) + (reset-x-p)) + ; Unit u-mem must be specified before the u-movem-* for memory address + ; register stall count to be right. + ((crisv32 (unit u-mem) (unit u-movem-rtom) (unit u-exec-movem) + (unit u-mem-w))) +) + +; MOVEM [Rs],Rd [ Rd | 10111011 | Rs ] +; MOVEM [Rs+],Rd [ Rd | 11111011 | Rs ] + +(define-pmacro + (movem-to-reg-step regn) + ; Without the SI attribute, UINT is generated, which isn't supported by + ; the sim framework. + (if (ge SI (regno Rd) regn) + (sequence + ((SI tmp)) + (set tmp (mem SI addr)) + (set (reg h-gr regn) tmp) + (set addr (add addr 4)))) +) + +(dni + movem-m-r + "movem to register" + (MACH-PRE-V32) + "movem [${Rs}${inc}],${Rd}" + (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs) + (sequence + ((SI addr) (BI postinc)) + ; FIXME: Mostly a copy of what's in cris-get-mem. + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; Get the address from somewhere. If the insn was prefixed, it's in + ; the prefix-register. + (set addr + (if SI (eq prefix-set 0) + Rs + prefixreg)) + + ; CGEN-FIXME: See movem-r-m. + (sequence ((SI dummy)) (set dummy Rd)) + + (.splice + sequence () + ; The first movem step is left out because it can't happen; it's for + ; PC destination. See the pattern below. + (.unsplice (.map movem-to-reg-step (.iota 15 14 -1)))) + + ; Update the source-register for post-increments. + ; FIXME: No postinc-prefixed for v0 IIRC. + (if (ne postinc 0) + (set Rs (if SI (eq prefix-set 0) addr prefixreg))) + (reset-x-p)) + (simplecris-movem-timing) +) + +; (MOVEM [Rs],PC [ 1111 | 10111011 | Rs ]) +; (MOVEM [Rs+],PC [ 1111 | 11111011 | Rs ]) +; We have to special-case it for PC destination; used in longjump. +; We shouldn't *have* to special-case it; the main reason is (FIXME:) +; misgeneration of the simulator when the PC case is folded into the +; generic PRE-V32 movem; possibly related to then being a COND-CTI rather +; than an UNCOND-CTI. +(dni-cmt-attr + movem-m-pc + "movem to register, ending with PC" + (MACH-PRE-V32) + "movem [${Rs}${inc}],${Rd}" + (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs) + (sequence + ((SI addr) (BI postinc)) + ; FIXME: Mostly a copy of what's in cris-get-mem. + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; Get the address from somewhere. If the insn was prefixed, it's in + ; the prefix-register. + (set addr + (if SI (eq prefix-set 0) + Rs + prefixreg)) + + ; FIXME: Add kludge here too *and* a test-case. + + (.splice + sequence () + ; The first movem step is for PC destination, used in longjmp. + (set pc (mem SI addr)) + (set addr (add addr 4)) + (.unsplice + (.map + (.pmacro + (regn) + (sequence + ((SI tmp)) + (set tmp (mem SI addr)) + (set (reg h-gr regn) tmp) + (set addr (add addr 4)))) + (.iota 15 14 -1)))) + + ; Update the source-register for post-increments. + ; FIXME: No postinc-prefixed for v0. + (if (ne postinc 0) + (set Rs (if SI (eq prefix-set 0) addr prefixreg))) + (reset-x-p)) +) + +(dni + movem-m-r-v32 + "movem to register" + (MACH-V32) + "movem [${Rs}${inc}],${Rd}" + (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd) + (sequence + ((SI addr) (BI postinc)) + ; FIXME: A copy of what's in cris-get-mem + + ; Cache the incrementness of the operand. + (set postinc inc) + + ; Get the address from somewhere. + (set addr Rs) + + ; CGEN-FIXME: See movem-r-m. + (sequence ((SI dummy)) (set dummy Rd)) + + (.splice + sequence () + (.unsplice (.map movem-to-reg-step (.iota 16)))) + + ; Update the source-register for post-increments. + ; FIXME: No postinc-prefixed for v0 IIRC. + (if (ne postinc 0) + (set Rs addr)) + (reset-x-p)) + ; u-mem must be specified before the u-movem-* for memory source + ; register stall count to be right. + ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-movem-mtor) + (unit u-exec-movem))) +) + +; ADD.m Rs,Rd [ Rd | 011000mm | Rs ] +(dni-cdt-bwd + add "add from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_ADD Rs) + (.pmacro (BWD) (cris-arit add BWD Rd Rs)) +) + +; ADD.m [Rs],Rd [ Rd | 101000mm | Rs ] +; ADD.m [Rs+],Rd [ Rd | 111000mm | Rs ] +(dni-cmt-bwd + add-m "add from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_ADD Rs Rd) + (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs)) +) +; (ADD.m [PC+],Rd [ Rd | 111000mm | 1111 ]) +(dni-c-QI + addcbr "add constant byte to register" + "add.b ${sconst8}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_BYTE (f-source 15) sconst8) + (cris-arit add QI Rd sconst8) +) + +(dni-c-HI + addcwr "add constant word to register" + "add.w ${sconst16}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_WORD (f-source 15) sconst16) + (cris-arit add HI Rd sconst16) +) + +(dni-c-SI + addcdr "add constant dword to register" + "add.d ${const32}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) + (cris-arit add SI Rd const32) +) + +; (ADD.D [PC+],PC [ 1111 | 11100010 | 1111 ]) +; This insn is used for DSO-local jumps in PIC code. +(dni + addcpc "Relative jump by adding constant to PC" + (MACH-PC) + "add.d ${sconst32},PC" + (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) + (sequence + ((SI newpc) (SI oldpc) (SI offs)) + (set offs const32) + (set oldpc (add SI pc 6)) + (set newpc (add SI oldpc offs)) + (set pc newpc) + (setf-arit SI add oldpc offs newpc cbit)) + (simplecris-common-timing ((unit u-const32) (unit u-stall) (unit u-exec))) +) + +; ADDS.z Rs,Rd [ Rd | 0100001z | Rs ] +(dni-cdt-sbw + adds "add sign-extended from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_ADDX Rs) + (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs)))) +) + +; ADDS.z [Rs],Rd [ Rd | 1000001z | Rs ] +; ADDS.z [Rs+],Rd [ Rd | 1100001z | Rs ] +(dni-cmt-sbw + adds-m "add sign-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_ADDX Rs) + (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) +) + +; (ADDS.z [PC+],Rd [ Rd | 1100001z | 1111 ]) +(dni-c-QI + addscbr "add sign-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_BYTE (f-source 15) sconst8) + (cris-arit add SI Rd (ext SI (trunc QI sconst8))) +) +(dni-c-HI + addscwr "add sign-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_WORD (f-source 15) sconst16) + (cris-arit add SI Rd (ext SI (trunc HI sconst16))) +) + +; (ADDS.w [],PC [ 1111 | 10000011 | 1111 ]) +; For a PC destination, we support only the two-operand case +; (dest == src), which is used in switch/case statements. +; FIXME: Should implement ADD.D [PC],PC and ADDS.B [PC],PC for use if/when +; implementing CASE_VECTOR_SHORTEN_MODE. +(dni + addspcpc "add sign-extended prefixed arg to PC" + (MACH-PC) + "adds.w [PC],PC" + (+ (f-dest 15) MODE_INDIRECT INDIR_ADDX SIGNED_WORD (f-source 15)) + (sequence + ((SI newpc) (SI oldpc) (HI offs)) + (if (not prefix-set) + (error "Unexpected adds.w [PC],PC without prefix")) + ; We don't use cris-get-mem but instead special-case this one, since we + ; have most instruction fields fixed where cris-get-mem expects + ; field-parametrization by certain names. + (set offs (mem HI prefixreg)) + (set oldpc (add SI pc 2)) + (set newpc (add SI oldpc offs)) + (set pc newpc) + (setf-arit SI add oldpc (ext SI offs) newpc cbit)) + (simplecris-common-timing ((unit u-mem) (unit u-stall) (unit u-exec))) +) + +; ADDU.z Rs,Rd [ Rd | 0100000z | Rs ] +(dni-cdt-ubw + addu "add zero-extended from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_ADDX Rs) + (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs)))) +) + +; ADDU.z [Rs],Rd [ Rd | 1000000z | Rs ] +; ADDU.z [Rs+],Rd [ Rd | 1100000z | Rs ] +(dni-cmt-ubw + addu-m "add zero-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_ADDX Rs) + (.pmacro (BW) + (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) +) + +; (ADDU.z [PC+],Rd [ Rd | 1100000z | 1111 ]) +(dni-c-QI + adducbr "add zero-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_BYTE (f-source 15) sconst8) + (cris-arit add SI Rd (zext SI (trunc QI sconst8))) +) +(dni-c-HI + adducwr "add zero-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_WORD (f-source 15) sconst16) + (cris-arit add SI Rd (zext SI (trunc HI sconst16))) +) + +; SUB.m Rs,Rd [ Rd | 011010mm | Rs ] +(dni-cdt-bwd + sub "subtract from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_SUB Rs) + (.pmacro (BWD) (cris-arit sub BWD Rd Rs)) +) + +; SUB.m [Rs],Rd [ Rd | 101010mm | Rs ] +; SUB.m [Rs+],Rd [ Rd | 111010mm | Rs ] +(dni-cmt-bwd + sub-m "subtract from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_SUB Rs Rd) + (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs)) +) + +; (SUB.m [PC+],Rd [ Rd | 111010mm | 1111 ] +(dni-c-QI + subcbr "subtract constant byte from register" + "sub.b ${sconst8}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_BYTE (f-source 15) sconst8) + (cris-arit sub QI Rd sconst8) +) + +(dni-c-HI + subcwr "subtract constant word from register" + "sub.w ${sconst16}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_WORD (f-source 15) sconst16) + (cris-arit sub HI Rd sconst16) +) + +(dni-c-SI + subcdr "subtract constant dword from register" + "sub.d ${const32}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_DWORD (f-source 15) const32) + (cris-arit sub SI Rd const32) +) + +; SUBS.z Rs,Rd [ Rd | 0100101z | Rs ] +(dni-cdt-sbw + subs "sub sign-extended from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_SUBX Rs) + (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs)))) +) + +; SUBS.z [Rs],Rd [ Rd | 1000101z | Rs ] +; SUBS.z [Rs+],Rd [ Rd | 1100101z | Rs ] +(dni-cmt-sbw + subs-m "sub sign-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_SUBX Rs) + (.pmacro (BW) + (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) +) + +; (SUBS.z [PC+],Rd [ Rd | 1100101z | 1111 ]) +(dni-c-QI + subscbr "sub sign-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_BYTE (f-source 15) sconst8) + (cris-arit sub SI Rd (ext SI (trunc QI sconst8))) +) +(dni-c-HI + subscwr "sub sign-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_WORD (f-source 15) sconst16) + (cris-arit sub SI Rd (ext SI (trunc HI sconst16))) +) + +; SUBU.z Rs,Rd [ Rd | 0100100z | Rs ] +(dni-cdt-ubw + subu "sub zero-extended from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_SUBX Rs) + (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs)))) +) + +; SUBU.z [Rs],Rd [ Rd | 1000100z | Rs ] +; SUBU.z [Rs+],Rd [ Rd | 1100100z | Rs ] +(dni-cmt-ubw + subu-m "sub zero-extended from memory to register" + "[${Rs}${inc}],$Rd" + (+ Rd INDIR_SUBX Rs) + (.pmacro (BW) + (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) +) + +; (SUBU.z [PC+],Rd [ Rd | 1100100z | 1111 ]) +(dni-c-QI + subucbr "sub zero-extended constant byte to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_BYTE (f-source 15) sconst8) + (cris-arit sub SI Rd (zext SI (trunc QI sconst8))) +) +(dni-c-HI + subucwr "sub zero-extended constant word to register" + "[${Rs}${inc}],$Rd" + (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_WORD (f-source 15) sconst16) + (cris-arit sub SI Rd (zext SI (trunc HI sconst16))) +) + +; ADDC Rs,Rd [ Rd | 01010111 | Rs ] +(dni-cdt-attr + addc-r "addc from register to register" + (MACH-V32) + "addc $Rs,$Rd" + (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs) + ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do + ; that, semantically. + (sequence + () + (set-quiet xbit 1) + (cris-arit add SI Rd Rs)) +) + +; ADDC [Rs],Rd [ Rd | 10011010 | Rs ] +; ADDC [Rs+],Rd [ Rd | 11011010 | Rs ] +(dni-cmt-attr + addc-m "addc from memory to register" + (MACH-V32) + "addc [${Rs}${inc}],${Rd}" + (+ Rd INDIR_ADDC SIZE_DWORD Rs) + (sequence + () + (set-quiet xbit 1) + (cris-arit add SI Rd (cris-get-mem SI Rs))) +) + +; (ADDC [Rs+],Rd [ Rd | 11011010 | 1111 ]) +(dni-c-SI-attr + addc-c "addc constant to register" + (MACH-V32) + "addc ${const32},${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_ADDC SIZE_DWORD (f-source 15) const32) + (sequence + () + (set-quiet xbit 1) + (cris-arit add SI Rd const32)) +) + +; LAPC [PC+],Rd [ Rd | 11010111 1111 ] +(dni-c-SI-attr + lapc-d "lapc.d" + (MACH-V32) + "lapc.d ${const32-pcrel},${Rd}" + (+ Rd MODE_AUTOINCREMENT INFIX_LAPC SIZE_FIXED (f-source 15) const32-pcrel) + (sequence + () + (set Rd const32-pcrel) + (reset-x-p)) +) + +; LAPCQ qo,Rd [ Rd | 10010111 | qo ] +(dni-cdt-attr + lapcq "lapcq" + (MACH-V32) + "lapcq ${qo},${Rd}" + (+ Rd MODE_INDIRECT INFIX_LAPC SIZE_FIXED qo) + (sequence + () + (set Rd qo) + (reset-x-p)) +) + +; ADDI Rs.m,Rd [ Rs | 010100mm | Rd ] +(dni-cdt-bwd + addi "addi" + "${Rs-dfield}.m,${Rd-sfield}" + (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield) + (.pmacro + (BWD) + (sequence + () + (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) + (reset-x-p))) +) + +; NEG.m Rs,Rd [ Rd | 010110mm | Rs ] +(dni-cdt-bwd + neg "neg.m Rs,Rd" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_NEG Rs) + (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs)) +) + +; TEST.m [Rs] [ 0000101110mm | Rs ] +; TEST.m [Rs+] [ 0000111110mm | Rs ] +(dni-cmt-bwd + test-m "test.m [Rs(+)]" + "[${Rs}${inc}]" + (+ (f-dest 0) INDIR_TEST Rs) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd (cris-get-mem BWD Rs)) + ; This is supposed to be the same result as for cmpq 0,X, hence same code. + (cris-arit6-int + sub BWD (.pmacro (sz regno val) (nop)) 0 tmpd 0 cbit cbit))) +) + +; MOVE.m Rs,[Rd] [ Rs | 101111mm | Rd ] +; MOVE.m Rs,[Rd+] [ Rs | 111111mm | Rd ] + +(dni-cmwt-bwd + move-r-m "move.m R,[]" + "${Rs-dfield},[${Rd-sfield}${inc}]" + (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd Rs-dfield) + (cris-set-mem BWD Rd-sfield tmpd) + (reset-x-p))) +) + +; MULS.m Rs,Rd [ Rd | 110100mm | Rs ] +(dni-bwd-attr + muls "muls.m Rs,Rd" + ((MACH crisv10,crisv32)) + "$Rs,$Rd" + (+ Rd MODE_MULS INDIR_MUL Rs) + (.pmacro + (BWD) + (sequence + ((DI src1) (DI src2) (DI tmpr)) + (set src1 (ext DI (trunc BWD Rs))) + (set src2 (ext DI (trunc BWD Rd))) + (set tmpr (mul src1 src2)) + (set Rd (trunc SI tmpr)) + (set mof (trunc SI (srl tmpr 32))) + (setf-arit DI muls src1 src2 tmpr cbit))) + ((crisv10 (unit u-multiply) (unit u-exec)) + (crisv32 (unit u-multiply) (unit u-exec))) +) + +; MULU.m Rs,Rd [ Rd | 100100mm | Rs ] +(dni-bwd-attr + mulu "mulu.m Rs,Rd" + ((MACH crisv10,crisv32)) + "$Rs,$Rd" + (+ Rd MODE_MULU INDIR_MUL Rs) + (.pmacro + (BWD) + (sequence + ((DI src1) (DI src2) (DI tmpr)) + (set src1 (zext DI (trunc BWD Rs))) + (set src2 (zext DI (trunc BWD Rd))) + (set tmpr (mul src1 src2)) + (set Rd (trunc SI tmpr)) + (set mof (trunc SI (srl tmpr 32))) + (setf-arit DI mulu src1 src2 tmpr cbit))) + ((crisv10 (unit u-multiply) (unit u-exec)) + (crisv32 (unit u-multiply) (unit u-exec))) +) + +; MCP Ps,Rd [ Ps | 01111111 | Rd ] +(dni-cdt-attr + mcp "Multiply Carry Propagation" + (MACH-V32) + "mcp $Ps,$Rd" + (+ Ps MODE_REGISTER RFIX_MCP SIZE_FIXED Rd-sfield) + (sequence + () + (set-quiet xbit 1) + (set-quiet zbit 1) + (cris-arit5 add SI Rd-sfield Rd-sfield Ps rbit rbit)) +) + +; MSTEP Rs,Rd [ Rd | 01111111 | Rs ] +(dni-cdt-attr + mstep "Multiply step" + (MACH-PRE-V32) + "mstep $Rs,$Rd" + (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs) + (sequence + ((SI tmpd) (SI tmps)) + (set tmps Rs) + (set tmpd (add (sll Rd 1) (if SI nbit tmps 0))) + (set Rd tmpd) + (setf-move SI tmpd)) +) + +; DSTEP Rs,Rd [ Rd | 01101111 | Rs ] +(dni-cdt + dstep "Division step" + "dstep $Rs,$Rd" + (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs) + (sequence + ((SI tmp) (SI tmps) (SI tmpd)) + (set tmps Rs) + (set tmp (sll Rd 1)) + (set tmpd (if SI (geu tmp tmps) (sub tmp tmps) tmp)) + (set Rd tmpd) + (setf-move SI tmpd)) +) + +; ABS Rs,Rd [ Rd | 01101011 | Rs ] +(dni-cdt + abs "Absolut Instruction" + "abs $Rs,$Rd" + (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs) + (sequence + ((SI tmpd)) + (set tmpd (abs Rs)) + (set Rd tmpd) + (setf-move SI tmpd)) +) + +; AND.m Rs,Rd [ Rd | 011100mm | Rs ] +(dni-cdt-bwd + and "And from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_AND Rs) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd (and BWD Rd Rs)) + (set-subreg-gr BWD (regno Rd) tmpd) + (setf-move BWD tmpd))) +) + +; AND.m [Rs],Rd [ Rd | 101100mm | Rs ] +; AND.m [Rs+],Rd [ Rd | 111100mm | Rs ] +(dni-cmt-bwd + and-m "And from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_AND Rs Rd) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd (and BWD Rd (cris-get-mem BWD Rs))) + (set-subreg-gr + BWD + (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) + tmpd) + (setf-move BWD tmpd))) +) + +; (AND.m [PC+],Rd [ Rd | 111100mm | 1111 ]) +(dni-c-QI + andcbr "And constant byte to register" + "and.b ${sconst8}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_BYTE (f-source 15) sconst8) + (sequence + ((QI tmpd)) + (set tmpd (and QI Rd sconst8)) + (set-subreg-gr QI (regno Rd) tmpd) + (setf-move QI tmpd)) +) + +(dni-c-HI + andcwr "And constant word to register" + "and.w ${sconst16}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_WORD (f-source 15) sconst16) + (sequence + ((HI tmpd)) + (set tmpd (and HI Rd sconst16)) + (set-subreg-gr HI (regno Rd) tmpd) + (setf-move HI tmpd)) +) + +(dni-c-SI + andcdr "And constant dword to register" + "and.d ${const32}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_DWORD (f-source 15) const32) + (sequence + ((SI tmpd)) + (set tmpd (and SI Rd const32)) + (set-subreg-gr SI (regno Rd) tmpd) + (setf-move SI tmpd)) +) + +; ANDQ i,Rd [ Rd | 001100 | i ] +(dni-cdt + andq "And quick-immediate to register" + "andq $i,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_ANDQ i) + (sequence + ((SI tmpd)) + (set tmpd (and SI Rd i)) + (set-subreg-gr SI (regno Rd) tmpd) + (setf-move SI tmpd)) +) + +; OR.m Rs,Rd [ Rd | 011101mm | Rs ] +(dni-cdt-bwd + orr "Or from register to register" + "$Rs,$Rd" + (+ Rd MODE_REGISTER R_OR Rs) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd (or BWD Rd Rs)) + (set-subreg-gr BWD (regno Rd) tmpd) + (setf-move BWD tmpd))) +) + +; OR.m [Rs],Rd [ Rd | 101101mm | Rs ] +; OR.m [Rs+],Rd [ Rd | 111101mm | Rs ] +(dni-cmt-bwd + or-m "Or from memory to register" + "[${Rs}${inc}],${Rd}" + (+ INDIR_OR Rs Rd) + (.pmacro + (BWD) + (sequence + ((BWD tmpd)) + (set tmpd (or BWD Rd (cris-get-mem BWD Rs))) + (set-subreg-gr + BWD + (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) + tmpd) + (setf-move BWD tmpd))) +) + +; (OR.m [PC+],Rd [ Rd | 111101mm | 1111 ]) +(dni-c-QI + orcbr "Or constant byte to register" + "or.b ${sconst8}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_BYTE (f-source 15) sconst8) + (sequence + ((QI tmpd)) + (set tmpd (or QI Rd sconst8)) + (set-subreg-gr QI (regno Rd) tmpd) + (setf-move QI tmpd)) +) + +(dni-c-HI + orcwr "Or constant word to register" + "or.w ${sconst16}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_WORD (f-source 15) sconst16) + (sequence + ((HI tmpd)) + (set tmpd (or HI Rd sconst16)) + (set-subreg-gr HI (regno Rd) tmpd) + (setf-move HI tmpd)) +) + +(dni-c-SI + orcdr "Or constant dword to register" + "or.d ${const32}],${Rd}" + (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_DWORD (f-source 15) const32) + (sequence + ((SI tmpd)) + (set tmpd (or SI Rd const32)) + (set-subreg-gr SI (regno Rd) tmpd) + (setf-move SI tmpd)) +) + +; ORQ i,Rd [ Rd | 001101 | i ] +(dni-cdt + orq "Or quick-immediate to register" + "orq $i,$Rd" + (+ Rd MODE_QUICK_IMMEDIATE Q_ORQ i) + (sequence + ((SI tmpd)) + (set tmpd (or SI Rd i)) + (set-subreg-gr SI (regno Rd) tmpd) + (setf-move SI tmpd)) +) + +; XOR Rs,Rd [ Rd | 01111011 | Rs ] +(dni-cdt + xor "Xor from register to register" + "xor $Rs,$Rd" + (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs) + (sequence + ((SI tmpd)) + (set tmpd (xor SI Rd Rs)) + (set Rd tmpd) + (setf-move SI tmpd)) +) + +(define-pmacro (swap-r x) + "Perform bit-wise swap within each byte" + (sequence + SI + ((SI tmpr)) + (set tmpr x) + (or (sll (and tmpr #x1010101) 7) + (or (sll (and tmpr #x2020202) 5) + (or (sll (and tmpr #x4040404) 3) + (or (sll (and tmpr #x8080808) 1) + (or (srl (and tmpr #x10101010) 1) + (or (srl (and tmpr #x20202020) 3) + (or (srl (and tmpr #x40404040) 5) + (srl (and tmpr #x80808080) 7))))))))) +) + +(define-pmacro (swap-b x) + "Perform byte-wise swap within each word" + (sequence + SI + ((SI tmpb)) + (set tmpb x) + (or (and (sll tmpb 8) #xff00ff00) + (and (srl tmpb 8) #xff00ff))) +) + +(define-pmacro (swap-w x) + "Perform word-wise swap within each dword" + (sequence + SI + ((SI tmpb)) + (set tmpb x) + (or (and (sll tmpb 16) #xffff0000) + (and (srl tmpb 16) #xffff))) +) + +(define-pmacro (swap-_ x) + "Do nothing swap-wise" + (error SI "SWAP without swap modifier isn't implemented") +) + +(define-pmacro (swap-n x) + "Perform bitwise not (that is, perform a not, not not perform)" + (inv x) +) + +(define-pmacro (swap-br x) "Combine swap-r and swap-b" (swap-r (swap-b x))) +(define-pmacro (swap-wr x) "Combine swap-r and swap-w" (swap-r (swap-w x))) +(define-pmacro (swap-wb x) "Combine swap-b and swap-w" (swap-b (swap-w x))) +(define-pmacro (swap-wbr x) "Combine swap-r and swap-wb" (swap-r (swap-wb x))) +(define-pmacro (swap-nr x) "Combine swap-r and swap-n" (swap-r (swap-n x))) +(define-pmacro (swap-nb x) "Combine swap-n and swap-b" (swap-b (swap-n x))) +(define-pmacro (swap-nbr x) "Combine swap-r and swap-nb" (swap-r (swap-nb x))) +(define-pmacro (swap-nw x) "Combine swap-n and swap-w" (swap-w (swap-n x))) +(define-pmacro (swap-nwr x) "Combine swap-r and swap-nw" (swap-r (swap-nw x))) +(define-pmacro (swap-nwb x) "Combine swap-b and swap-nw" (swap-b (swap-nw x))) +(define-pmacro (swap-nwbr x) "Combine swap-r and swap-nwb" (swap-r (swap-nwb x))) + +(define-pmacro (cris-swap swapcode val) + (sequence + SI + ((SI tmpcode) (SI tmpval) (SI tmpres)) + (set tmpcode swapcode) + (set tmpval val) + (.splice + cond + (.unsplice + (.map + (.pmacro + (x-swapcode x-swap) + ((eq tmpcode x-swapcode) + (set tmpres ((.sym swap- x-swap) tmpval)))) + (.iota 16) + (.splice _ (.unsplice cris-swap-codes))))) + tmpres) +) + +; NOT Rd alias for SWAPN Rd +(dni-cdt-attr + not "Not" + ((MACH crisv0,crisv3)) + "not ${Rs}" + (+ (f-dest 8) RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) + (sequence + ((SI tmp) (SI tmpd)) + (set tmp Rd-sfield) + (set tmpd (cris-swap 8 tmp)) + (set Rd-sfield tmpd) + (setf-move SI tmpd)) +) + +; SWAP