Change ARM vfp assembly functions to use unified syntax.

git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@138332 91177308-0d34-0410-b5e6-96231b3b80d8

34 files changed, 152 insertions, 118 deletions

diff --git a/lib/arm/adddf3vfp.S b/lib/arm/adddf3vfp.S
index cced1e09a..c90b0c2ea 100644
--- a/lib/arm/adddf3vfp.S
+++ b/lib/arm/adddf3vfp.S
@@ -15,10 +15,11 @@
 // Adds two double precision floating point numbers using the Darwin
 // calling convention where double arguments are passsed in GPR pairs
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__adddf3vfp)
-	fmdrr	d6, r0, r1		// move first param from r0/r1 pair into d6
-	fmdrr	d7, r2, r3		// move second param from r2/r3 pair into d7
-	faddd	d6, d6, d7		
-	fmrrd	r0, r1, d6		// move result back to r0/r1 pair
+	vmov	d6, r0, r1		// move first param from r0/r1 pair into d6
+	vmov	d7, r2, r3		// move second param from r2/r3 pair into d7
+	vadd.f64 d6, d6, d7		
+	vmov	r0, r1, d6		// move result back to r0/r1 pair
 	bx	lr
diff --git a/lib/arm/addsf3vfp.S b/lib/arm/addsf3vfp.S
index b747528de..43653d526 100644
--- a/lib/arm/addsf3vfp.S
+++ b/lib/arm/addsf3vfp.S
@@ -15,10 +15,11 @@
 // Adds two single precision floating point numbers using the Darwin
 // calling convention where single arguments are passsed in GPRs
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__addsf3vfp)
-	fmsr	s14, r0		// move first param from r0 into float register
-	fmsr	s15, r1		// move second param from r1 into float register
-	fadds	s14, s14, s15
-	fmrs	r0, s14		// move result back to r0
+	vmov	s14, r0		// move first param from r0 into float register
+	vmov	s15, r1		// move second param from r1 into float register
+	vadd.f32 s14, s14, s15
+	vmov	r0, s14		// move result back to r0
 	bx	lr
diff --git a/lib/arm/divdf3vfp.S b/lib/arm/divdf3vfp.S
index 74ef0eabf..52de67f7f 100644
--- a/lib/arm/divdf3vfp.S
+++ b/lib/arm/divdf3vfp.S
@@ -15,10 +15,11 @@
 // Divides two double precision floating point numbers using the Darwin
 // calling convention where double arguments are passsed in GPR pairs
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__divdf3vfp)
-	fmdrr	d6, r0, r1		// move first param from r0/r1 pair into d6
-	fmdrr	d7, r2, r3		// move second param from r2/r3 pair into d7
-	fdivd	d5, d6, d7		
-	fmrrd	r0, r1, d5		// move result back to r0/r1 pair
+	vmov	d6, r0, r1		// move first param from r0/r1 pair into d6
+	vmov	d7, r2, r3		// move second param from r2/r3 pair into d7
+	vdiv.f64 d5, d6, d7		
+	vmov	r0, r1, d5		// move result back to r0/r1 pair
 	bx	lr
diff --git a/lib/arm/divsf3vfp.S b/lib/arm/divsf3vfp.S
index 9eefcf31e..81ba90307 100644
--- a/lib/arm/divsf3vfp.S
+++ b/lib/arm/divsf3vfp.S
@@ -15,10 +15,11 @@
 // Divides two single precision floating point numbers using the Darwin
 // calling convention where single arguments are passsed like 32-bit ints.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__divsf3vfp)
-	fmsr	s14, r0		// move first param from r0 into float register
-	fmsr	s15, r1		// move second param from r1 into float register
-	fdivs	s13, s14, s15
-	fmrs	r0, s13		// move result back to r0
+	vmov	s14, r0		// move first param from r0 into float register
+	vmov	s15, r1		// move second param from r1 into float register
+	vdiv.f32 s13, s14, s15
+	vmov	r0, s13		// move result back to r0
 	bx	lr
diff --git a/lib/arm/eqdf2vfp.S b/lib/arm/eqdf2vfp.S
index 2998a76e0..c41e55a34 100644
--- a/lib/arm/eqdf2vfp.S
+++ b/lib/arm/eqdf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov	d6, r0, r1	// load r0/r1 pair in double register
+	vmov	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7		
+	vmrs	apsr_nzcv, fpscr
 	moveq	r0, #1		// set result register to 1 if equal
 	movne	r0, #0
 	bx	lr
diff --git a/lib/arm/eqsf2vfp.S b/lib/arm/eqsf2vfp.S
index 927566edd..730ef88da 100644
--- a/lib/arm/eqsf2vfp.S
+++ b/lib/arm/eqsf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__eqsf2vfp)
-	fmsr	s14, r0     // move from GPR 0 to float register
-	fmsr	s15, r1	    // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0     // move from GPR 0 to float register
+	vmov	s15, r1	    // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	moveq	r0, #1      // set result register to 1 if equal
 	movne	r0, #0
 	bx	lr
diff --git a/lib/arm/extendsfdf2vfp.S b/lib/arm/extendsfdf2vfp.S
index b1aa88e2a..17a146e02 100644
--- a/lib/arm/extendsfdf2vfp.S
+++ b/lib/arm/extendsfdf2vfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a single precision parameter is 
 // passed in a GPR and a double precision result is returned in R0/R1 pair.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp)
-	fmsr	s15, r0      // load float register from R0
-	fcvtds	d7, s15      // convert single to double
-	fmrrd	r0, r1, d7   // return result in r0/r1 pair
+	vmov	s15, r0      // load float register from R0
+	vcvt.f64.f32 d7, s15 // convert single to double
+	vmov	r0, r1, d7   // return result in r0/r1 pair
 	bx	lr
diff --git a/lib/arm/fixdfsivfp.S b/lib/arm/fixdfsivfp.S
index 0285a17e4..b7c3299d1 100644
--- a/lib/arm/fixdfsivfp.S
+++ b/lib/arm/fixdfsivfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a double precision parameter is 
 // passed in GPR register pair.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp)
-	fmdrr	d7, r0, r1    // load double register from R0/R1
-	ftosizd	s15, d7       // convert double to 32-bit int into s15
-	fmrs	r0, s15	      // move s15 to result register
+	vmov	d7, r0, r1    // load double register from R0/R1
+	vcvt.s32.f64 s15, d7  // convert double to 32-bit int into s15
+	vmov	r0, s15	      // move s15 to result register
 	bx	lr
diff --git a/lib/arm/fixsfsivfp.S b/lib/arm/fixsfsivfp.S
index d05ba740a..1cea6a486 100644
--- a/lib/arm/fixsfsivfp.S
+++ b/lib/arm/fixsfsivfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a single precision parameter is 
 // passed in a GPR..
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__fixsfsivfp)
-	fmsr	s15, r0      // load float register from R0
-	ftosizs	s15, s15     // convert single to 32-bit int into s15
-	fmrs	r0, s15	     // move s15 to result register
+	vmov	s15, r0        // load float register from R0
+	vcvt.s32.f32 s15, s15  // convert single to 32-bit int into s15
+	vmov	r0, s15	       // move s15 to result register
 	bx	lr
diff --git a/lib/arm/fixunsdfsivfp.S b/lib/arm/fixunsdfsivfp.S
index ddb703cdd..54b03592b 100644
--- a/lib/arm/fixunsdfsivfp.S
+++ b/lib/arm/fixunsdfsivfp.S
@@ -17,9 +17,10 @@
 // Uses Darwin calling convention where a double precision parameter is 
 // passed in GPR register pair.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp)
-	fmdrr	d7, r0, r1    // load double register from R0/R1
-	ftouizd	s15, d7       // convert double to 32-bit int into s15
-	fmrs	r0, s15	      // move s15 to result register
+	vmov	d7, r0, r1    // load double register from R0/R1
+	vcvt.u32.f64 s15, d7  // convert double to 32-bit int into s15
+	vmov	r0, s15	      // move s15 to result register
 	bx	lr
diff --git a/lib/arm/fixunssfsivfp.S b/lib/arm/fixunssfsivfp.S
index afbb64f39..12adb529a 100644
--- a/lib/arm/fixunssfsivfp.S
+++ b/lib/arm/fixunssfsivfp.S
@@ -17,9 +17,10 @@
 // Uses Darwin calling convention where a single precision parameter is 
 // passed in a GPR..
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__fixunssfsivfp)
-	fmsr	s15, r0      // load float register from R0
-	ftouizs	s15, s15     // convert single to 32-bit unsigned into s15
-	fmrs	r0, s15	     // move s15 to result register
+	vmov	s15, r0        // load float register from R0
+	vcvt.u32.f32 s15, s15  // convert single to 32-bit unsigned into s15
+	vmov	r0, s15	       // move s15 to result register
 	bx	lr
diff --git a/lib/arm/floatsidfvfp.S b/lib/arm/floatsidfvfp.S
index fe3366a90..e6a1eb3e4 100644
--- a/lib/arm/floatsidfvfp.S
+++ b/lib/arm/floatsidfvfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a double precision result is 
 // return in GPR register pair.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp)
-	fmsr	s15, r0		   // move int to float register s15
-	fsitod	d7, s15        // convert 32-bit int in s15 to double in d7
-	fmrrd	r0, r1, d7     // move d7 to result register pair r0/r1
+	vmov	s15, r0        // move int to float register s15
+	vcvt.f64.s32 d7, s15   // convert 32-bit int in s15 to double in d7
+	vmov	r0, r1, d7     // move d7 to result register pair r0/r1
 	bx	lr
diff --git a/lib/arm/floatsisfvfp.S b/lib/arm/floatsisfvfp.S
index 5b416100a..0d3a24fc1 100644
--- a/lib/arm/floatsisfvfp.S
+++ b/lib/arm/floatsisfvfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a single precision result is 
 // return in a GPR..
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__floatsisfvfp)
-	fmsr	s15, r0	     // move int to float register s15
-	fsitos	s15, s15     // convert 32-bit int in s15 to float in s15
-	fmrs	r0, s15      // move s15 to result register
+	vmov	s15, r0	       // move int to float register s15
+	vcvt.f32.s32 s15, s15  // convert 32-bit int in s15 to float in s15
+	vmov	r0, s15        // move s15 to result register
 	bx	lr
diff --git a/lib/arm/floatunssidfvfp.S b/lib/arm/floatunssidfvfp.S
index 9b22a6f76..770b20292 100644
--- a/lib/arm/floatunssidfvfp.S
+++ b/lib/arm/floatunssidfvfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a double precision result is 
 // return in GPR register pair.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
-	fmsr	s15, r0		   // move int to float register s15
-	fuitod	d7, s15        // convert 32-bit int in s15 to double in d7
-	fmrrd	r0, r1, d7     // move d7 to result register pair r0/r1
+	vmov	s15, r0        // move int to float register s15
+	vcvt.f64.u32 d7, s15   // convert 32-bit int in s15 to double in d7
+	vmov	r0, r1, d7     // move d7 to result register pair r0/r1
 	bx	lr
diff --git a/lib/arm/floatunssisfvfp.S b/lib/arm/floatunssisfvfp.S
index 44d5e9380..16b3ffb10 100644
--- a/lib/arm/floatunssisfvfp.S
+++ b/lib/arm/floatunssisfvfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a single precision result is 
 // return in a GPR..
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__floatunssisfvfp)
-	fmsr	s15, r0	     // move int to float register s15
-	fuitos 	s15, s15     // convert 32-bit int in s15 to float in s15
-	fmrs	r0, s15      // move s15 to result register
+	vmov	s15, r0	       // move int to float register s15
+	vcvt.f32.u32 s15, s15  // convert 32-bit int in s15 to float in s15
+	vmov	r0, s15        // move s15 to result register
 	bx	lr
diff --git a/lib/arm/gedf2vfp.S b/lib/arm/gedf2vfp.S
index 9993f52fb..55603b83e 100644
--- a/lib/arm/gedf2vfp.S
+++ b/lib/arm/gedf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__gedf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7
+	vmrs	apsr_nzcv, fpscr
 	movge	r0, #1      // set result register to 1 if greater than or equal
 	movlt	r0, #0
 	bx	lr
diff --git a/lib/arm/gesf2vfp.S b/lib/arm/gesf2vfp.S
index 9ce168259..02da35c02 100644
--- a/lib/arm/gesf2vfp.S
+++ b/lib/arm/gesf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__gesf2vfp)
-	fmsr	s14, r0	    // move from GPR 0 to float register
-	fmsr	s15, r1	    // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0	    // move from GPR 0 to float register
+	vmov	s15, r1	    // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movge	r0, #1      // set result register to 1 if greater than or equal
 	movlt	r0, #0
 	bx	lr
diff --git a/lib/arm/gtdf2vfp.S b/lib/arm/gtdf2vfp.S
index 8a049c889..b5b1e1482 100644
--- a/lib/arm/gtdf2vfp.S
+++ b/lib/arm/gtdf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__gtdf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7
+	vmrs	apsr_nzcv, fpscr
 	movgt	r0, #1		// set result register to 1 if equal
 	movle	r0, #0
 	bx	lr
diff --git a/lib/arm/gtsf2vfp.S b/lib/arm/gtsf2vfp.S
index 1ffe1ec52..685a9cec9 100644
--- a/lib/arm/gtsf2vfp.S
+++ b/lib/arm/gtsf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__gtsf2vfp)
-	fmsr	s14, r0		// move from GPR 0 to float register
-	fmsr	s15, r1		// move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0		// move from GPR 0 to float register
+	vmov	s15, r1		// move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movgt	r0, #1		// set result register to 1 if equal
 	movle	r0, #0
 	bx	lr
diff --git a/lib/arm/ledf2vfp.S b/lib/arm/ledf2vfp.S
index a04d0f2a4..6e140dde8 100644
--- a/lib/arm/ledf2vfp.S
+++ b/lib/arm/ledf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__ledf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7
+	vmrs	apsr_nzcv, fpscr
 	movls	r0, #1		// set result register to 1 if equal
 	movhi	r0, #0
 	bx	lr
diff --git a/lib/arm/lesf2vfp.S b/lib/arm/lesf2vfp.S
index 301120047..7b2825097 100644
--- a/lib/arm/lesf2vfp.S
+++ b/lib/arm/lesf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__lesf2vfp)
-	fmsr	s14, r0     // move from GPR 0 to float register
-	fmsr	s15, r1     // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0     // move from GPR 0 to float register
+	vmov	s15, r1     // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movls	r0, #1      // set result register to 1 if equal
 	movhi	r0, #0
 	bx	lr
diff --git a/lib/arm/ltdf2vfp.S b/lib/arm/ltdf2vfp.S
index 87144a8c8..a09e67a2f 100644
--- a/lib/arm/ltdf2vfp.S
+++ b/lib/arm/ltdf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__ltdf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7
+	vmrs	apsr_nzcv, fpscr
 	movmi	r0, #1		// set result register to 1 if equal
 	movpl	r0, #0
 	bx	lr
diff --git a/lib/arm/ltsf2vfp.S b/lib/arm/ltsf2vfp.S
index ca06ae208..8c7f9a863 100644
--- a/lib/arm/ltsf2vfp.S
+++ b/lib/arm/ltsf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__ltsf2vfp)
-	fmsr	s14, r0     // move from GPR 0 to float register
-	fmsr	s15, r1     // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0     // move from GPR 0 to float register
+	vmov	s15, r1     // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movmi	r0, #1      // set result register to 1 if equal
 	movpl	r0, #0
 	bx	lr
diff --git a/lib/arm/muldf3vfp.S b/lib/arm/muldf3vfp.S
index 96bba06c1..838581eb1 100644
--- a/lib/arm/muldf3vfp.S
+++ b/lib/arm/muldf3vfp.S
@@ -15,10 +15,11 @@
 // Multiplies two double precision floating point numbers using the Darwin
 // calling convention where double arguments are passsed in GPR pairs
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__muldf3vfp)
-	fmdrr	d6, r0, r1		// move first param from r0/r1 pair into d6
-	fmdrr	d7, r2, r3		// move second param from r2/r3 pair into d7
-	fmuld	d6, d6, d7		
-	fmrrd	r0, r1, d6		// move result back to r0/r1 pair
+	vmov 	d6, r0, r1         // move first param from r0/r1 pair into d6
+	vmov 	d7, r2, r3         // move second param from r2/r3 pair into d7
+	vmul.f64 d6, d6, d7		
+	vmov 	r0, r1, d6         // move result back to r0/r1 pair
 	bx	lr
diff --git a/lib/arm/mulsf3vfp.S b/lib/arm/mulsf3vfp.S
index c56991d62..ea25913cc 100644
--- a/lib/arm/mulsf3vfp.S
+++ b/lib/arm/mulsf3vfp.S
@@ -15,10 +15,11 @@
 // Multiplies two single precision floating point numbers using the Darwin
 // calling convention where single arguments are passsed like 32-bit ints.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__mulsf3vfp)
-	fmsr	s14, r0		// move first param from r0 into float register
-	fmsr	s15, r1		// move second param from r1 into float register
-	fmuls	s13, s14, s15
-	fmrs	r0, s13		// move result back to r0
+	vmov	s14, r0		// move first param from r0 into float register
+	vmov	s15, r1		// move second param from r1 into float register
+	vmul.f32 s13, s14, s15
+	vmov	r0, s13		// move result back to r0
 	bx	lr
diff --git a/lib/arm/nedf2vfp.S b/lib/arm/nedf2vfp.S
index a02b09cc8..21670816c 100644
--- a/lib/arm/nedf2vfp.S
+++ b/lib/arm/nedf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__nedf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7		
+	vmrs	apsr_nzcv, fpscr
 	movne	r0, #1		// set result register to 0 if unequal
 	moveq	r0, #0
 	bx	lr
diff --git a/lib/arm/negdf2vfp.S b/lib/arm/negdf2vfp.S
index 100f4fd5c..64c9b692f 100644
--- a/lib/arm/negdf2vfp.S
+++ b/lib/arm/negdf2vfp.S
@@ -15,6 +15,7 @@
 // Returns the negation a double precision floating point numbers using the 
 // Darwin calling convention where double arguments are passsed in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__negdf2vfp)
 	eor	r1, r1, #-2147483648	// flip sign bit on double in r0/r1 pair
diff --git a/lib/arm/negsf2vfp.S b/lib/arm/negsf2vfp.S
index f96c8ad2b..b883b733d 100644
--- a/lib/arm/negsf2vfp.S
+++ b/lib/arm/negsf2vfp.S
@@ -15,6 +15,7 @@
 // Returns the negation of a single precision floating point numbers using the 
 // Darwin calling convention where single arguments are passsed like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__negsf2vfp)
 	eor	r0, r0, #-2147483648	// flip sign bit on float in r0
diff --git a/lib/arm/nesf2vfp.S b/lib/arm/nesf2vfp.S
index d6205497a..fa7aa80e1 100644
--- a/lib/arm/nesf2vfp.S
+++ b/lib/arm/nesf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__nesf2vfp)
-	fmsr	s14, r0	    // move from GPR 0 to float register
-	fmsr	s15, r1	    // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0	    // move from GPR 0 to float register
+	vmov	s15, r1	    // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movne	r0, #1      // set result register to 1 if unequal
 	moveq	r0, #0
 	bx	lr
diff --git a/lib/arm/subdf3vfp.S b/lib/arm/subdf3vfp.S
index ff53b3000..3f88baacd 100644
--- a/lib/arm/subdf3vfp.S
+++ b/lib/arm/subdf3vfp.S
@@ -15,10 +15,11 @@
 // Returns difference between two double precision floating point numbers using 
 // the Darwin calling convention where double arguments are passsed in GPR pairs
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__subdf3vfp)
-	fmdrr	d6, r0, r1		// move first param from r0/r1 pair into d6
-	fmdrr	d7, r2, r3		// move second param from r2/r3 pair into d7
-	fsubd	d6, d6, d7		
-	fmrrd	r0, r1, d6		// move result back to r0/r1 pair
+	vmov 	d6, r0, r1         // move first param from r0/r1 pair into d6
+	vmov 	d7, r2, r3         // move second param from r2/r3 pair into d7
+	vsub.f64 d6, d6, d7		
+	vmov 	r0, r1, d6         // move result back to r0/r1 pair
 	bx	lr
diff --git a/lib/arm/subsf3vfp.S b/lib/arm/subsf3vfp.S
index 238f3f047..ed02ba921 100644
--- a/lib/arm/subsf3vfp.S
+++ b/lib/arm/subsf3vfp.S
@@ -16,10 +16,11 @@
 // using the Darwin calling convention where single arguments are passsed
 // like 32-bit ints.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__subsf3vfp)
-	fmsr	s14, r0		// move first param from r0 into float register
-	fmsr	s15, r1		// move second param from r1 into float register
-	fsubs	s14, s14, s15
-	fmrs	r0, s14		// move result back to r0
+	vmov	s14, r0		// move first param from r0 into float register
+	vmov	s15, r1		// move second param from r1 into float register
+	vsub.f32 s14, s14, s15
+	vmov	r0, s14		// move result back to r0
 	bx	lr
diff --git a/lib/arm/truncdfsf2vfp.S b/lib/arm/truncdfsf2vfp.S
index 6e55c7ffb..371aee94b 100644
--- a/lib/arm/truncdfsf2vfp.S
+++ b/lib/arm/truncdfsf2vfp.S
@@ -16,9 +16,10 @@
 // Uses Darwin calling convention where a double precision parameter is 
 // passed in a R0/R1 pair and a signle precision result is returned in R0.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__truncdfsf2vfp)
-	fmdrr	d7, r0, r1   // load double from r0/r1 pair
-	fcvtsd	s15, d7      // convert double to single (trucate precision)
-	fmrs	r0, s15      // return result in r0
+	vmov 	d7, r0, r1   // load double from r0/r1 pair
+	vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
+	vmov 	r0, s15      // return result in r0
 	bx	lr
diff --git a/lib/arm/unorddf2vfp.S b/lib/arm/unorddf2vfp.S
index 9b52131e4..c49e55f29 100644
--- a/lib/arm/unorddf2vfp.S
+++ b/lib/arm/unorddf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where double precision arguments are passsed 
 // like in GPR pairs.
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__unorddf2vfp)
-	fmdrr	d6, r0, r1	// load r0/r1 pair in double register
-	fmdrr	d7, r2, r3	// load r2/r3 pair in double register
-	fcmpd	d6, d7		
-	fmstat
+	vmov 	d6, r0, r1	// load r0/r1 pair in double register
+	vmov 	d7, r2, r3	// load r2/r3 pair in double register
+	vcmp.f64 d6, d7		
+	vmrs	apsr_nzcv, fpscr
 	movvs	r0, #1      // set result register to 1 if "overflow" (any NaNs)
 	movvc	r0, #0
 	bx	lr
diff --git a/lib/arm/unordsf2vfp.S b/lib/arm/unordsf2vfp.S
index e486533e2..0ab27edf5 100644
--- a/lib/arm/unordsf2vfp.S
+++ b/lib/arm/unordsf2vfp.S
@@ -16,12 +16,13 @@
 // Uses Darwin calling convention where single precision arguments are passsed 
 // like 32-bit ints
 //
+	.syntax unified
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__unordsf2vfp)
-	fmsr	s14, r0     // move from GPR 0 to float register
-	fmsr	s15, r1	    // move from GPR 1 to float register
-	fcmps	s14, s15
-	fmstat
+	vmov	s14, r0     // move from GPR 0 to float register
+	vmov	s15, r1	    // move from GPR 1 to float register
+	vcmp.f32 s14, s15
+	vmrs	apsr_nzcv, fpscr
 	movvs	r0, #1      // set result register to 1 if "overflow" (any NaNs)
 	movvc	r0, #0
 	bx	lr