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| author | Olivier Deprez <olivier.deprez@arm.com> | 2021-05-25 12:06:03 +0200 |
|---|---|---|
| committer | Olivier Deprez <olivier.deprez@arm.com> | 2021-06-03 09:31:10 +0200 |
| commit | 2e61d6871cc310e9404fe5cfa10b9828f1c869a7 (patch) | |
| tree | 61024a28709256c620be75b3811bdeb3fa84af40 | |
| parent | 203d48adcad8d90eb8fb5eb4bb2de4c65c9837af (diff) | |
| download | arm-trusted-firmware-2e61d6871cc310e9404fe5cfa10b9828f1c869a7.tar.gz | |
fix: random typos in tf-a code base
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 4 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch32/context_mgmt.c | 4 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 730b09beb..bd8f85f6d 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -144,7 +144,7 @@ endfunc do_cpu_reg_dump * If cpu_ops for the MIDR_EL1 cannot be found and * SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a * default cpu_ops with an MIDR value of 0. - * (Implementation number 0x0 should be reseverd for software use + * (Implementation number 0x0 should be reserved for software use * and therefore no clashes should happen with that default value). * * Return : diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 2443001b8..81d793b46 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,7 @@ void cm_init(void) * * To prepare the register state for entry call cm_prepare_el3_exit() and * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to - * cm_e1_sysreg_context_restore(). + * cm_el1_sysregs_context_restore(). ******************************************************************************/ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e0e429849..96023b694 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -60,7 +60,7 @@ void __init cm_init(void) * * To prepare the register state for entry call cm_prepare_el3_exit() and * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to - * cm_e1_sysreg_context_restore(). + * cm_el1_sysregs_context_restore(). ******************************************************************************/ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { @@ -286,7 +286,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) /* * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 - * and other EL2 registers are set up by cm_prepare_ns_entry() as they + * and other EL2 registers are set up by cm_prepare_el3_exit() as they * are not part of the stored cpu_context. */ write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); |