diff options
author | Bipin Ravi <bipin.ravi@arm.com> | 2023-02-06 03:16:01 +0100 |
---|---|---|
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-02-06 03:16:01 +0100 |
commit | 81b01a9b719597b498029705f14c547160acb99a (patch) | |
tree | 0ce75b2d85bc9f79aa9945583e2e47da6872e5a8 | |
parent | a6d2f1aac8b50c8fd46e4cb281df8a3bd4f36ecc (diff) | |
parent | 40b90a9c4ce8a7f131ea65edb549d8f0160a5999 (diff) | |
download | arm-trusted-firmware-81b01a9b719597b498029705f14c547160acb99a.tar.gz |
Merge "fix(layerscape): unlock write access SMMU_CBn_ACTLR" into lts-v2.8
-rw-r--r-- | include/drivers/nxp/smmu/nxp_smmu.h | 12 | ||||
-rw-r--r-- | plat/nxp/soc-ls1043a/soc.c | 8 | ||||
-rw-r--r-- | plat/nxp/soc-ls1043a/soc.mk | 2 | ||||
-rw-r--r-- | plat/nxp/soc-ls1046a/soc.c | 8 | ||||
-rw-r--r-- | plat/nxp/soc-ls1046a/soc.mk | 2 | ||||
-rw-r--r-- | plat/nxp/soc-ls1088a/soc.c | 8 | ||||
-rw-r--r-- | plat/nxp/soc-ls1088a/soc.mk | 2 | ||||
-rw-r--r-- | plat/nxp/soc-lx2160a/soc.c | 8 | ||||
-rw-r--r-- | plat/nxp/soc-lx2160a/soc.mk | 2 |
9 files changed, 40 insertions, 12 deletions
diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h index d64c33b20..bc17703dc 100644 --- a/include/drivers/nxp/smmu/nxp_smmu.h +++ b/include/drivers/nxp/smmu/nxp_smmu.h @@ -10,10 +10,13 @@ #define SMMU_SCR0 (0x0) #define SMMU_NSCR0 (0x400) +#define SMMU_SACR (0x10) #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 +#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) + static inline void bypass_smmu(uintptr_t smmu_base_addr) { uint32_t val; @@ -27,4 +30,13 @@ static inline void bypass_smmu(uintptr_t smmu_base_addr) mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); } +static inline void smmu_cache_unlock(uintptr_t smmu_base_addr) +{ + uint32_t val; + + val = mmio_read_32((smmu_base_addr + SMMU_SACR)); + val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; + mmio_write_32((smmu_base_addr + SMMU_SACR), val); +} + #endif diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c index 7badf8c38..3e821d0c2 100644 --- a/plat/nxp/soc-ls1043a/soc.c +++ b/plat/nxp/soc-ls1043a/soc.c @@ -21,9 +21,7 @@ #ifdef POLICY_FUSE_PROVISION #include <nxp_gpio.h> #endif -#if TRUSTED_BOARD_BOOT #include <nxp_smmu.h> -#endif #include <nxp_timer.h> #include <plat_console.h> #include <plat_gic.h> @@ -174,6 +172,12 @@ void soc_early_init(void) get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); plat_ls_interconnect_enter_coherency(num_clusters); + /* + * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. + */ + smmu_cache_unlock(NXP_SMMU_ADDR); + INFO("SMMU Cache Unlocking is Configured.\n"); + #if TRUSTED_BOARD_BOOT uint32_t mode; diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk index b6ce14e5e..0ebb3774d 100644 --- a/plat/nxp/soc-ls1043a/soc.mk +++ b/plat/nxp/soc-ls1043a/soc.mk @@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk # For Security Features DISABLE_FUSE_WRITE := 1 -ifeq (${TRUSTED_BOARD_BOOT}, 1) $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) +ifeq (${TRUSTED_BOARD_BOOT}, 1) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) SECURE_BOOT := yes diff --git a/plat/nxp/soc-ls1046a/soc.c b/plat/nxp/soc-ls1046a/soc.c index d17e67219..6dfea89bb 100644 --- a/plat/nxp/soc-ls1046a/soc.c +++ b/plat/nxp/soc-ls1046a/soc.c @@ -21,9 +21,7 @@ #ifdef POLICY_FUSE_PROVISION #include <nxp_gpio.h> #endif -#if TRUSTED_BOARD_BOOT #include <nxp_smmu.h> -#endif #include <nxp_timer.h> #include <plat_console.h> #include <plat_gic.h> @@ -168,6 +166,12 @@ void soc_early_init(void) get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); plat_ls_interconnect_enter_coherency(num_clusters); + /* + * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. + */ + smmu_cache_unlock(NXP_SMMU_ADDR); + INFO("SMMU Cache Unlocking is Configured.\n"); + #if TRUSTED_BOARD_BOOT uint32_t mode; diff --git a/plat/nxp/soc-ls1046a/soc.mk b/plat/nxp/soc-ls1046a/soc.mk index 8207dcd80..764402719 100644 --- a/plat/nxp/soc-ls1046a/soc.mk +++ b/plat/nxp/soc-ls1046a/soc.mk @@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk # For Security Features DISABLE_FUSE_WRITE := 1 -ifeq (${TRUSTED_BOARD_BOOT}, 1) $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) +ifeq (${TRUSTED_BOARD_BOOT}, 1) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) SECURE_BOOT := yes diff --git a/plat/nxp/soc-ls1088a/soc.c b/plat/nxp/soc-ls1088a/soc.c index 5f9f313e2..02d62ea88 100644 --- a/plat/nxp/soc-ls1088a/soc.c +++ b/plat/nxp/soc-ls1088a/soc.c @@ -17,9 +17,7 @@ #include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables_v2.h> #include <ls_interconnect.h> -#if TRUSTED_BOARD_BOOT #include <nxp_smmu.h> -#endif #include <nxp_timer.h> #include <plat_console.h> #include <plat_gic.h> @@ -254,6 +252,12 @@ void soc_early_init(void) MT_DEVICE | MT_RW | MT_NS); } + /* + * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. + */ + smmu_cache_unlock(NXP_SMMU_ADDR); + INFO("SMMU Cache Unlocking is Configured.\n"); + #if TRUSTED_BOARD_BOOT uint32_t mode; diff --git a/plat/nxp/soc-ls1088a/soc.mk b/plat/nxp/soc-ls1088a/soc.mk index 83ac9d08f..6e39461e3 100644 --- a/plat/nxp/soc-ls1088a/soc.mk +++ b/plat/nxp/soc-ls1088a/soc.mk @@ -23,12 +23,12 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk # For Security Features DISABLE_FUSE_WRITE := 1 +$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) ifeq (${TRUSTED_BOARD_BOOT}, 1) ifeq (${GENERATE_COT},1) # Save Keys to be used by DDR FIP image SAVE_KEYS=1 endif -$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) # Used by create_pbl tool to diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c index df313935c..427189dc5 100644 --- a/plat/nxp/soc-lx2160a/soc.c +++ b/plat/nxp/soc-lx2160a/soc.c @@ -23,9 +23,7 @@ #ifdef POLICY_FUSE_PROVISION #include <nxp_gpio.h> #endif -#if TRUSTED_BOARD_BOOT #include <nxp_smmu.h> -#endif #include <nxp_timer.h> #include <plat_console.h> #include <plat_gic.h> @@ -286,6 +284,12 @@ void soc_early_init(void) sfp_init(NXP_SFP_ADDR); #endif + /* + * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. + */ + smmu_cache_unlock(NXP_SMMU_ADDR); + INFO("SMMU Cache Unlocking is Configured.\n"); + #if TRUSTED_BOARD_BOOT uint32_t mode; diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk index 75a3af294..239442c20 100644 --- a/plat/nxp/soc-lx2160a/soc.mk +++ b/plat/nxp/soc-lx2160a/soc.mk @@ -36,12 +36,12 @@ endif # For Security Features DISABLE_FUSE_WRITE := 1 +$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) ifeq (${TRUSTED_BOARD_BOOT}, 1) ifeq (${GENERATE_COT},1) # Save Keys to be used by DDR FIP image SAVE_KEYS=1 endif -$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) # Used by create_pbl tool to |