summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBipin Ravi <bipin.ravi@arm.com>2023-02-06 03:29:56 +0100
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2023-02-06 03:29:56 +0100
commitf4bb2cc70b2b9c2789b617326682c831f05c2e70 (patch)
tree8b34dd912c4cb182a26b9a31a505eac2995142b9
parentc3b1d08fe86a84cf89e8374b9cbeff2a7a127234 (diff)
parentb33ea1e3e91430d03d4328f1c7c094af7622ff2d (diff)
downloadarm-trusted-firmware-f4bb2cc70b2b9c2789b617326682c831f05c2e70.tar.gz
Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into lts-v2.8
-rw-r--r--docs/design/cpu-specific-build-macros.rst4
-rw-r--r--lib/cpus/aarch64/cortex_a78c.S38
-rw-r--r--lib/cpus/cpu-ops.mk8
3 files changed, 47 insertions, 3 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c4a0e1558..f2408aa79 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -361,6 +361,10 @@ For Cortex-A78C, the following errata build flags are defined :
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
+- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
+ Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
+ This erratum is still open.
+
For Cortex-X1 CPU, the following errata build flags are defined:
- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 49cebfe59..5cdce89c2 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,13 +117,13 @@ func check_errata_2132064
b cpu_rev_var_range
endfunc check_errata_2132064
-/* --------------------------------------------------------------------
+/* ----------------------------------------------------------
* Errata Workaround for A78C Erratum 2242638.
* This applies to revisions r0p1 and r0p2 of the Cortex A78C
* processor and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
- * --------------------------------------------------------------------
+ * ----------------------------------------------------------
*/
func errata_a78c_2242638_wa
/* Compare x0 against revisions r0p1 - r0p2 */
@@ -152,6 +152,31 @@ func check_errata_2242638
b cpu_rev_var_range
endfunc check_errata_2242638
+/* ----------------------------------------------------------------
+ * Errata Workaround for A78C Erratum 2772121.
+ * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
+ * processor and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------------------
+ */
+func errata_a78c_2772121_wa
+ mov x17, x30
+ bl check_errata_2772121
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_a78c_2772121_wa
+
+func check_errata_2772121
+ /* Applies to all revisions <= r0p2 */
+ mov x1, #0x02
+ b cpu_rev_var_ls
+endfunc check_errata_2772121
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -215,6 +240,12 @@ func cortex_a78c_core_pwr_dwn
mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
+#if ERRATA_A78C_2772121
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_a78c_2772121_wa
+ mov x30, x15
+#endif /* ERRATA_A78C_2772121 */
isb
ret
endfunc cortex_a78c_core_pwr_dwn
@@ -237,6 +268,7 @@ func cortex_a78c_errata_report
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
+ report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4d50c1bb1..8bc6ff486 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -398,6 +398,10 @@ ERRATA_A78C_2376749 ?=0
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2395411 ?=0
+# Flag to apply erratum 2772121 workaround during powerdown. This erratum
+# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
+ERRATA_A78C_2772121 ?=0
+
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
ERRATA_X1_1821534 ?=0
@@ -1075,6 +1079,10 @@ $(eval $(call add_define,ERRATA_A78C_2376749))
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
$(eval $(call add_define,ERRATA_A78C_2395411))
+# Process ERRATA_A78C_2772121 flag
+$(eval $(call assert_boolean,ERRATA_A78C_2772121))
+$(eval $(call add_define,ERRATA_A78C_2772121))
+
# Process ERRATA_X1_1821534 flag
$(eval $(call assert_boolean,ERRATA_X1_1821534))
$(eval $(call add_define,ERRATA_X1_1821534))