fdts: Add DTS files used in the prototype

The following DTS files are added to enable the use of the
prototype:

- inner_initrd.dts: DTS for N-HF ramdisk
- normal_world_multi: 8 core DTS for ATF and booting HF
- normal_world_single: Single core DTS for ATF and booting HF
- secure_world_dt.dts: DTS for S-HF

Change-Id: I75e1e17eb933083ab695637cab343992fa3af929

4 files changed, 1021 insertions, 0 deletions

diff --git a/fdts/inner_initrd.dts b/fdts/inner_initrd.dts
new file mode 100644
index 000000000..c4d458e3a
--- /dev/null
+++ b/fdts/inner_initrd.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+
+	hypervisor {
+		compatible = "hafnium,hafnium";
+		spci_tee;
+
+		vm1 {
+			debug_name = "linux_test";
+			kernel_filename = "vmlinuz";
+			ramdisk_filename = "initrd.img";
+			uuid = < 0x00 0x00 0x00 0x01 >;
+			messaging_method = < 0x02 >;
+		};
+	};
+};
diff --git a/fdts/normal_world_multi.dts b/fdts/normal_world_multi.dts
new file mode 100644
index 000000000..48148cce4
--- /dev/null
+++ b/fdts/normal_world_multi.dts
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/memreserve/	0x0000000080000000 0x0000000000010000;
+/ {
+	model = "FVP Base";
+	compatible = "arm,vfp-base", "arm,vexpress";
+	interrupt-parent = <0x1>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	aliases {
+		serial0 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@90000";
+		serial1 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@a0000";
+		serial2 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@b0000";
+		serial3 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@c0000";
+	};
+
+	firmware {
+
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "ffa";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+		method = "smc";
+		cpu_suspend = <0xc4000001>;
+		cpu_off = <0x84000002>;
+		cpu_on = <0xc4000003>;
+		sys_poweroff = <0x84000008>;
+		sys_reset = <0x84000009>;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu-map {
+
+			cluster0 {
+
+				core0 {
+					cpu = <0x2>;
+				};
+
+				core1 {
+					cpu = <0x3>;
+				};
+
+				core2 {
+					cpu = <0x4>;
+				};
+
+				core3 {
+					cpu = <0x5>;
+				};
+			};
+
+			cluster1 {
+
+				core0 {
+					cpu = <0x6>;
+				};
+
+				core1 {
+					cpu = <0x7>;
+				};
+
+				core2 {
+					cpu = <0x8>;
+				};
+
+				core3 {
+					cpu = <0x9>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "arm,psci";
+
+			cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x10000>;
+				entry-latency-us = <0x28>;
+				exit-latency-us = <0x64>;
+				min-residency-us = <0x96>;
+				phandle = <0xa>;
+			};
+
+			cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x1010000>;
+				entry-latency-us = <0x1f4>;
+				exit-latency-us = <0x3e8>;
+				min-residency-us = <0x9c4>;
+				phandle = <0xb>;
+			};
+		};
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x3>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x4>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x5>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x6>;
+		};
+
+		cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x7>;
+		};
+
+		cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x10200>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x8>;
+		};
+
+		cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x10300>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x9>;
+		};
+
+		l2-cache0 {
+			compatible = "cache";
+			phandle = <0xc>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x7f000000 0x8 0x80000000 0x0 0x80000000>;
+	};
+
+	interrupt-controller@2f000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <0x3>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+		interrupt-controller;
+		reg = <0x0 0x2f000000 0x0 0x10000 0x0 0x2f100000 0x0 0x200000 0x0 0x2c000000 0x0 0x2000 0x0 0x2c010000 0x0 0x2000 0x0 0x2c02f000 0x0 0x2000>;
+		interrupts = <0x1 0x9 0x4>;
+		phandle = <0x1>;
+
+		its@2f020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2f020000 0x0 0x20000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
+		clock-frequency = <0x5f5e100>;
+	};
+
+	timer@2a810000 {
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x0 0x2a810000 0x0 0x10000>;
+		clock-frequency = <0x5f5e100>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		frame@2a830000 {
+			frame-number = <0x1>;
+			interrupts = <0x0 0x1a 0x4>;
+			reg = <0x0 0x2a830000 0x0 0x10000>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4 0x0 0x3f 0x4>;
+	};
+
+	smb@0,0 {
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		ranges = <0x0 0x0 0x0 0x8000000 0x4000000 0x1 0x0 0x0 0x14000000 0x4000000 0x2 0x0 0x0 0x18000000 0x4000000 0x3 0x0 0x0 0x1c000000 0x4000000 0x4 0x0 0x0 0xc000000 0x4000000 0x5 0x0 0x0 0x10000000 0x4000000>;
+
+		motherboard {
+			arm,v2m-memory-map = "rs1";
+			compatible = "arm,vexpress,v2m-p1", "simple-bus";
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			ranges;
+
+			flash@0,00000000 {
+				compatible = "arm,vexpress-flash", "cfi-flash";
+				reg = <0x0 0x0 0x4000000 0x4 0x0 0x4000000>;
+				bank-width = <0x4>;
+			};
+
+			vram@2,00000000 {
+				compatible = "arm,vexpress-vram";
+				reg = <0x2 0x0 0x800000>;
+			};
+
+			ethernet@2,02000000 {
+				compatible = "smsc,lan91c111";
+				reg = <0x2 0x2000000 0x10000>;
+				interrupts = <0x0 0xf 0x4>;
+			};
+
+			clk24mhz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x16e3600>;
+				clock-output-names = "v2m:clk24mhz";
+				phandle = <0xf>;
+			};
+
+			refclk1mhz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0xf4240>;
+				clock-output-names = "v2m:refclk1mhz";
+				phandle = <0xe>;
+			};
+
+			refclk32khz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x8000>;
+				clock-output-names = "v2m:refclk32khz";
+				phandle = <0xd>;
+			};
+
+			iofpga@3,00000000 {
+				compatible = "arm,amba-bus", "simple-bus";
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				ranges = <0x0 0x3 0x0 0x200000>;
+
+				sysreg@10000 {
+					compatible = "arm,vexpress-sysreg";
+					reg = <0x10000 0x1000>;
+					gpio-controller;
+					#gpio-cells = <0x2>;
+					phandle = <0x10>;
+				};
+
+				sysctl@20000 {
+					compatible = "arm,sp810", "arm,primecell";
+					reg = <0x20000 0x1000>;
+					clocks = <0xd 0xe 0xf>;
+					clock-names = "refclk", "timclk", "apb_pclk";
+					#clock-cells = <0x1>;
+					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+					phandle = <0x12>;
+				};
+
+				aaci@40000 {
+					compatible = "arm,pl041", "arm,primecell";
+					reg = <0x40000 0x1000>;
+					interrupts = <0x0 0xb 0x4>;
+					clocks = <0xf>;
+					clock-names = "apb_pclk";
+				};
+
+				mmci@50000 {
+					compatible = "arm,pl180", "arm,primecell";
+					reg = <0x50000 0x1000>;
+					interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
+					cd-gpios = <0x10 0x0 0x0>;
+					wp-gpios = <0x10 0x1 0x0>;
+					max-frequency = <0xb71b00>;
+					vmmc-supply = <0x11>;
+					clocks = <0xf 0xf>;
+					clock-names = "mclk", "apb_pclk";
+				};
+
+				kmi@60000 {
+					compatible = "arm,pl050", "arm,primecell";
+					reg = <0x60000 0x1000>;
+					interrupts = <0x0 0xc 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "KMIREFCLK", "apb_pclk";
+				};
+
+				kmi@70000 {
+					compatible = "arm,pl050", "arm,primecell";
+					reg = <0x70000 0x1000>;
+					interrupts = <0x0 0xd 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "KMIREFCLK", "apb_pclk";
+				};
+
+				uart@90000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0x90000 0x1000>;
+					interrupts = <0x0 0x5 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@a0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xa0000 0x1000>;
+					interrupts = <0x0 0x6 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@b0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xb0000 0x1000>;
+					interrupts = <0x0 0x7 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@c0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xc0000 0x1000>;
+					interrupts = <0x0 0x8 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				wdt@f0000 {
+					compatible = "arm,sp805", "arm,primecell";
+					reg = <0xf0000 0x1000>;
+					interrupts = <0x0 0x0 0x4>;
+					clocks = <0xd 0xf>;
+					clock-names = "wdogclk", "apb_pclk";
+				};
+
+				timer@110000 {
+					compatible = "arm,sp804", "arm,primecell";
+					reg = <0x110000 0x1000>;
+					interrupts = <0x0 0x2 0x4>;
+					clocks = <0x12 0x0 0x12 0x1 0xf>;
+					clock-names = "timclken1", "timclken2", "apb_pclk";
+				};
+
+				timer@120000 {
+					compatible = "arm,sp804", "arm,primecell";
+					reg = <0x120000 0x1000>;
+					interrupts = <0x0 0x3 0x4>;
+					clocks = <0x12 0x2 0x12 0x3 0xf>;
+					clock-names = "timclken1", "timclken2", "apb_pclk";
+				};
+
+				rtc@170000 {
+					compatible = "arm,pl031", "arm,primecell";
+					reg = <0x170000 0x1000>;
+					interrupts = <0x0 0x4 0x4>;
+					clocks = <0xf>;
+					clock-names = "apb_pclk";
+				};
+
+				clcd@1f0000 {
+					compatible = "arm,pl111", "arm,primecell";
+					reg = <0x1f0000 0x1000>;
+					interrupts = <0x0 0xe 0x4>;
+					clocks = <0x13 0xf>;
+					clock-names = "clcdclk", "apb_pclk";
+					mode = "XVGA";
+					use_dma = <0x0>;
+					framebuffer = <0x18000000 0x180000>;
+				};
+
+				virtio_block@130000 {
+					compatible = "virtio,mmio";
+					reg = <0x130000 0x1000>;
+					interrupts = <0x0 0x2a 0x4>;
+				};
+			};
+
+			fixedregulator {
+				compatible = "regulator-fixed";
+				regulator-name = "3V3";
+				regulator-min-microvolt = <0x325aa0>;
+				regulator-max-microvolt = <0x325aa0>;
+				regulator-always-on;
+				phandle = <0x11>;
+			};
+
+			mcc {
+				compatible = "arm,vexpress,config-bus", "simple-bus";
+				arm,vexpress,config-bridge = <0x10>;
+
+				osc {
+					compatible = "arm,vexpress-osc";
+					arm,vexpress-sysreg,func = <0x1 0x1>;
+					freq-range = <0x16a6570 0x3c8eee0>;
+					#clock-cells = <0x0>;
+					clock-output-names = "v2m:oscclk1";
+					phandle = <0x13>;
+				};
+
+				muxfpga {
+					compatible = "arm,vexpress-muxfpga";
+					arm,vexpress-sysreg,func = <0x7 0x0>;
+				};
+
+				dvimode {
+					compatible = "arm,vexpress-dvimode";
+					arm,vexpress-sysreg,func = <0xb 0x0>;
+				};
+			};
+		};
+	};
+
+	panels {
+
+		panel {
+			compatible = "panel";
+			mode = "XVGA";
+			refresh = <0x3c>;
+			xres = <0x400>;
+			yres = <0x300>;
+			pixclock = <0x3d84>;
+			left_margin = <0x98>;
+			right_margin = <0x30>;
+			upper_margin = <0x17>;
+			lower_margin = <0x3>;
+			hsync_len = <0x68>;
+			vsync_len = <0x4>;
+			sync = <0x0>;
+			vmode = "FB_VMODE_NONINTERLACED";
+			tim2 = "TIM2_BCD", "TIM2_IPC";
+			cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
+			caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
+			bpp = <0x10>;
+		};
+	};
+
+	chosen {
+		linux,initrd-start = <0x84000000>;
+		linux,initrd-end = <0x85e2a800>;
+		stdout-path = "serial0:115200n8";
+		bootargs = "cpuidle.off=1";
+	};
+
+	hypervisor {
+		compatible = "hafnium,hafnium";
+
+		vm1 {
+			debug_name = "linux_test";
+			kernel_filename = "vmlinuz";
+			ramdisk_filename = "initrd.img";
+			uuid = <0x0 0x0 0x0 0x1>;
+			messaging_method = <0x2>;
+			smc_whitelist_permissive;
+		};
+	};
+};
diff --git a/fdts/normal_world_single.dts b/fdts/normal_world_single.dts
new file mode 100644
index 000000000..9f260df9a
--- /dev/null
+++ b/fdts/normal_world_single.dts
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/memreserve/	0x0000000080000000 0x0000000000010000;
+/ {
+	model = "FVP Base";
+	compatible = "arm,vfp-base", "arm,vexpress";
+	interrupt-parent = <0x1>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	chosen {
+		linux,initrd-start = <0x84000000>;
+		linux,initrd-end = <0x85e2a800>;
+		stdout-path = "serial0:115200n8";
+		bootargs = "cpuidle.off=1";
+	};
+
+	aliases {
+		serial0 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@90000";
+		serial1 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@a0000";
+		serial2 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@b0000";
+		serial3 = "/smb@0,0/motherboard/iofpga@3,00000000/uart@c0000";
+	};
+
+	firmware {
+
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "ffa";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+		method = "smc";
+		cpu_suspend = <0xc4000001>;
+		cpu_off = <0x84000002>;
+		cpu_on = <0xc4000003>;
+		sys_poweroff = <0x84000008>;
+		sys_reset = <0x84000009>;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu-map {
+
+			cluster0 {
+
+				core0 {
+					cpu = <0x2>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "arm,psci";
+
+			cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x10000>;
+				entry-latency-us = <0x28>;
+				exit-latency-us = <0x64>;
+				min-residency-us = <0x96>;
+				phandle = <0xa>;
+			};
+
+			cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x1010000>;
+				entry-latency-us = <0x1f4>;
+				exit-latency-us = <0x3e8>;
+				min-residency-us = <0x9c4>;
+				phandle = <0xb>;
+			};
+		};
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <0xa 0xb>;
+			next-level-cache = <0xc>;
+			phandle = <0x2>;
+		};
+
+		l2-cache0 {
+			compatible = "cache";
+			phandle = <0xc>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x7f000000 0x8 0x80000000 0x0 0x80000000>;
+	};
+
+	interrupt-controller@2f000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <0x3>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+		interrupt-controller;
+		reg = <0x0 0x2f000000 0x0 0x10000 0x0 0x2f100000 0x0 0x200000 0x0 0x2c000000 0x0 0x2000 0x0 0x2c010000 0x0 0x2000 0x0 0x2c02f000 0x0 0x2000>;
+		interrupts = <0x1 0x9 0x4>;
+		phandle = <0x1>;
+
+		its@2f020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2f020000 0x0 0x20000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
+		clock-frequency = <0x5f5e100>;
+	};
+
+	timer@2a810000 {
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x0 0x2a810000 0x0 0x10000>;
+		clock-frequency = <0x5f5e100>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		frame@2a830000 {
+			frame-number = <0x1>;
+			interrupts = <0x0 0x1a 0x4>;
+			reg = <0x0 0x2a830000 0x0 0x10000>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4 0x0 0x3f 0x4>;
+	};
+
+	smb@0,0 {
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		ranges = <0x0 0x0 0x0 0x8000000 0x4000000 0x1 0x0 0x0 0x14000000 0x4000000 0x2 0x0 0x0 0x18000000 0x4000000 0x3 0x0 0x0 0x1c000000 0x4000000 0x4 0x0 0x0 0xc000000 0x4000000 0x5 0x0 0x0 0x10000000 0x4000000>;
+
+		motherboard {
+			arm,v2m-memory-map = "rs1";
+			compatible = "arm,vexpress,v2m-p1", "simple-bus";
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			ranges;
+
+			flash@0,00000000 {
+				compatible = "arm,vexpress-flash", "cfi-flash";
+				reg = <0x0 0x0 0x4000000 0x4 0x0 0x4000000>;
+				bank-width = <0x4>;
+			};
+
+			vram@2,00000000 {
+				compatible = "arm,vexpress-vram";
+				reg = <0x2 0x0 0x800000>;
+			};
+
+			ethernet@2,02000000 {
+				compatible = "smsc,lan91c111";
+				reg = <0x2 0x2000000 0x10000>;
+				interrupts = <0x0 0xf 0x4>;
+			};
+
+			clk24mhz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x16e3600>;
+				clock-output-names = "v2m:clk24mhz";
+				phandle = <0xf>;
+			};
+
+			refclk1mhz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0xf4240>;
+				clock-output-names = "v2m:refclk1mhz";
+				phandle = <0xe>;
+			};
+
+			refclk32khz {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x8000>;
+				clock-output-names = "v2m:refclk32khz";
+				phandle = <0xd>;
+			};
+
+			iofpga@3,00000000 {
+				compatible = "arm,amba-bus", "simple-bus";
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				ranges = <0x0 0x3 0x0 0x200000>;
+
+				sysreg@10000 {
+					compatible = "arm,vexpress-sysreg";
+					reg = <0x10000 0x1000>;
+					gpio-controller;
+					#gpio-cells = <0x2>;
+					phandle = <0x10>;
+				};
+
+				sysctl@20000 {
+					compatible = "arm,sp810", "arm,primecell";
+					reg = <0x20000 0x1000>;
+					clocks = <0xd 0xe 0xf>;
+					clock-names = "refclk", "timclk", "apb_pclk";
+					#clock-cells = <0x1>;
+					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+					phandle = <0x12>;
+				};
+
+				aaci@40000 {
+					compatible = "arm,pl041", "arm,primecell";
+					reg = <0x40000 0x1000>;
+					interrupts = <0x0 0xb 0x4>;
+					clocks = <0xf>;
+					clock-names = "apb_pclk";
+				};
+
+				mmci@50000 {
+					compatible = "arm,pl180", "arm,primecell";
+					reg = <0x50000 0x1000>;
+					interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
+					cd-gpios = <0x10 0x0 0x0>;
+					wp-gpios = <0x10 0x1 0x0>;
+					max-frequency = <0xb71b00>;
+					vmmc-supply = <0x11>;
+					clocks = <0xf 0xf>;
+					clock-names = "mclk", "apb_pclk";
+				};
+
+				kmi@60000 {
+					compatible = "arm,pl050", "arm,primecell";
+					reg = <0x60000 0x1000>;
+					interrupts = <0x0 0xc 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "KMIREFCLK", "apb_pclk";
+				};
+
+				kmi@70000 {
+					compatible = "arm,pl050", "arm,primecell";
+					reg = <0x70000 0x1000>;
+					interrupts = <0x0 0xd 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "KMIREFCLK", "apb_pclk";
+				};
+
+				uart@90000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0x90000 0x1000>;
+					interrupts = <0x0 0x5 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@a0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xa0000 0x1000>;
+					interrupts = <0x0 0x6 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@b0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xb0000 0x1000>;
+					interrupts = <0x0 0x7 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				uart@c0000 {
+					compatible = "arm,pl011", "arm,primecell";
+					reg = <0xc0000 0x1000>;
+					interrupts = <0x0 0x8 0x4>;
+					clocks = <0xf 0xf>;
+					clock-names = "uartclk", "apb_pclk";
+				};
+
+				wdt@f0000 {
+					compatible = "arm,sp805", "arm,primecell";
+					reg = <0xf0000 0x1000>;
+					interrupts = <0x0 0x0 0x4>;
+					clocks = <0xd 0xf>;
+					clock-names = "wdogclk", "apb_pclk";
+				};
+
+				timer@110000 {
+					compatible = "arm,sp804", "arm,primecell";
+					reg = <0x110000 0x1000>;
+					interrupts = <0x0 0x2 0x4>;
+					clocks = <0x12 0x0 0x12 0x1 0xf>;
+					clock-names = "timclken1", "timclken2", "apb_pclk";
+				};
+
+				timer@120000 {
+					compatible = "arm,sp804", "arm,primecell";
+					reg = <0x120000 0x1000>;
+					interrupts = <0x0 0x3 0x4>;
+					clocks = <0x12 0x2 0x12 0x3 0xf>;
+					clock-names = "timclken1", "timclken2", "apb_pclk";
+				};
+
+				rtc@170000 {
+					compatible = "arm,pl031", "arm,primecell";
+					reg = <0x170000 0x1000>;
+					interrupts = <0x0 0x4 0x4>;
+					clocks = <0xf>;
+					clock-names = "apb_pclk";
+				};
+
+				clcd@1f0000 {
+					compatible = "arm,pl111", "arm,primecell";
+					reg = <0x1f0000 0x1000>;
+					interrupts = <0x0 0xe 0x4>;
+					clocks = <0x13 0xf>;
+					clock-names = "clcdclk", "apb_pclk";
+					mode = "XVGA";
+					use_dma = <0x0>;
+					framebuffer = <0x18000000 0x180000>;
+				};
+
+				virtio_block@130000 {
+					compatible = "virtio,mmio";
+					reg = <0x130000 0x1000>;
+					interrupts = <0x0 0x2a 0x4>;
+				};
+			};
+
+			fixedregulator {
+				compatible = "regulator-fixed";
+				regulator-name = "3V3";
+				regulator-min-microvolt = <0x325aa0>;
+				regulator-max-microvolt = <0x325aa0>;
+				regulator-always-on;
+				phandle = <0x11>;
+			};
+
+			mcc {
+				compatible = "arm,vexpress,config-bus", "simple-bus";
+				arm,vexpress,config-bridge = <0x10>;
+
+				osc {
+					compatible = "arm,vexpress-osc";
+					arm,vexpress-sysreg,func = <0x1 0x1>;
+					freq-range = <0x16a6570 0x3c8eee0>;
+					#clock-cells = <0x0>;
+					clock-output-names = "v2m:oscclk1";
+					phandle = <0x13>;
+				};
+
+				muxfpga {
+					compatible = "arm,vexpress-muxfpga";
+					arm,vexpress-sysreg,func = <0x7 0x0>;
+				};
+
+				dvimode {
+					compatible = "arm,vexpress-dvimode";
+					arm,vexpress-sysreg,func = <0xb 0x0>;
+				};
+			};
+		};
+	};
+
+	panels {
+
+		panel {
+			compatible = "panel";
+			mode = "XVGA";
+			refresh = <0x3c>;
+			xres = <0x400>;
+			yres = <0x300>;
+			pixclock = <0x3d84>;
+			left_margin = <0x98>;
+			right_margin = <0x30>;
+			upper_margin = <0x17>;
+			lower_margin = <0x3>;
+			hsync_len = <0x68>;
+			vsync_len = <0x4>;
+			sync = <0x0>;
+			vmode = "FB_VMODE_NONINTERLACED";
+			tim2 = "TIM2_BCD", "TIM2_IPC";
+			cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
+			caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
+			bpp = <0x10>;
+		};
+	};
+
+	hypervisor {
+		compatible = "hafnium,hafnium";
+
+		vm1 {
+			debug_name = "linux_test";
+			kernel_filename = "vmlinuz";
+			ramdisk_filename = "initrd.img";
+			uuid = <0x0 0x0 0x0 0x1>;
+			messaging_method = <0x2>;
+			smc_whitelist_permissive;
+		};
+	};
+};
diff --git a/fdts/secure_world_dt.dts b/fdts/secure_world_dt.dts
new file mode 100644
index 000000000..50b1cc73e
--- /dev/null
+++ b/fdts/secure_world_dt.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "arm,spmc_rd";
+
+	attribute {
+		maj_ver = <0x0>;
+		min_ver = <0x9>;
+		runtime_el = <0x2>;
+		exec_state = <0x0>;
+		load_address = <0x0 0x6000000>;
+		entrypoint = <0x0 0x6000000>;
+
+		/* State the register where the dtb is passed */
+		spm_init_register = "0";
+	};
+
+	chosen {
+		optee,initrd-start = <0xA000000>;
+		optee,initrd-end = <0xB000000>;
+
+		linux,initrd-start = <0xA000000>;
+		linux,initrd-end = <0xF000000>;
+		stdout-path = "serial0:115200n8";
+		bootargs =  "";
+	};
+
+	hypervisor {
+		compatible = "hafnium,hafnium";
+		vm32769 {
+			debug_name = "OPTEE_HF";
+			kernel_filename = "optee";
+			ramdisk_filename = "initrd.img";
+			uuid = <0x486178E0 0xE7F811E3 0xBC5E0002 0xA5D5C51B>;
+			messaging_method = <0x2>;
+		};
+		vm32770 {
+			debug_name = "BARE_SP";
+			vcpu_count = <1>;
+			mem_size = <0x100000>;
+			kernel_filename = "bare_metal_sp";
+			ramdisk_filename = "initrd.img";
+			uuid = <0x1 0x1 0x1 0x1>;
+			messaging_method = <0x2>;
+		};
+
+	};
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x0 0x7ffffff 0x1c090000 0x1c0A0000>;
+	};
+};