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| author | Bipin Ravi <bipin.ravi@arm.com> | 2022-06-08 15:27:00 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2022-06-16 12:23:53 -0500 |
| commit | 7bf1a7aaaa41034587e43d5805b42da83090b85b (patch) | |
| tree | bc1247da9e5ebc9afd38134a264673fbe01f1d73 /include/lib/cpus | |
| parent | 65a5e1c04df56dbc0feb270fbae13c884020a5b9 (diff) | |
| download | arm-trusted-firmware-7bf1a7aaaa41034587e43d5805b42da83090b85b.tar.gz | |
fix(errata): workaround for Cortex-A77 erratum 2356587
Cortex-A77 erratum 2356587 is a cat B erratum that applies to revisions
r0p0 - r1p1 and is still open. The workaround is to set bit[0] of
CPUACTLR2_EL1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not
cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I243cfd587bca06ffd2a7be5bce28f8d2c5e68230
Diffstat (limited to 'include/lib/cpus')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a77.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index 4a871689c..63f155f7b 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -32,6 +32,7 @@ ******************************************************************************/ #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 |