diff options
Diffstat (limited to 'docs/getting_started/build-options.rst')
| -rw-r--r-- | docs/getting_started/build-options.rst | 51 |
1 files changed, 33 insertions, 18 deletions
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index d2f463fab..4eafb392b 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -436,17 +436,24 @@ Common build options (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure - world to trap to EL3. SME is an optional architectural feature for AArch64 + world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a + superset of SVE. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. Default is 0. +- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension + version 2 (SME2) for the non-secure world only. SME2 is an optional + architectural feature for AArch64 and TF-A support is experimental. + This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME + accesses will still be trapped. This flag can take the values 0 to 2, to + align with the ``FEATURE_DETECTION`` mechanism. Default is 0. + - ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix - Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS - must also be set to use this. If enabling this, the secure world MUST - handle context switching for SME, SVE, and FPU/SIMD registers to ensure that - no data is leaked to non-secure world. This is experimental. Default is 0. + Extension for secure world. Used along with SVE and FPU/SIMD. + ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. + This is experimental. Default is 0. - ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. @@ -462,17 +469,15 @@ Common build options This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an - assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled. - This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` - mechanism. The default is 2 but is automatically disabled when - ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE. - At this time, this build option cannot be used on systems that have SPM_MM - enabled. + assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` + enabled. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be + used on systems that have SPM_MM enabled. The default is 1. - ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option - requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it - is automatically disabled when the target architecture is AArch32. + requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is + automatically disabled when the target architecture is AArch32. - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The @@ -633,6 +638,10 @@ Common build options translation library (xlat tables v2) must be used; version 1 of translation library is not supported. +- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for + implementation defined system register accesses from lower ELs. Default + value is ``0``. + - ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the bottom, higher addresses at the top. This build flag can be set to '1' to invert this behavior. Lower addresses will be printed at the top and higher @@ -766,15 +775,14 @@ Common build options - ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI OS-initiated mode. This option defaults to 0. -- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features +- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. - When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be - set to ``1``. - - This option is disabled by default. +- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors + originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, + ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 @@ -1121,6 +1129,13 @@ Common build options means platform hook won't be checked and CMOs will always be performed when related functions are called. +- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management + firmware interface for the BL31 image. By default its disabled (``0``). + +- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the + errata mitigation for platforms with a non-arm interconnect using the errata + ABI. By default its disabled (``0``). + GICv3 driver options -------------------- |