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-rw-r--r--lib/cpus/cpu-ops.mk43
-rw-r--r--lib/debugfs/debugfs_smc.c2
-rw-r--r--lib/el3_runtime/aarch64/context.S37
-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c20
-rw-r--r--lib/optee/optee_utils.c2
-rw-r--r--lib/xlat_tables/aarch32/nonlpae_tables.c2
-rw-r--r--lib/xlat_tables/xlat_tables_common.c2
-rw-r--r--lib/xlat_tables_v2/xlat_tables_core.c2
-rw-r--r--lib/xlat_tables_v2/xlat_tables_utils.c2
9 files changed, 69 insertions, 43 deletions
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 82a4890cf..e16c8e495 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -324,6 +324,11 @@ CPU_FLAG_LIST += ERRATA_A78_2376745
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78_2395406
+# Flag to apply erratum 2712571 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu.
+# It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A78_2712571
+
# Flag to apply erratum 2742426 workaround during reset. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
# open.
@@ -362,6 +367,11 @@ CPU_FLAG_LIST += ERRATA_A78C_1827430
# to revision r0p0 of the A78C cpu. It is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A78C_1827440
+# Flag to apply erratum 2712574 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_A78_AE_2712574
+
# Flag to apply erratum 2132064 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2132064
@@ -378,6 +388,11 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2395411
+# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p1 and r0p2 of the A78C cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_A78C_2712575
+
# Flag to apply erratum 2772121 workaround during powerdown. This erratum
# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2772121
@@ -509,6 +524,11 @@ CPU_FLAG_LIST += ERRATA_V1_2294912
# to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V1_2372203
+# Flag to apply erratum 2701953 workaround to non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r1p1 of the Neoverse V1 cpu,
+# it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_V1_2701953
+
# Flag to apply erratum 2743093 workaround during powerdown. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
# still open.
@@ -581,6 +601,11 @@ CPU_FLAG_LIST += ERRATA_A710_2008768
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
CPU_FLAG_LIST += ERRATA_A710_2371105
+# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This
+# erratum applies to revision r0p0, r1p0, r2p0, r2p1 of the Cortex-A710 cpu
+# and is still open.
+CPU_FLAG_LIST += ERRATA_A710_2701952
+
# Flag to apply erratum 2768515 workaround during power down. This erratum
# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is
# still open.
@@ -638,6 +663,11 @@ CPU_FLAG_LIST += ERRATA_N2_2376738
# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2388450
+# Flag to apply erratum 2728475 workaround for non-arm interconnect ip. This
+# erratum applies to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in
+# r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2728475
+
# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
@@ -682,6 +712,11 @@ CPU_FLAG_LIST += ERRATA_X2_2282622
# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
CPU_FLAG_LIST += ERRATA_X2_2371105
+# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-x2 cpu
+# and is still open.
+CPU_FLAG_LIST += ERRATA_X2_2701952
+
# Flag to apply erratum 2768515 workaround during power down. This erratum
# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is
# still open.
@@ -743,6 +778,14 @@ CPU_FLAG_LIST += ERRATA_A510_2666669
# Cortex-A510 cpu and is fixed in r1p3.
CPU_FLAG_LIST += ERRATA_A510_2684597
+# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, rop1. Fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2719103
+
+# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
+# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A715_2701951
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c
index 400c166d7..13ced3db1 100644
--- a/lib/debugfs/debugfs_smc.c
+++ b/lib/debugfs/debugfs_smc.c
@@ -54,7 +54,7 @@ static union debugfs_parms {
} parms;
/* debugfs_access_lock protects shared buffer and internal */
-/* FS functions from concurrent acccesses. */
+/* FS functions from concurrent accesses. */
static spinlock_t debugfs_access_lock;
static bool debugfs_initialized;
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 456ed5113..9922fb147 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -17,10 +17,6 @@
.global el2_sysregs_context_save_mte
.global el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if RAS_EXTENSION
- .global el2_sysregs_context_save_ras
- .global el2_sysregs_context_restore_ras
-#endif /* RAS_EXTENSION */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -210,30 +206,6 @@ func el2_sysregs_context_restore_mte
endfunc el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if RAS_EXTENSION
-func el2_sysregs_context_save_ras
- /*
- * VDISR_EL2 and VSESR_EL2 registers are saved only when
- * FEAT_RAS is supported.
- */
- mrs x11, vdisr_el2
- mrs x12, vsesr_el2
- stp x11, x12, [x0, #CTX_VDISR_EL2]
- ret
-endfunc el2_sysregs_context_save_ras
-
-func el2_sysregs_context_restore_ras
- /*
- * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS
- * is supported.
- */
- ldp x11, x12, [x0, #CTX_VDISR_EL2]
- msr vdisr_el2, x11
- msr vsesr_el2, x12
- ret
-endfunc el2_sysregs_context_restore_ras
-#endif /* RAS_EXTENSION */
-
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
@@ -796,7 +768,12 @@ sve_not_enabled:
1:
#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */
-#if IMAGE_BL31 && RAS_EXTENSION
+/*
+ * This is a hot path, so we don't want to do some actual FEAT_RAS runtime
+ * detection here. The "esb" is a cheaper variant, so using "dsb" in the
+ * ENABLE_FEAT_RAS==2 case is not ideal, but won't hurt.
+ */
+#if IMAGE_BL31 && ENABLE_FEAT_RAS == 1
/* ----------------------------------------------------------
* Issue Error Synchronization Barrier to synchronize SErrors
* before exiting EL3. We're running with EAs unmasked, so
@@ -807,7 +784,7 @@ sve_not_enabled:
esb
#else
dsb sy
-#endif /* IMAGE_BL31 && RAS_EXTENSION */
+#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */
/* ----------------------------------------------------------
* Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 744e4f910..3760b8f13 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -457,7 +457,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e
void __init cm_init(void)
{
/*
- * The context management library has only global data to intialize, but
+ * The context management library has only global data to initialize, but
* that will be done when the BSS is zeroed out.
*/
}
@@ -1013,9 +1013,13 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2,
read_ttbr1_el2());
}
-#if RAS_EXTENSION
- el2_sysregs_context_save_ras(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_ras_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2,
+ read_vdisr_el2());
+ write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2,
+ read_vsesr_el2());
+ }
if (is_feat_nv2_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2,
@@ -1096,9 +1100,11 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2));
write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2));
}
-#if RAS_EXTENSION
- el2_sysregs_context_restore_ras(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_ras_supported()) {
+ write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2));
+ write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2));
+ }
if (is_feat_nv2_supported()) {
write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 25272fc94..6641db9af 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -180,7 +180,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
/*
* Update "pc" value which should comes from pager image. After the
- * header image is parsed, it will be unuseful, and the actual
+ * header image is parsed, it will be useless, and the actual
* execution image after BL31 is pager image.
*/
header_ep->pc = pager_image_info->image_base;
diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index 5646f347c..f58240470 100644
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -272,7 +272,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
/* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
- /* Check we haven't lost the empty sentinal from the end of the array */
+ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U);
mm->base_pa = base_pa;
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index 71273cb97..e2c8370e2 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -161,7 +161,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
/* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
- /* Check we haven't lost the empty sentinal from the end of the array */
+ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U);
mm->base_pa = base_pa;
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index de5718454..3a9c0588d 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -988,7 +988,7 @@ int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm)
(uintptr_t)mm_last - (uintptr_t)mm_cursor);
/*
- * Check we haven't lost the empty sentinal from the end of the array.
+ * Check we haven't lost the empty sentinel from the end of the array.
* This shouldn't happen as we have checked in mmap_add_region_check
* that there is free space.
*/
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index 38a375edf..f3a53ccd3 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -585,7 +585,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
base_va += PAGE_SIZE;
}
- /* Ensure that the last descriptor writen is seen by the system. */
+ /* Ensure that the last descriptor written is seen by the system. */
dsbish();
return 0;
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