diff options
Diffstat (limited to 'plat/ti/k3/board/lite/include/board_def.h')
| -rw-r--r-- | plat/ti/k3/board/lite/include/board_def.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h index 7c7ea62c1..18b7f4206 100644 --- a/plat/ti/k3/board/lite/include/board_def.h +++ b/plat/ti/k3/board/lite/include/board_def.h @@ -20,15 +20,26 @@ * It may need to be increased if BL31 grows in size. * Current computation assumes data structures necessary for GIC and ARM for * a single cluster of 4 processor. + * + * The link addresses are determined by SEC_SRAM_BASE + offset. + * When ENABLE_PIE is set, the TF images can be loaded anywhere, so + * SEC_SRAM_BASE is really arbitrary. + * + * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that + * it matches to the physical address where BL31 is loaded, that is, + * SEC_SRAM_BASE should be the base address of the RAM region. + * + * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is + * defined as default for our platform. */ -#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */ -#define SEC_SRAM_SIZE 0x0001a000 /* 104k */ +#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ +#define SEC_SRAM_SIZE UL(0x0001c000) /* 112k */ #define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_RET_STATE U(1) -#define PLAT_PROC_START_ID 32 -#define PLAT_PROC_DEVICE_START_ID 135 -#define PLAT_CLUSTER_DEVICE_START_ID 134 +#define PLAT_PROC_START_ID U(32) +#define PLAT_PROC_DEVICE_START_ID U(135) +#define PLAT_CLUSTER_DEVICE_START_ID U(134) #endif /* BOARD_DEF_H */ |