diff options
Diffstat (limited to 'plat/xilinx/zynqmp/pm_service')
-rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 100 | ||||
-rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 420 | ||||
-rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c | 2 | ||||
-rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h | 122 | ||||
-rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_api_sys.h | 2 |
5 files changed, 323 insertions, 323 deletions
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 0099070f7..ec1ea78c0 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -21,51 +21,51 @@ #include "pm_common.h" #include "pm_ipi.h" -#define CLK_NODE_MAX U(6) - -#define CLK_PARENTS_ID_LEN U(16) -#define CLK_TOPOLOGY_NODE_OFFSET U(16) -#define CLK_TOPOLOGY_PAYLOAD_LEN U(12) -#define CLK_PARENTS_PAYLOAD_LEN U(12) -#define CLK_TYPE_SHIFT U(2) -#define CLK_CLKFLAGS_SHIFT U(8) -#define CLK_TYPEFLAGS_SHIFT U(24) -#define CLK_TYPEFLAGS2_SHIFT U(4) -#define CLK_TYPEFLAGS_BITS_MASK U(0xFF) -#define CLK_TYPEFLAGS2_BITS_MASK U(0x0F00) -#define CLK_TYPEFLAGS_BITS U(8) +#define CLK_NODE_MAX (6U) + +#define CLK_PARENTS_ID_LEN (16U) +#define CLK_TOPOLOGY_NODE_OFFSET (16U) +#define CLK_TOPOLOGY_PAYLOAD_LEN (12U) +#define CLK_PARENTS_PAYLOAD_LEN (12U) +#define CLK_TYPE_SHIFT (2U) +#define CLK_CLKFLAGS_SHIFT (8U) +#define CLK_TYPEFLAGS_SHIFT (24U) +#define CLK_TYPEFLAGS2_SHIFT (4U) +#define CLK_TYPEFLAGS_BITS_MASK (0xFFU) +#define CLK_TYPEFLAGS2_BITS_MASK (0x0F00U) +#define CLK_TYPEFLAGS_BITS (8U) #define CLK_EXTERNAL_PARENT (PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN) -#define NA_MULT U(0) -#define NA_DIV U(0) -#define NA_SHIFT U(0) -#define NA_WIDTH U(0) -#define NA_CLK_FLAGS U(0) -#define NA_TYPE_FLAGS U(0) +#define NA_MULT (0U) +#define NA_DIV (0U) +#define NA_SHIFT (0U) +#define NA_WIDTH (0U) +#define NA_CLK_FLAGS (0U) +#define NA_TYPE_FLAGS (0U) /* PLL nodes related definitions */ -#define PLL_PRESRC_MUX_SHIFT U(20) -#define PLL_PRESRC_MUX_WIDTH U(3) -#define PLL_POSTSRC_MUX_SHIFT U(24) -#define PLL_POSTSRC_MUX_WIDTH U(3) -#define PLL_DIV2_MUX_SHIFT U(16) -#define PLL_DIV2_MUX_WIDTH U(1) -#define PLL_BYPASS_MUX_SHIFT U(3) -#define PLL_BYPASS_MUX_WIDTH U(1) +#define PLL_PRESRC_MUX_SHIFT (20U) +#define PLL_PRESRC_MUX_WIDTH (3U) +#define PLL_POSTSRC_MUX_SHIFT (24U) +#define PLL_POSTSRC_MUX_WIDTH (3U) +#define PLL_DIV2_MUX_SHIFT (16U) +#define PLL_DIV2_MUX_WIDTH (1U) +#define PLL_BYPASS_MUX_SHIFT (3U) +#define PLL_BYPASS_MUX_WIDTH (1U) /* Peripheral nodes related definitions */ /* Peripheral Clocks */ -#define PERIPH_MUX_SHIFT U(0) -#define PERIPH_MUX_WIDTH U(3) -#define PERIPH_DIV1_SHIFT U(8) -#define PERIPH_DIV1_WIDTH U(6) -#define PERIPH_DIV2_SHIFT U(16) -#define PERIPH_DIV2_WIDTH U(6) -#define PERIPH_GATE_SHIFT U(24) -#define PERIPH_GATE_WIDTH U(1) +#define PERIPH_MUX_SHIFT (0U) +#define PERIPH_MUX_WIDTH (3U) +#define PERIPH_DIV1_SHIFT (8U) +#define PERIPH_DIV1_WIDTH (6U) +#define PERIPH_DIV2_SHIFT (16U) +#define PERIPH_DIV2_WIDTH (6U) +#define PERIPH_GATE_SHIFT (24U) +#define PERIPH_GATE_WIDTH (1U) -#define USB_GATE_SHIFT U(25) +#define USB_GATE_SHIFT (25U) /* External clock related definitions */ @@ -87,20 +87,20 @@ #define PLLCTRL_BP_MASK BIT(3) -#define PLLCTRL_RESET_MASK U(1) -#define PLL_FRAC_OFFSET U(8) -#define PLL_FRAC_MODE U(1) -#define PLL_INT_MODE U(0) -#define PLL_FRAC_MODE_MASK U(0x80000000) -#define PLL_FRAC_MODE_SHIFT U(31) -#define PLL_FRAC_DATA_MASK U(0xFFFF) -#define PLL_FRAC_DATA_SHIFT U(0) -#define PLL_FBDIV_MASK U(0x7F00) -#define PLL_FBDIV_WIDTH U(7) -#define PLL_FBDIV_SHIFT U(8) - -#define CLK_PLL_RESET_ASSERT U(1) -#define CLK_PLL_RESET_RELEASE U(2) +#define PLLCTRL_RESET_MASK (1U) +#define PLL_FRAC_OFFSET (8U) +#define PLL_FRAC_MODE (1U) +#define PLL_INT_MODE (0U) +#define PLL_FRAC_MODE_MASK (0x80000000U) +#define PLL_FRAC_MODE_SHIFT (31U) +#define PLL_FRAC_DATA_MASK (0xFFFFU) +#define PLL_FRAC_DATA_SHIFT (0U) +#define PLL_FBDIV_MASK (0x7F00U) +#define PLL_FBDIV_WIDTH (7U) +#define PLL_FBDIV_SHIFT (8U) + +#define CLK_PLL_RESET_ASSERT (1U) +#define CLK_PLL_RESET_RELEASE (2U) #define CLK_PLL_RESET_PULSE (CLK_PLL_RESET_ASSERT | CLK_PLL_RESET_RELEASE) /* Common topology definitions */ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index db476e829..cc0daccdf 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -57,224 +57,224 @@ //CLock Ids enum clock_id { - CLK_IOPLL, - CLK_RPLL, - CLK_APLL, - CLK_DPLL, - CLK_VPLL, - CLK_IOPLL_TO_FPD, - CLK_RPLL_TO_FPD, - CLK_APLL_TO_LPD, - CLK_DPLL_TO_LPD, - CLK_VPLL_TO_LPD, - CLK_ACPU, - CLK_ACPU_HALF, - CLK_DBG_FPD, - CLK_DBG_LPD, - CLK_DBG_TRACE, - CLK_DBG_TSTMP, - CLK_DP_VIDEO_REF, - CLK_DP_AUDIO_REF, - CLK_DP_STC_REF, - CLK_GDMA_REF, - CLK_DPDMA_REF, - CLK_DDR_REF, - CLK_SATA_REF, - CLK_PCIE_REF, - CLK_GPU_REF, - CLK_GPU_PP0_REF, - CLK_GPU_PP1_REF, - CLK_TOPSW_MAIN, - CLK_TOPSW_LSBUS, - CLK_GTGREF0_REF, - CLK_LPD_SWITCH, - CLK_LPD_LSBUS, - CLK_USB0_BUS_REF, - CLK_USB1_BUS_REF, - CLK_USB3_DUAL_REF, - CLK_USB0, - CLK_USB1, - CLK_CPU_R5, - CLK_CPU_R5_CORE, - CLK_CSU_SPB, - CLK_CSU_PLL, - CLK_PCAP, - CLK_IOU_SWITCH, - CLK_GEM_TSU_REF, - CLK_GEM_TSU, - CLK_GEM0_TX, - CLK_GEM1_TX, - CLK_GEM2_TX, - CLK_GEM3_TX, - CLK_GEM0_RX, - CLK_GEM1_RX, - CLK_GEM2_RX, - CLK_GEM3_RX, - CLK_QSPI_REF, - CLK_SDIO0_REF, - CLK_SDIO1_REF, - CLK_UART0_REF, - CLK_UART1_REF, - CLK_SPI0_REF, - CLK_SPI1_REF, - CLK_NAND_REF, - CLK_I2C0_REF, - CLK_I2C1_REF, - CLK_CAN0_REF, - CLK_CAN1_REF, - CLK_CAN0, - CLK_CAN1, - CLK_DLL_REF, - CLK_ADMA_REF, - CLK_TIMESTAMP_REF, - CLK_AMS_REF, - CLK_PL0_REF, - CLK_PL1_REF, - CLK_PL2_REF, - CLK_PL3_REF, - CLK_FPD_WDT, - CLK_IOPLL_INT, - CLK_IOPLL_PRE_SRC, - CLK_IOPLL_HALF, - CLK_IOPLL_INT_MUX, - CLK_IOPLL_POST_SRC, - CLK_RPLL_INT, - CLK_RPLL_PRE_SRC, - CLK_RPLL_HALF, - CLK_RPLL_INT_MUX, - CLK_RPLL_POST_SRC, - CLK_APLL_INT, - CLK_APLL_PRE_SRC, - CLK_APLL_HALF, - CLK_APLL_INT_MUX, - CLK_APLL_POST_SRC, - CLK_DPLL_INT, - CLK_DPLL_PRE_SRC, - CLK_DPLL_HALF, - CLK_DPLL_INT_MUX, - CLK_DPLL_POST_SRC, - CLK_VPLL_INT, - CLK_VPLL_PRE_SRC, - CLK_VPLL_HALF, - CLK_VPLL_INT_MUX, - CLK_VPLL_POST_SRC, - CLK_CAN0_MIO, - CLK_CAN1_MIO, - CLK_ACPU_FULL, - CLK_GEM0_REF, - CLK_GEM1_REF, - CLK_GEM2_REF, - CLK_GEM3_REF, - CLK_GEM0_REF_UNGATED, - CLK_GEM1_REF_UNGATED, - CLK_GEM2_REF_UNGATED, - CLK_GEM3_REF_UNGATED, - CLK_LPD_WDT, - END_OF_OUTPUT_CLKS, + CLK_IOPLL = (0U), + CLK_RPLL = (1U), + CLK_APLL = (2U), + CLK_DPLL = (3U), + CLK_VPLL = (4U), + CLK_IOPLL_TO_FPD = (5U), + CLK_RPLL_TO_FPD = (6U), + CLK_APLL_TO_LPD = (7U), + CLK_DPLL_TO_LPD = (8U), + CLK_VPLL_TO_LPD = (9U), + CLK_ACPU = (10U), + CLK_ACPU_HALF = (11U), + CLK_DBG_FPD = (12U), + CLK_DBG_LPD = (13U), + CLK_DBG_TRACE = (14U), + CLK_DBG_TSTMP = (15U), + CLK_DP_VIDEO_REF = (16U), + CLK_DP_AUDIO_REF = (17U), + CLK_DP_STC_REF = (18U), + CLK_GDMA_REF = (19U), + CLK_DPDMA_REF = (20U), + CLK_DDR_REF = (21U), + CLK_SATA_REF = (22U), + CLK_PCIE_REF = (23U), + CLK_GPU_REF = (24U), + CLK_GPU_PP0_REF = (25U), + CLK_GPU_PP1_REF = (26U), + CLK_TOPSW_MAIN = (27U), + CLK_TOPSW_LSBUS = (28U), + CLK_GTGREF0_REF = (29U), + CLK_LPD_SWITCH = (30U), + CLK_LPD_LSBUS = (31U), + CLK_USB0_BUS_REF = (32U), + CLK_USB1_BUS_REF = (33U), + CLK_USB3_DUAL_REF = (34U), + CLK_USB0 = (35U), + CLK_USB1 = (36U), + CLK_CPU_R5 = (37U), + CLK_CPU_R5_CORE = (38U), + CLK_CSU_SPB = (39U), + CLK_CSU_PLL = (40U), + CLK_PCAP = (41U), + CLK_IOU_SWITCH = (42U), + CLK_GEM_TSU_REF = (43U), + CLK_GEM_TSU = (44U), + CLK_GEM0_TX = (45U), + CLK_GEM1_TX = (46U), + CLK_GEM2_TX = (47U), + CLK_GEM3_TX = (48U), + CLK_GEM0_RX = (49U), + CLK_GEM1_RX = (50U), + CLK_GEM2_RX = (51U), + CLK_GEM3_RX = (52U), + CLK_QSPI_REF = (53U), + CLK_SDIO0_REF = (54U), + CLK_SDIO1_REF = (55U), + CLK_UART0_REF = (56U), + CLK_UART1_REF = (57U), + CLK_SPI0_REF = (58U), + CLK_SPI1_REF = (59U), + CLK_NAND_REF = (60U), + CLK_I2C0_REF = (61U), + CLK_I2C1_REF = (62U), + CLK_CAN0_REF = (63U), + CLK_CAN1_REF = (64U), + CLK_CAN0 = (65U), + CLK_CAN1 = (66U), + CLK_DLL_REF = (67U), + CLK_ADMA_REF = (68U), + CLK_TIMESTAMP_REF = (69U), + CLK_AMS_REF = (70U), + CLK_PL0_REF = (71U), + CLK_PL1_REF = (72U), + CLK_PL2_REF = (73U), + CLK_PL3_REF = (74U), + CLK_FPD_WDT = (75U), + CLK_IOPLL_INT = (76U), + CLK_IOPLL_PRE_SRC = (77U), + CLK_IOPLL_HALF = (78U), + CLK_IOPLL_INT_MUX = (79U), + CLK_IOPLL_POST_SRC = (80U), + CLK_RPLL_INT = (81U), + CLK_RPLL_PRE_SRC = (82U), + CLK_RPLL_HALF = (83U), + CLK_RPLL_INT_MUX = (84U), + CLK_RPLL_POST_SRC = (85U), + CLK_APLL_INT = (86U), + CLK_APLL_PRE_SRC = (87U), + CLK_APLL_HALF = (88U), + CLK_APLL_INT_MUX = (89U), + CLK_APLL_POST_SRC = (90U), + CLK_DPLL_INT = (91U), + CLK_DPLL_PRE_SRC = (92U), + CLK_DPLL_HALF = (93U), + CLK_DPLL_INT_MUX = (94U), + CLK_DPLL_POST_SRC = (95U), + CLK_VPLL_INT = (96U), + CLK_VPLL_PRE_SRC = (97U), + CLK_VPLL_HALF = (98U), + CLK_VPLL_INT_MUX = (99U), + CLK_VPLL_POST_SRC = (100U), + CLK_CAN0_MIO = (101U), + CLK_CAN1_MIO = (102U), + CLK_ACPU_FULL = (103U), + CLK_GEM0_REF = (104U), + CLK_GEM1_REF = (105U), + CLK_GEM2_REF = (106U), + CLK_GEM3_REF = (107U), + CLK_GEM0_REF_UNGATED = (108U), + CLK_GEM1_REF_UNGATED = (109U), + CLK_GEM2_REF_UNGATED = (110U), + CLK_GEM3_REF_UNGATED = (111U), + CLK_LPD_WDT = (112U), + END_OF_OUTPUT_CLKS = (113U), }; -#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS) +#define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS //External clock ids enum { EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS, - EXT_CLK_VIDEO, - EXT_CLK_PSS_ALT_REF, - EXT_CLK_AUX_REF, - EXT_CLK_GT_CRX_REF, - EXT_CLK_SWDT0, - EXT_CLK_SWDT1, - EXT_CLK_GEM0_TX_EMIO, - EXT_CLK_GEM1_TX_EMIO, - EXT_CLK_GEM2_TX_EMIO, - EXT_CLK_GEM3_TX_EMIO, - EXT_CLK_GEM0_RX_EMIO, - EXT_CLK_GEM1_RX_EMIO, - EXT_CLK_GEM2_RX_EMIO, - EXT_CLK_GEM3_RX_EMIO, - EXT_CLK_MIO50_OR_MIO51, - EXT_CLK_MIO0, - EXT_CLK_MIO1, - EXT_CLK_MIO2, - EXT_CLK_MIO3, - EXT_CLK_MIO4, - EXT_CLK_MIO5, - EXT_CLK_MIO6, - EXT_CLK_MIO7, - EXT_CLK_MIO8, - EXT_CLK_MIO9, - EXT_CLK_MIO10, - EXT_CLK_MIO11, - EXT_CLK_MIO12, - EXT_CLK_MIO13, - EXT_CLK_MIO14, - EXT_CLK_MIO15, - EXT_CLK_MIO16, - EXT_CLK_MIO17, - EXT_CLK_MIO18, - EXT_CLK_MIO19, - EXT_CLK_MIO20, - EXT_CLK_MIO21, - EXT_CLK_MIO22, - EXT_CLK_MIO23, - EXT_CLK_MIO24, - EXT_CLK_MIO25, - EXT_CLK_MIO26, - EXT_CLK_MIO27, - EXT_CLK_MIO28, - EXT_CLK_MIO29, - EXT_CLK_MIO30, - EXT_CLK_MIO31, - EXT_CLK_MIO32, - EXT_CLK_MIO33, - EXT_CLK_MIO34, - EXT_CLK_MIO35, - EXT_CLK_MIO36, - EXT_CLK_MIO37, - EXT_CLK_MIO38, - EXT_CLK_MIO39, - EXT_CLK_MIO40, - EXT_CLK_MIO41, - EXT_CLK_MIO42, - EXT_CLK_MIO43, - EXT_CLK_MIO44, - EXT_CLK_MIO45, - EXT_CLK_MIO46, - EXT_CLK_MIO47, - EXT_CLK_MIO48, - EXT_CLK_MIO49, - EXT_CLK_MIO50, - EXT_CLK_MIO51, - EXT_CLK_MIO52, - EXT_CLK_MIO53, - EXT_CLK_MIO54, - EXT_CLK_MIO55, - EXT_CLK_MIO56, - EXT_CLK_MIO57, - EXT_CLK_MIO58, - EXT_CLK_MIO59, - EXT_CLK_MIO60, - EXT_CLK_MIO61, - EXT_CLK_MIO62, - EXT_CLK_MIO63, - EXT_CLK_MIO64, - EXT_CLK_MIO65, - EXT_CLK_MIO66, - EXT_CLK_MIO67, - EXT_CLK_MIO68, - EXT_CLK_MIO69, - EXT_CLK_MIO70, - EXT_CLK_MIO71, - EXT_CLK_MIO72, - EXT_CLK_MIO73, - EXT_CLK_MIO74, - EXT_CLK_MIO75, - EXT_CLK_MIO76, - EXT_CLK_MIO77, - END_OF_CLKS, + EXT_CLK_VIDEO = (114U), + EXT_CLK_PSS_ALT_REF = (115U), + EXT_CLK_AUX_REF = (116U), + EXT_CLK_GT_CRX_REF = (117U), + EXT_CLK_SWDT0 = (118U), + EXT_CLK_SWDT1 = (119U), + EXT_CLK_GEM0_TX_EMIO = (120U), + EXT_CLK_GEM1_TX_EMIO = (121U), + EXT_CLK_GEM2_TX_EMIO = (122U), + EXT_CLK_GEM3_TX_EMIO = (123U), + EXT_CLK_GEM0_RX_EMIO = (124U), + EXT_CLK_GEM1_RX_EMIO = (125U), + EXT_CLK_GEM2_RX_EMIO = (126U), + EXT_CLK_GEM3_RX_EMIO = (127U), + EXT_CLK_MIO50_OR_MIO51 = (128U), + EXT_CLK_MIO0 = (129U), + EXT_CLK_MIO1 = (130U), + EXT_CLK_MIO2 = (131U), + EXT_CLK_MIO3 = (132U), + EXT_CLK_MIO4 = (133U), + EXT_CLK_MIO5 = (134U), + EXT_CLK_MIO6 = (135U), + EXT_CLK_MIO7 = (136U), + EXT_CLK_MIO8 = (137U), + EXT_CLK_MIO9 = (138U), + EXT_CLK_MIO10 = (139U), + EXT_CLK_MIO11 = (140U), + EXT_CLK_MIO12 = (141U), + EXT_CLK_MIO13 = (142U), + EXT_CLK_MIO14 = (143U), + EXT_CLK_MIO15 = (144U), + EXT_CLK_MIO16 = (145U), + EXT_CLK_MIO17 = (146U), + EXT_CLK_MIO18 = (147U), + EXT_CLK_MIO19 = (148U), + EXT_CLK_MIO20 = (149U), + EXT_CLK_MIO21 = (150U), + EXT_CLK_MIO22 = (151U), + EXT_CLK_MIO23 = (152U), + EXT_CLK_MIO24 = (153U), + EXT_CLK_MIO25 = (154U), + EXT_CLK_MIO26 = (155U), + EXT_CLK_MIO27 = (156U), + EXT_CLK_MIO28 = (157U), + EXT_CLK_MIO29 = (158U), + EXT_CLK_MIO30 = (159U), + EXT_CLK_MIO31 = (160U), + EXT_CLK_MIO32 = (161U), + EXT_CLK_MIO33 = (162U), + EXT_CLK_MIO34 = (163U), + EXT_CLK_MIO35 = (164U), + EXT_CLK_MIO36 = (165U), + EXT_CLK_MIO37 = (166U), + EXT_CLK_MIO38 = (167U), + EXT_CLK_MIO39 = (168U), + EXT_CLK_MIO40 = (169U), + EXT_CLK_MIO41 = (170U), + EXT_CLK_MIO42 = (171U), + EXT_CLK_MIO43 = (172U), + EXT_CLK_MIO44 = (173U), + EXT_CLK_MIO45 = (174U), + EXT_CLK_MIO46 = (175U), + EXT_CLK_MIO47 = (176U), + EXT_CLK_MIO48 = (177U), + EXT_CLK_MIO49 = (178U), + EXT_CLK_MIO50 = (179U), + EXT_CLK_MIO51 = (180U), + EXT_CLK_MIO52 = (181U), + EXT_CLK_MIO53 = (182U), + EXT_CLK_MIO54 = (183U), + EXT_CLK_MIO55 = (184U), + EXT_CLK_MIO56 = (185U), + EXT_CLK_MIO57 = (186U), + EXT_CLK_MIO58 = (187U), + EXT_CLK_MIO59 = (188U), + EXT_CLK_MIO60 = (189U), + EXT_CLK_MIO61 = (190U), + EXT_CLK_MIO62 = (191U), + EXT_CLK_MIO63 = (192U), + EXT_CLK_MIO64 = (193U), + EXT_CLK_MIO65 = (194U), + EXT_CLK_MIO66 = (195U), + EXT_CLK_MIO67 = (196U), + EXT_CLK_MIO68 = (197U), + EXT_CLK_MIO69 = (198U), + EXT_CLK_MIO70 = (199U), + EXT_CLK_MIO71 = (200U), + EXT_CLK_MIO72 = (201U), + EXT_CLK_MIO73 = (202U), + EXT_CLK_MIO74 = (203U), + EXT_CLK_MIO75 = (204U), + EXT_CLK_MIO76 = (205U), + EXT_CLK_MIO77 = (206U), + END_OF_CLKS = (207U), }; -#define CLK_MAX (unsigned int)(END_OF_CLKS) +#define CLK_MAX END_OF_CLKS //CLock types #define CLK_TYPE_OUTPUT 0U diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c index 945d06078..8f373418c 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c @@ -27,7 +27,7 @@ struct pinctrl_function { }; /* Max groups for one pin */ -#define MAX_PIN_GROUPS U(13) +#define MAX_PIN_GROUPS (13U) struct zynqmp_pin_group { uint16_t (*groups)[]; diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h index 1b46375c0..5c4cb4504 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h @@ -22,67 +22,67 @@ //pinctrl function ids enum { - PINCTRL_FUNC_CAN0, - PINCTRL_FUNC_CAN1, - PINCTRL_FUNC_ETHERNET0, - PINCTRL_FUNC_ETHERNET1, - PINCTRL_FUNC_ETHERNET2, - PINCTRL_FUNC_ETHERNET3, - PINCTRL_FUNC_GEMTSU0, - PINCTRL_FUNC_GPIO0, - PINCTRL_FUNC_I2C0, - PINCTRL_FUNC_I2C1, - PINCTRL_FUNC_MDIO0, - PINCTRL_FUNC_MDIO1, - PINCTRL_FUNC_MDIO2, - PINCTRL_FUNC_MDIO3, - PINCTRL_FUNC_QSPI0, - PINCTRL_FUNC_QSPI_FBCLK, - PINCTRL_FUNC_QSPI_SS, - PINCTRL_FUNC_SPI0, - PINCTRL_FUNC_SPI1, - PINCTRL_FUNC_SPI0_SS, - PINCTRL_FUNC_SPI1_SS, - PINCTRL_FUNC_SDIO0, - PINCTRL_FUNC_SDIO0_PC, - PINCTRL_FUNC_SDIO0_CD, - PINCTRL_FUNC_SDIO0_WP, - PINCTRL_FUNC_SDIO1, - PINCTRL_FUNC_SDIO1_PC, - PINCTRL_FUNC_SDIO1_CD, - PINCTRL_FUNC_SDIO1_WP, - PINCTRL_FUNC_NAND0, - PINCTRL_FUNC_NAND0_CE, - PINCTRL_FUNC_NAND0_RB, - PINCTRL_FUNC_NAND0_DQS, - PINCTRL_FUNC_TTC0_CLK, - PINCTRL_FUNC_TTC0_WAV, - PINCTRL_FUNC_TTC1_CLK, - PINCTRL_FUNC_TTC1_WAV, - PINCTRL_FUNC_TTC2_CLK, - PINCTRL_FUNC_TTC2_WAV, - PINCTRL_FUNC_TTC3_CLK, - PINCTRL_FUNC_TTC3_WAV, - PINCTRL_FUNC_UART0, - PINCTRL_FUNC_UART1, - PINCTRL_FUNC_USB0, - PINCTRL_FUNC_USB1, - PINCTRL_FUNC_SWDT0_CLK, - PINCTRL_FUNC_SWDT0_RST, - PINCTRL_FUNC_SWDT1_CLK, - PINCTRL_FUNC_SWDT1_RST, - PINCTRL_FUNC_PMU0, - PINCTRL_FUNC_PCIE0, - PINCTRL_FUNC_CSU0, - PINCTRL_FUNC_DPAUX0, - PINCTRL_FUNC_PJTAG0, - PINCTRL_FUNC_TRACE0, - PINCTRL_FUNC_TRACE0_CLK, - PINCTRL_FUNC_TESTSCAN0, - END_FUNCTION, + PINCTRL_FUNC_CAN0 = (0U), + PINCTRL_FUNC_CAN1 = (1U), + PINCTRL_FUNC_ETHERNET0 = (2U), + PINCTRL_FUNC_ETHERNET1 = (3U), + PINCTRL_FUNC_ETHERNET2 = (4U), + PINCTRL_FUNC_ETHERNET3 = (5U), + PINCTRL_FUNC_GEMTSU0 = (6U), + PINCTRL_FUNC_GPIO0 = (7U), + PINCTRL_FUNC_I2C0 = (8U), + PINCTRL_FUNC_I2C1 = (9U), + PINCTRL_FUNC_MDIO0 = (10U), + PINCTRL_FUNC_MDIO1 = (11U), + PINCTRL_FUNC_MDIO2 = (12U), + PINCTRL_FUNC_MDIO3 = (13U), + PINCTRL_FUNC_QSPI0 = (14U), + PINCTRL_FUNC_QSPI_FBCLK = (15U), + PINCTRL_FUNC_QSPI_SS = (16U), + PINCTRL_FUNC_SPI0 = (17U), + PINCTRL_FUNC_SPI1 = (18U), + PINCTRL_FUNC_SPI0_SS = (19U), + PINCTRL_FUNC_SPI1_SS = (20U), + PINCTRL_FUNC_SDIO0 = (21U), + PINCTRL_FUNC_SDIO0_PC = (22U), + PINCTRL_FUNC_SDIO0_CD = (23U), + PINCTRL_FUNC_SDIO0_WP = (24U), + PINCTRL_FUNC_SDIO1 = (25U), + PINCTRL_FUNC_SDIO1_PC = (26U), + PINCTRL_FUNC_SDIO1_CD = (27U), + PINCTRL_FUNC_SDIO1_WP = (28U), + PINCTRL_FUNC_NAND0 = (29U), + PINCTRL_FUNC_NAND0_CE = (30U), + PINCTRL_FUNC_NAND0_RB = (31U), + PINCTRL_FUNC_NAND0_DQS = (32U), + PINCTRL_FUNC_TTC0_CLK = (33U), + PINCTRL_FUNC_TTC0_WAV = (34U), + PINCTRL_FUNC_TTC1_CLK = (35U), + PINCTRL_FUNC_TTC1_WAV = (36U), + PINCTRL_FUNC_TTC2_CLK = (37U), + PINCTRL_FUNC_TTC2_WAV = (38U), + PINCTRL_FUNC_TTC3_CLK = (39U), + PINCTRL_FUNC_TTC3_WAV = (40U), + PINCTRL_FUNC_UART0 = (41U), + PINCTRL_FUNC_UART1 = (42U), + PINCTRL_FUNC_USB0 = (43U), + PINCTRL_FUNC_USB1 = (44U), + PINCTRL_FUNC_SWDT0_CLK = (45U), + PINCTRL_FUNC_SWDT0_RST = (46U), + PINCTRL_FUNC_SWDT1_CLK = (47U), + PINCTRL_FUNC_SWDT1_RST = (48U), + PINCTRL_FUNC_PMU0 = (49U), + PINCTRL_FUNC_PCIE0 = (50U), + PINCTRL_FUNC_CSU0 = (51U), + PINCTRL_FUNC_DPAUX0 = (52U), + PINCTRL_FUNC_PJTAG0 = (53U), + PINCTRL_FUNC_TRACE0 = (54U), + PINCTRL_FUNC_TRACE0_CLK = (55U), + PINCTRL_FUNC_TESTSCAN0 = (56U), + END_FUNCTION = (57U), }; -#define MAX_FUNCTION (unsigned int)(END_FUNCTION) +#define MAX_FUNCTION END_FUNCTION // pinctrl pin numbers enum { @@ -164,10 +164,10 @@ enum { PINCTRL_PIN_75, PINCTRL_PIN_76, PINCTRL_PIN_77, - END_PINS, + END_PINS = (78U), }; -#define MAX_PIN (unsigned int)(END_PINS) +#define MAX_PIN END_PINS // pinctrl group ids enum { diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h index d3e9a34a9..9ba9475d4 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h @@ -126,7 +126,7 @@ enum pm_ret_status pm_secure_rsaaes(uint32_t address_low, uint32_t address_high, uint32_t size, uint32_t flags); -unsigned int pm_get_shutdown_scope(void); +uint32_t pm_get_shutdown_scope(void); void pm_get_callbackdata(uint32_t *data, size_t count); enum pm_ret_status pm_ioctl(enum pm_node_id nid, uint32_t ioctl_id, |