summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Merge "docs(changelog): changelog for lts-v2.8.6 release" into lts-v2.8lts-v2.8.6lts-v2.8Bipin Ravi2023-04-212-1/+21
|\
| * docs(changelog): changelog for lts-v2.8.6 releaseVarun Wadekar2023-04-202-1/+21
|/ | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I7904bb919fc78ac9ff8b4b67d187f8b09afc1a68
* Merge "fix(tsp): use verbose for power logs" into lts-v2.8Varun Wadekar2023-04-201-8/+8
|\
| * fix(tsp): use verbose for power logsShruti Gupta2023-04-041-8/+8
| | | | | | | | | | | | | | | | TSP use verbose for cpu suspend resume logs Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: Ic1d3706feec6361946dd5c0d2bea90a2dd7a2d02 (cherry picked from commit 3354915fff2ad5f97551c22a44a90f4ff7b7cc9b)
* | Merge "fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4" into lts-v2.8Varun Wadekar2023-04-2011-65/+149
|\ \
| * | fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4Varun Wadekar2023-04-2011-65/+149
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The purpose of this patch is to address the T241 erratum T241-FABRIC-4, which causes unexpected behavior in the GIC when multiple transactions are received simultaneously from different sources. This hardware issue impacts NVIDIA server platforms that use more than two T241 chips interconnected. Each chip has support for 320 {E}SPIs. This issue occurs when multiple packets from different GICs are incorrectly interleaved at the target chip. The erratum text below specifies exactly what can cause multiple transfer packets susceptible to interleaving and GIC state corruption. GIC state corruption can lead to a range of problems, including kernel panics, and unexpected behavior. Erratum documentation: https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf The workaround is to ensure that MMIO accesses target the GIC on the socket that holds the data, for example SPI ranges owned by the socket’s GIC. This ensures that the GIC will not utilize the inter-socket AXI Stream interface for servicing these GIC MMIO accesses. This patch updates the functions that use the GICD_In{E} registers to ensure that the accesses are directed to the chip that owns the SPI, instead of using the global alias. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I04e33ba64eb306bd5fdabb56e63cbe273d8cd632 (cherry picked from commit a02a45dfef4b02fa363a5f843ba6a0aac52d181f)
* | Merge "docs(changelog): changelog for lts-v2.8.5 release" into lts-v2.8lts-v2.8.5Bipin Ravi2023-04-191-0/+12
|\ \
| * | docs(changelog): changelog for lts-v2.8.5 releaseVarun Wadekar2023-04-191-0/+12
|/ / | | | | | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ie1b4f81018ce5ed45b0f6efdb2c4c0d71e9b4afe
* | Merge "fix(cpus): workaround for Cortex-A78C erratum 1827440" into lts-v2.8Varun Wadekar2023-04-153-0/+41
|\ \
| * | fix(cpus): workaround for Cortex-A78C erratum 1827440Bipin Ravi2023-04-113-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A78C erratum 1827440 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[2], which forces atomic store operations to write-back memory to be performed in the L1 data cache. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7 (cherry picked from commit b01a59eb2a0456ca3ae6b8d020068ba846f813d4)
* | | Merge "fix(cpus): workaround for Cortex-A78C erratum 1827430" into lts-v2.8Varun Wadekar2023-04-154-0/+42
|\ \ \ | |/ /
| * | fix(cpus): workaround for Cortex-A78C erratum 1827430Bipin Ravi2023-04-114-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A78C erratum 1827430 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set the CPUECTLR_EL1[53] to 1, which disables allocation of splintered pages in the L2 TLB. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426 (cherry picked from commit 672eb21e26a41657b8146372d4283e794b430c5f)
* | | Merge "refactor(cpus): shorten errata flag defines" into lts-v2.8Varun Wadekar2023-04-152-893/+207
|\ \ \ | |/ /
| * | refactor(cpus): shorten errata flag definesBoyan Karatotev2023-04-112-893/+207
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu-ops makefile has errata flag definition and flag processing done per flag in separate parts in the file. Rework this to make a list and do this in a much more concise way. To ensure no flags were missed, a bash script [1] was used to verify all errata flags made it across. Only the first few flags with different naming were checked manually. [1]: sed -n "s/CPU_FLAG_LIST += ERRATA_\(.*\)/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/new git checkout origin/master sed -n "s/ERRATA_\([[:alnum:]_-]*\)\s*?=0/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/old diff /tmp/old /tmp/new Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3b88af46838cc26f42d2c66b31f96c0855fa406c (cherry picked from commit e444763d6517488a5a114dd3936c563186278278)
* | Merge "docs(changelog): changelog for lts-v2.8.4 release" into lts-v2.8lts-v2.8.4Varun Wadekar2023-04-102-1/+11
|\ \
| * | docs(changelog): changelog for lts-v2.8.4 releaseVarun Wadekar2023-04-042-1/+11
|/ / | | | | | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I7f63ca46c503a898ae39bbf3c1e0a078b0089f9d
* | Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into lts-v2.8Varun Wadekar2023-04-044-0/+52
|\ \ | |/ |/|
| * fix(cpus): workaround for Neoverse V1 errata 2743233Sona Mathew2023-03-284-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse V1 erratum 2743233 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround sets CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest Change-Id: If51a6f4293fa8b5b35c44edd564ebb715ba309a1 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> (cherry picked from commit f1c3eae9e091a63b42eebae8b03d4d470c9c3f75)
* | Merge "docs(changelog): changelog for lts-v2.8.3 release" into lts-v2.8lts-v2.8.3Varun Wadekar2023-03-292-1/+18
|\ \ | |/ |/|
| * docs(changelog): changelog for lts-v2.8.3 releaseVarun Wadekar2023-03-282-1/+18
|/ | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I49321c297446cce48b3c76ad99fcd8c45b51947d
* Merge "fix(cpus): workaround for Cortex-A78C erratum 2779484" into lts-v2.8Varun Wadekar2023-03-284-1/+54
|\
| * fix(cpus): workaround for Cortex-A78C erratum 2779484Bipin Ravi2023-03-104-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A78C erratum 2779484 is a Cat B erratum that applies to revisions r0p1 and r0p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed (cherry picked from commit 66bf3ba482e46137e19f368f1386436a33eaba74)
* | Merge "fix(cpus): workaround for Cortex-A78 erratum 2742426" into lts-v2.8Varun Wadekar2023-03-284-2/+53
|\ \ | |/
| * fix(cpus): workaround for Cortex-A78 erratum 2742426Bipin Ravi2023-03-104-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A78 erratum 2742426 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1 (cherry picked from commit a63332c517ac5699644d3e2fbf159d3e35c32549)
* | Merge "fix(deps): add missing aeabi_memset.S" into lts-v2.8Varun Wadekar2023-03-282-0/+50
|\ \
| * | fix(deps): add missing aeabi_memset.SBoyan Karatotev2023-03-242-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file provides __aeabi_memclr8 builtin which the Ubuntu 22.04 version of clang 14 needs to compile. Add it to prevent this oddity from failing the build. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id67aa0abba4a27c51b3ed6bb1be84b4e803b44bf (cherry picked from commit bdedee5a0f156d05eb62c704e702bfd1c506dc5d)
* | | Merge "docs(changelog): changelog for lts-v2.8.2 release" into lts-v2.8lts-v2.8.2Varun Wadekar2023-03-272-1/+13
|\ \ \ | |/ / |/| |
| * | docs(changelog): changelog for lts-v2.8.2 releaseVarun Wadekar2023-03-202-1/+13
|/ / | | | | | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I6e31d87362336cb2825dd4a66dac408f141fa3a7
* | Merge "fix(zynqmp): enable A53 workaround(errata 1530924)" into lts-v2.8Varun Wadekar2023-03-201-0/+1
|\ \ | |/ |/|
| * fix(zynqmp): enable A53 workaround(errata 1530924)Michal Simek2023-02-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BL31 already reports that there is missing CPU workaround for this erratum as "WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!" That's why enable it by default as was done by other platforms for example by commit 74665119f04d ("allwinner: Enable workaround for Cortex-A53 erratum 1530924"). Change-Id: I251ffe3c307781b07477afb64f4e7af5dd9af9fe Signed-off-by: Michal Simek <michal.simek@amd.com> (cherry picked from commit d8133d7785969b417cbace293db6393c55844fac)
* | Merge "docs(changelog): changelog for lts-v2.8.1 release" into lts-v2.8lts-v2.8.1Varun Wadekar2023-03-102-1/+11
|\ \
| * | docs(changelog): changelog for lts-v2.8.1 releaseOkash Khawaja2023-03-092-1/+11
|/ / | | | | | | | | Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I648f63de1fbdb2d38be59b06b9a0d8c22ee52dff
* | Merge "Revert "fix(el3_runtime): allow SErrors when executing in EL3"" into ↵Varun Wadekar2023-03-091-10/+0
|\ \ | |/ |/| | | lts-v2.8
| * Revert "fix(el3_runtime): allow SErrors when executing in EL3"Okash Khawaja2023-02-281-10/+0
|/ | | | | | | | | This reverts commit 327f4bb0cf2035ee46f0753429a43fd4c97a5d98. Reason for revert: deemed too disruptive for LTS at this stage Change-Id: I384a92511178b26fb2756fa4d273887b3912bb89 Signed-off-by: Okash Khawaja <okash@google.com>
* Merge "docs(changelog): changelog for lts-v2.8.0 release" into lts-v2.8lts-v2.8.0Varun Wadekar2023-02-132-3/+89
|\
| * docs(changelog): changelog for lts-v2.8.0 releaseVarun Wadekar2023-02-132-3/+89
|/ | | | | Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id86d52d8728f380986061bc04768c0b337851d3c
* Merge "docs(security): security advisory for CVE-2022-47630" into lts-v2.8lts-v2.8-rc0lts-testBipin Ravi2023-02-062-0/+160
|\
| * docs(security): security advisory for CVE-2022-47630Sandrine Bailleux2023-02-032-0/+160
| | | | | | | | | | | | | | | | Reported-by: Demi Marie Obenour <demiobenour@gmail.com> Co-authored-by: Demi Marie Obenour <demiobenour@gmail.com> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I20be2d280437eb223c988e2bf59c4562515817a0 (cherry picked from commit d7156d4123e55c598953251f77a83d9207eebe34)
* | Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into lts-v2.8Bipin Ravi2023-02-067-5/+92
|\ \ | |/
| * fix(cpus): workaround for Cortex-A510 erratum 2684597Harrison Mutai2023-02-037-5/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The workaround is to execute a TSB CSYNC and DSB before executing WFI for power down. SDEN can be found here: https://developer.arm.com/documentation/SDEN1873361/latest https://developer.arm.com/documentation/SDEN1873351/latest Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> (cherry picked from commit aea4ccf8d9f3eabbc931f0e82df65ffca28c25e5)
* | Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into lts-v2.8Bipin Ravi2023-02-063-3/+47
|\ \ | |/
| * fix(cpus): workaround for Cortex-A78C erratum 2772121Bipin Ravi2023-02-033-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A78C erratum 2772121 is a Cat B erratum that applies to all revisions <=r0p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9 (cherry picked from commit 00230e37e3c21fed4a46eeb69dea9d808f8402b4)
* | Merge "fix(plat/css): fix invalid redistributor poweroff" into lts-v2.8Bipin Ravi2023-02-061-3/+0
|\ \ | |/
| * fix(plat/css): fix invalid redistributor poweroffWaleed Elmelegy2023-02-031-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf introduced an invalid redistributor power off where we turn off the redistributor without checking if the system power domain level is turning off, otherwise we can turn off a redistributor when other cores or clusters are sharing it, also if it does indeed needs powering off during suspend we do it twice. This change fixes this by checking on the system power state first then turning off the redistributor. Signed-off-by: Waleed Elmelegy <waleed.elmelegy@arm.com> Change-Id: Id202bc2316ab7c516298fa33ea089ae2e221a933 (cherry picked from commit 60719e4e0965aead49d927f12bf2a37bd2629012)
* | Merge "fix(libc): properly define SCHAR_MIN" into lts-v2.8Bipin Ravi2023-02-062-4/+4
|\ \ | |/
| * fix(libc): properly define SCHAR_MINYann Gautier2023-02-032-4/+4
| | | | | | | | | | | | | | | | SCHAR_MIN definition should use SCHAR_MAX, and not itself. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: If8c1751a381dac50fe3ec5fdf19d6a4918470b58 (cherry picked from commit 06c01b085fb28fcfe26d747da2ba33415dbd52b9)
* | Merge "fix(el3_runtime): allow SErrors when executing in EL3" into lts-v2.8Bipin Ravi2023-02-061-0/+10
|\ \ | |/
| * fix(el3_runtime): allow SErrors when executing in EL3Manish Pandey2023-02-031-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCR_EL3.EA is set to 1 in BL31 initialization and is cleared before entering to lower ELs(except for RAS FFH case "HANDLE_EA_EL3_FIRST_NS"). The cleared value persist even during run time when execution comes back to EL3. When SCR_EL3.EA is 0 and execution state is EL3, Async EAs(delivered as SErrors) are implicitly masked and hence any Async EA by EL3 will remain pending and will trap at the exception level EA is targeted to and unmasked when entering lower EL. This causes unexpected EA at lower EL. This is a very rare to get SError in EL3 until unless there is any programming error. This patch sets SCR_EL3.EA to 1 when entering EL3 from lower EL. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibb593369edb034f670fd85ee79adc9829b900a83 (cherry picked from commit 1cbe42a510812a4a4415a26ba46821cad1c04b68)
* | Merge "fix(st): include utils.h to solve compilation error" into lts-v2.8Bipin Ravi2023-02-061-0/+1
|\ \ | |/
| * fix(st): include utils.h to solve compilation errorYann Gautier2023-02-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If compiling with STM32MP13 with DECRYPTION_SUPPORT != none, there is a compilation error: plat/st/common/stm32mp_crypto_lib.c: In function 'plat_get_enc_key_info': plat/st/common/stm32mp_crypto_lib.c:532:25: error: implicit declaration of function 'zeromem' [-Werror=implicit-function-declaration] 532 | zeromem(key, *key_len); | ^~~~~~~ Adding #include <lib/utils.h> solves the error. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I0a20c5632f0379612149333e69875369d4cfca15 (cherry picked from commit 377846b65e8eb946a6560f1200ca4ca0e1eb8b99)
View Lorry Controller Status