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* Revert "Code change to fix small bugs"revert-1389-db/bugfixDimitris Papastamos2018-06-082-1/+7
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* Merge pull request #1405 from dp-arm/dp/cve_2017_5715Dimitris Papastamos2018-06-081-11/+12
|\ | | | | Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32
| * Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32Dimitris Papastamos2018-06-071-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When SMCCC_ARCH_WORKAROUND_1 is invoked from a lower EL running in AArch32 state, ensure that the SMC call will take a shortcut in EL3. This minimizes the time it takes to apply the mitigation in EL3. When lower ELs run in AArch32, it is preferred that they execute the `BPIALL` instruction to invalidate the BTB. However, on some cores the `BPIALL` instruction may be a no-op and thus would benefit from making the SMCCC_ARCH_WORKAROUND_1 call go through the fast path. Change-Id: Ia38abd92efe2c4b4a8efa7b70f260e43c5bda8a5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Merge pull request #1389 from danielboulby-arm/db/bugfixDimitris Papastamos2018-06-082-7/+1
|\ \ | | | | | | Code change to fix small bugs
| * | Remove rt_svc_descs pointer from inner scopeDaniel Boulby2018-05-251-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A pointer to rt_svc_desc_t was defined both in the function and globally. The innermost definition hid the global definition which is the one we want to use so remove the innermost definition to prevent this Change-Id: Idabdbc0947178ae83224bd17a9b170df7c278d51 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
| * | Remove duplicate weak definitionDaniel Boulby2018-05-251-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The weak pragma was assigned twice to the bl2_plat_handle_post_image_load definition both in plat/common/ and in plat/arm/common/ this was an error as it should have only have been defined in plat/common Change-Id: Id85e14c699cb09ed998d1677f2a172e760911918 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | | Merge pull request #1407 from soby-mathew/sm/juno_bl1_sizeDimitris Papastamos2018-06-081-2/+2
|\ \ \ | | | | | | | | Juno: Bump up the BL1-RW size
| * | | Juno: Bump up the BL1-RW sizeSoby Mathew2018-06-071-2/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch bumps up the BL1-RW size for Juno and at the same time reduces the BL2 size when TBB is enabled, TF_MBEDTLS_KEY_ALG=rsa+ecdsa. The BL2 size for this config is reduced as it was observed that the peak memory usage is only reached when SPD=opteed and the dual rsa+ecdsa support is not needed for this case. Change-Id: Ia9009771b5cfd805e9cc75410aabb7db99fc2fbc Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | | Merge pull request #1404 from soby-mathew/sm/bl_layout_changeDimitris Papastamos2018-06-0713-153/+146
|\ \ \ | |_|/ |/| | ARM platforms: Change memory layout and update documentation
| * | docs: Firmware design update for BL memory layoutSoby Mathew2018-06-071-50/+65
| | | | | | | | | | | | | | | | | | | | | | | | This patch updates the firmware design guide for the BL memory layout change on ARM platforms. Change-Id: Icbfe7249484bb8b4ba3c94421172d42f27605c52 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * | ARM platforms: Move BL31 below BL2 to enable BL2 overlaySoby Mathew2018-06-0712-103/+81
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch changes the layout of BL images in memory to enable more efficient use of available space. Previously BL31 was loaded with the expectation that BL2 memory would be reclaimed by BL32 loaded in SRAM. But with increasing memory requirements in the firmware, we can no longer fit BL32 in SRAM anymore which means the BL2 memory is not reclaimed by any runtime image. Positioning BL2 below BL1-RW and above BL31 means that the BL31 NOBITS can be overlaid on BL2 and BL1-RW. This patch also propogates the same memory layout to BL32 for AArch32 mode. The reset addresses for the following configurations are also changed : * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode * When BL2_AT_EL3=1 for BL2 The restriction on BL31 to be only in DRAM when SPM is enabled is now removed with this change. The update to the firmware design guide for the BL memory layout is done in the following patch. Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1392 from dp-arm/dp/cve_2018_3639Dimitris Papastamos2018-05-2929-165/+424
|\ \ | |/ |/| Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75
| * Add support for dynamic mitigation for CVE-2018-3639Dimitris Papastamos2018-05-2312-10/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUS may benefit from using a dynamic mitigation approach for CVE-2018-3639. A new SMC interface is defined to allow software executing in lower ELs to enable or disable the mitigation for their execution context. It should be noted that regardless of the state of the mitigation for lower ELs, code executing in EL3 is always mitigated against CVE-2018-3639. NOTE: This change is a compatibility break for any platform using the declare_cpu_ops_workaround_cve_2017_5715 macro. Migrate to the declare_cpu_ops_wa macro instead. Change-Id: I3509a9337ad217bbd96de9f380c4ff8bf7917013 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * aarch32: Implement static workaround for CVE-2018-3639Dimitris Papastamos2018-05-234-0/+39
| | | | | | | | | | | | | | | | Implement static mitigation for CVE-2018-3639 on Cortex A57 and A72. Change-Id: I83409a16238729b84142b19e258c23737cc1ddc3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * Implement static workaround for CVE-2018-3639Dimitris Papastamos2018-05-2312-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For affected CPUs, this approach enables the mitigation during EL3 initialization, following every PE reset. No mechanism is provided to disable the mitigation at runtime. This approach permanently mitigates the entire software stack and no additional mitigation code is required in other software components. TF-A implements this approach for the following affected CPUs: * Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of `CPUACTLR_EL1` (`S3_1_C15_C2_0`). * Cortex-A73, by setting bit 3 of `S3_0_C15_C0_0` (not documented in the Technical Reference Manual (TRM)). * Cortex-A75, by setting bit 35 (reserved in TRM) of `CPUACTLR_EL1` (`S3_0_C15_C1_0`). Additionally, a new SMC interface is implemented to allow software executing in lower ELs to discover whether the system is mitigated against CVE-2018-3639. Refer to "Firmware interfaces for mitigating cache speculation vulnerabilities System Software on Arm Systems"[0] for more information. [0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification Change-Id: I084aa7c3bc7c26bf2df2248301270f77bed22ceb Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * Rename symbols and files relating to CVE-2017-5715Dimitris Papastamos2018-05-2314-155/+155
| | | | | | | | | | | | | | | | This patch renames symbols and files relating to CVE-2017-5715 to make it easier to introduce new symbols and files for new CVE mitigations. Change-Id: I24c23822862ca73648c772885f1690bed043dbc7 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | Merge pull request #1395 from antonio-nino-diaz-arm/an/spm-refactorDimitris Papastamos2018-05-2513-390/+384
|\ \ | |/ |/| SPM: Refactor codebase
| * plat/arm: SPM: Force BL31 to DRAM when SPM is usedAntonio Nino Diaz2018-05-244-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL31 is running out of space, and the use-case of SPM doesn't require it to be in SRAM. To prevent BL31 from running out of space in the future, move BL31 to DRAM if SPM is enabled. Secure Partition Manager design document updated to reflect the changes. Increased the size of the stack of BL31 for builds with SPM. The translation tables used by SPM in Arm platforms have been moved back to the 'xlat_tables' region instead of 'arm_el3_tzc_dram'. Everything is in DRAM now, so it doesn't make sense to treat them in a different way. Change-Id: Ia6136c8e108b8da9edd90e9d72763dada5e5e5dc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Extract code out of the SMC handlerAntonio Nino Diaz2018-05-231-76/+84
| | | | | | | | | | | | | | | | Simplify the code of the SMC handler by extracting the code of SP_EVENT_COMPLETE and MM_COMMUNICATE. Change-Id: I9250a3f5e4b807b35c9d044592c1074a45ab9a07 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Replace SP init flag by generic state enumAntonio Nino Diaz2018-05-232-11/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of just knowing if the Secure Partition is being initialized or not, this generic state enum can be used to tell if the Secure Partition is busy and to add more states in the future if needed. Also, the spinlock of the secure_partition_context_t structure now only protects against concurrent accesses to the state of the secure partition. Previously, it used to lock down the whole structure, thus preventing one CPU to access any of its fields while another CPU was executing the partition. Change-Id: I51215328e2ca8ea2452f92e4a1cb237415958b22 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Shorten names of types and functionsAntonio Nino Diaz2018-05-234-14/+14
| | | | | | | | | | | | | | | | | | The current internal names are too long, which makes it hard to write code as many lines overflow the limit and need to be split, which may not help the reader. Change-Id: I072bdc8f3dd125255063ffa7f02500e5228fc9a1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Move xlat-related functions to separate fileAntonio Nino Diaz2018-05-234-141/+166
| | | | | | | | | | | | | | This is done in order to make it easier to read the file spm_main.c. Change-Id: I21e765154c1682a319a3bc47a19a42fd736e910e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Move all SP-related info to SP context structAntonio Nino Diaz2018-05-235-235/+127
| | | | | | | | | | | | | | | | | | | | | | Move all information related to a Secure Partition to the struct secure_partition_context_t. This requires an in-depth refactor because most of the previous code of SPM relied on global information. Change-Id: I0a23e93817dcc191ce1d7506b8bc671d376123c4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * context_mgmt: Make cm_init_context_common publicAntonio Nino Diaz2018-05-233-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | This function can be currently accessed through the wrappers cm_init_context_by_index() and cm_init_my_context(). However, they only work on contexts that are associated to a CPU. By making this function public, it is possible to set up a context that isn't associated to any CPU. For consistency, it has been renamed to cm_setup_context(). Change-Id: Ib2146105abc8137bab08745a8adb30ca2c4cedf4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1386 from soby-mathew/sm/dyn_bl31Dimitris Papastamos2018-05-2327-74/+562
|\ \ | |/ |/| Extend dynamic configuration
| * FVP: Add dummy configs for BL31, BL32 and BL33Soby Mathew2018-05-2112-45/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP. The config files are placeholders and do not have any useful bindings defined. The tos_fw_config is packaged in FIP and loaded by BL2 only if SPD=tspd. The load address of these configs are specified in tb_fw_config via new bindings defined for these configs. Currently, in FVP, the soc_fw_config and tos_fw_config is loaded in the page between BL2_BASE and ARM_SHARED_RAM. This memory was typically used for BL32 when ARM_TSP_RAM_LOCATION=tsram but since we cannot fit BL32 in that space anymore, it should be safe to use this memory for these configs. There is also a runtime check in arm_bl2_dyn_cfg_init() which ensures that this overlap doesn't happen. The previous arm_dyn_get_hwconfig_info() is modified to accept configs other than hw_config and hence renamed to arm_dyn_get_config_load_info(). The patch also corrects the definition of ARM_TB_FW_CONFIG_LIMIT to be BL2_BASE. Change-Id: I03a137d9fa1f92c862c254be808b8330cfd17a5a Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Dynamic cfg: Enable support on CoT for other configsSoby Mathew2018-05-188-9/+145
| | | | | | | | | | | | | | | | | | | | This patch implements support for adding dynamic configurations for BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The necessary cert tool support and changes to default chain of trust are made for these configs. Change-Id: I25f266277b5b5501a196d2f2f79639d838794518 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * FVP: Enable capability to disable auth via dynamic configSoby Mathew2018-05-187-4/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds capability to FVP to disable authentication dynamically via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses the TB_FW_CONFIG for the `disable_auth` property and invokes the `load_dyn_disable_auth()` API to disable authentication if the property is set to 1. The DYN_DISABLE_AUTH is enabled by default for FVP as it is a development platform. Note that the TB_FW_CONFIG has to be authenticated by BL1 irrespective of these settings. The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup() rather than in bl2_platform_setup() as we need to get the value of `disable_auth` property prior to authentication of any image by BL2. Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Allow disabling authentication dynamicallySoby Mathew2018-05-185-20/+86
| | | | | | | | | | | | | | | | | | | | This patch allows platforms to dynamically disable authentication of images during cold boot. This capability is controlled via the DYN_DISABLE_AUTH build flag and is only meant for development purposes. Change-Id: Ia3df8f898824319bb76d5cc855b5ad6c3d227260 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1393 from geesun/correct_commentDimitris Papastamos2018-05-221-2/+2
|\ \ | | | | | | Correct some typo errors in comment
| * | Correct some typo errors in commentQixiang Xu2018-05-221-2/+2
| |/ | | | | | | | | | | | | File: include/common/aarch64/el3_common_macros.S Change-Id: I619401e961a3f627ad8864781b5f90bc747c3ddb Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | Merge pull request #1390 from soby-mathew/sm/fvp_rm_dtbDimitris Papastamos2018-05-229-19/+29
|\ \ | | | | | | Remove the DTBs and update userguide for FVP
| * | Docs: Update user guide for Dynamic Config on FVPSoby Mathew2018-05-211-19/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From TF-A v1.5, FVP supports loading the kernel FDT through firmware as part of dynamic configuration feature. This means that the FDT no longer needs to be loaded via Model parameters. This patch updates the user guide to reflect the same. Change-Id: I79833beeaae44a1564f6512c3a473625e5959f65 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * | Dynamic_config: remove the FVP dtb filesSoby Mathew2018-05-218-0/+0
| |/ | | | | | | | | | | | | | | | | Since FVP enables dynamic configuration by default, the DT blobs are compiled from source and included in FIP during build. Hence this patch removes the dtb files from the `fdts` folder. Change-Id: Ic155ecd257384a33eb2aa38c9b4430e47b09cd31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1359 from danielboulby-arm/db/match_flags_typeDimitris Papastamos2018-05-212-4/+8
|\ \ | |/ |/| Ensure read and write of flags defined in the console struct are 32 bit
| * Ensure read and write of flags are 32 bitDaniel Boulby2018-05-172-4/+8
| | | | | | | | | | | | | | | | | | | | In 'console_set_scope' and when registering a console, field 'flags' of 'console_t' is assigned a 32-bit value. However, when it is actually used, the functions perform 64-bit reads to access its value. This patch changes all 64-bit reads to 32-bit reads. Change-Id: I181349371409e60065335f078857946fa3c32dc1 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1369 from sivadur/xilinxdiffdanh-arm2018-05-1717-271/+692
|\ \ | | | | | | Xilinx platform mangement related changes
| * | zynqmp: Add wdt timeout restart functionalitySiva Durga Prasad Paladugu2018-05-176-0/+243
| | | | | | | | | | | | | | | | | | | | | This patch adds support to restart system incase of wdt timeout. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | zynqmp: Fix EG/EV detection logicSiva Durga Prasad Paladugu2018-05-172-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, display EG/EV as a part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field.This patch also used IPI to get this info from pmufw instead of directly accessing the registers. Accessing this info from pmufw using IPI fixes the issue of PMUFW access denied error for reading IPDISABLE register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * | zynqmp: Add new API for processing secure imagesSiva Durga Prasad Paladugu2018-05-174-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds new API for processing secure images. This API is used for authentication and decryption of secure images using xilsecure in pmufw. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | xilinx: zynqmp: pm_service: Fix APU only restartTejas Patel2018-05-173-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing code blocks each IPI send request in ipi_mb_notify() function till pmu clears respective bit in ipi observation register. After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will restart APU. While PMU is restarting APU, ATF is running out of OCM, which can cause read/write hang from/to OCM. There is no need to wait for notification from PMU in case of SystemShutdown request in ATF, as APU is going to restart. This patch fixes APU only restart issue. Signed-off-by: Tejas Patel <tejasp@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com>
| * | plat: xilinx: zynqmp: Make fpga load blocking until completedSiva Durga Prasad Paladugu2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes bitstream load blocking call and waits until bitstream is loaded successfully or return with error. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Avesh Khan <aveshk@xilinx.com>
| * | plat: xilinx: zynqmp: Remove GET_CALLBACK_DATA functionSiva Durga Prasad Paladugu2018-05-173-24/+0
| | | | | | | | | | | | | | | | | | | | | GET_CALLBACK_DATA function is not required now. IPI mailbox can be used instead of GET_CALLBACK_DATA function. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | zynqmp: pm_service: Make PMU IPI-1 channel unsecureRajan Vaja2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU IPI-1 is used for callbacks from PMU to master. Unsecure master can also receive callbacks from PMU, so make PMU IPI-1 as non-secure. All requests from master(s) to PMU would still go on PMU IPI-1 secure channel. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
| * | zynqmp: pm: Remove unnecessary header includesRajan Vaja2018-05-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove includes of gic_common.h and string.h which are not required. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com>
| * | xilinx: zynqmp: Remove PMU Firmware checksSiva Durga Prasad Paladugu2018-05-174-198/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx now requires the PMU FW when using ATF, so it doesn't make sense to maintain checks for the PMU FW in ATF. This also means that cases where ATF came up before the PMU FW (such as on QEMU) ATF will now hang waiting for the PMU FW instead of aborting. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: pm: Reverse logic for detecting that the PMU firmware is loadedSiva Durga Prasad Paladugu2018-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use positive logic (pm_up instead of pm_down) to check whether PMU services are available. This change also puts the variable into the BSS section rather than the Data section as the variable is now initialized to 0 rather than 1. Signed-off-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | plat: zynqmp: Don't panic() if we can't find the FSBL structAlistair Francis2018-05-172-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we can't find the FSBL handoff struct don't panic and just use the defaults instead. We still print a warning to the user to let them know what we couldn't find it. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * | plat: zynqmp: Let fsbl_atf_handover() return an error statusSiva Durga Prasad Paladugu2018-05-173-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | Instead of calling panic() in fsbl_atf_handover() return the error status so that bl31_early_platform_setup() can act accordingly. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | Include "bl_common.h" in Xilinx zynqmp_private.hWendy Liang2018-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Type "entry_point_info_t" is used in zynqmp_private.h. It is defined in "bl_common.h". The header file which defines the type should be included. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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