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* Remove copyright header from JSON file.topics/ffa_rel_protoMarc Bonnici2020-10-011-6/+0
| | | | | | | The copyright notice was added by mistake to a json file, remove the notice again. Change-Id: Ic822b224713191ea55b5c11e49cedc2504abe1b4
* Add Prototype DisclaimerMarc Bonnici2020-09-251-0/+7
| | | | Change-Id: I7fb08218eb04056e694c2b43073d606bc57f73b7
* Add build script and README for prototypeMarc Bonnici2020-09-252-0/+783
| | | | | | | | | | | | Adds a PROTOTYPE_README detailing the required environment and a `multi_build.sh` script to build/run the prototype. The script is able to run the prototype both with and without EL-2 enabled in the normal and secure world independently. For more usage information please consult the README or invoke the script with `--help`. Change-Id: Id489ad943399ff1da8976553f9d1318b3be6e4b5
* fdts: Add DTS files used in the prototypeMarc Bonnici2020-09-254-0/+1021
| | | | | | | | | | | | The following DTS files are added to enable the use of the prototype: - inner_initrd.dts: DTS for N-HF ramdisk - normal_world_multi: 8 core DTS for ATF and booting HF - normal_world_single: Single core DTS for ATF and booting HF - secure_world_dt.dts: DTS for S-HF Change-Id: I75e1e17eb933083ab695637cab343992fa3af929
* Update SPCI_VERSION to be EAC compliantMarc Bonnici2020-09-253-5/+5
| | | | | | | Bumped the version from 0.9 to 1.0 and update the register used by FF-A_VERSION. Change-Id: Ia630d36c284c804542585fcf44e5e753b49a65af
* SPMD: Increase maximum file size for DTBMarc Bonnici2020-09-251-1/+1
| | | | | | | | | Allow a larger DTB size to accommodate additional information to be supplied. The actual increase in the size of the DTB is smaller than allowed here however this value increase was determined by trail and error until a bootloop in TF-A was resolved. Change-Id: I19c707966681b7a392e5387fbfe6dad090d51be8
* Enable running OP-TEE as an S-EL1 partitionMarc Bonnici2020-09-255-20/+88
| | | | | | | | | - Add manifest and sp_layout files. - Increase ARM_SP_MAX_SIZE to 0x100000 to prevent boot loop. - Add additional allowed memory region for OP-TEE. - Update the start/end addressed of ramdisk. Change-Id: I0f888e03e9f4cafba8988004ba4d6489ba4af0fb
* SPMD: [EXP] Hook up support for PSCI usage from the secure worldAchin Gupta2020-06-014-4/+34
| | | | | | | | | | | | This is a temporary solution, all secure world PSCI calls are meant to be handled within S-EL2 which means the PSCI SPD callbacks need to be routed to S-EL2 appropriately. This patch delegates invocation of PSCI calls from the secure world to the SMC handler registered by the SPMD. Change-Id: I12f658f388175fdb7db42fcda8d884ac6401a887 Signed-off-by: Achin Gupta <achin.gupta@arm.com>
* SPMD: [EXP] Add PSCI_CPU_ON support to SPMDAchin Gupta2020-06-011-0/+131
| | | | | | | | | | | | | | | | | | | This is a temporary solution, all secure world PSCI calls are meant to be handled within S-EL2 which means the PSCI SPD callbacks need to be routed to S-EL2 appropriately. This patch enables the SPMD and SPMC to use the PSCI_CPU_ON function to initialise SPMC contexts on secondary CPUs. It registers a handler for PSCI calls from the secure world. Only the PSCI_CPU_ON call is implemented. It is used to register the entry point for the SPMC on each secondary CPU. It also registers a handler for a PSCI CPU ON finish operation that was invoked by the normal world. This handler initialises the SPMC context on the secondary CPU in response to an invocation of this hook. Change-Id: I4412b9a97afb520aaf9931d1c82979c2831c34b9 Signed-off-by: Achin Gupta <achin.gupta@arm.com>
* SPMD: [EXP] Use PSCI states to manage SPMC bootAchin Gupta2020-06-012-7/+21
| | | | | | | | | | | | | | This is a temporary solution, all secure world PSCI calls are meant to be handled within S-EL2 which means the PSCI SPD callbacks need to be routed to S-EL2 appropriately. This patch replaces private states used by the SPMD to determine whether SPMC has booted on a CPU with PSCI affinity states. This enables the SPMC on the boot CPU to use the PSCI_CPU_ON function to begin initialisation on secondary CPUs. Change-Id: Ie29b31c18f1e9ede199dc2c9c506fafb13fed296 Signed-off-by: Achin Gupta <achin.gupta@arm.com>
* SPMD: [EXP] Export entry point info as a global variableAchin Gupta2020-06-012-0/+12
| | | | | | | | | | | | | This is a temporary solution, all secure world PSCI calls are meant to be handled within S-EL2 which means the PSCI SPD callbacks need to be routed to S-EL2 appropriately. This patch converts the local entry_point_info structure used on the boot cpu to a global as it will be used to initialise the SPMC context on secondary CPUs in future patches. Change-Id: Icb92a2403d746cf120f05708bab56d3ffb3f7e05 Signed-off-by: Achin Gupta <achin.gupta@arm.com>
* SPMD: [EXP] Groundwork for PSCI usage to initialise SPMCAchin Gupta2020-06-013-5/+14
| | | | | | | | | | | | | | | | | This is a temporary solution, all secure world PSCI calls are meant to be handled within S-EL2 which means the PSCI SPD callbacks need to be routed to S-EL2 appropriately. This patch is the first in a series to demonstrate experimental support for use of PSCI functions to initialise the SPMC on secondary CPUs. This patch enables a SPMD to register a handler for PSCI calls invoked by the SPMC. It also moves a couple of utility functions from a private PSCI header to a public header. These functions will be used by the secure PSCI call handler. Change-Id: I6c412d21e4c66937c55024c91ef93baaaa061438 Signed-off-by: Achin Gupta <achin.gupta@arm.com>
* Merge "Enable v8.6 WFE trap delays" into integrationMark Dykes2020-05-207-0/+81
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| * Enable v8.6 WFE trap delaysjohpow012020-05-197-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the v8.6 extension to add a delay before WFE traps are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in plat/common/aarch64/plat_common.c that disables this feature by default but platform-specific code can override it when needed. The only hook provided sets the TWED fields in SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in lower ELs but these should be configured by code running at EL2 and/or EL1 depending on the platform configuration and is outside the scope of TF-A. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
* | Merge "plat/fvp: Populate GICv3 parameters dynamically" into integrationMark Dykes2020-05-203-2/+125
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| * | plat/fvp: Populate GICv3 parameters dynamicallylaurenw-arm2020-05-193-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | Query the GICD and GICR base addresses in runtime using fconf getter APIs. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I309fb2874f3329ddeb8677ddb53ed4c02199a1e9
* | | Merge "Tegra: enable stack protection" into integrationSandrine Bailleux2020-05-203-0/+36
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| * | Tegra: enable stack protectionVarun Wadekar2020-05-163-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets ENABLE_STACK_PROTECTOR=strong and implements the platform support to generate a stack protection canary value. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a
* | | Merge "Fix exception in save/restore of EL2 registers." into integrationManish Pandey2020-05-192-129/+124
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| * | | Fix exception in save/restore of EL2 registers.Max Shvetsov2020-05-192-129/+124
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Removing FPEXC32_EL2 from the register save/restore routine for EL2 registers since it is already a part of save/restore routine for fpregs. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4
* | | Merge "Fix compilation error when ENABLE_PIE=1" into integrationSandrine Bailleux2020-05-191-1/+2
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| * Fix compilation error when ENABLE_PIE=1Varun Wadekar2020-05-161-1/+2
|/ | | | | | | | | | | | | | | | This patch fixes compilation errors when ENABLE_PIE=1. <snip> bl31/aarch64/bl31_entrypoint.S: Assembler messages: bl31/aarch64/bl31_entrypoint.S:61: Error: invalid operand (*UND* section) for `~' bl31/aarch64/bl31_entrypoint.S:61: Error: invalid immediate Makefile:1079: recipe for target 'build/tegra/t194/debug/bl31/bl31_entrypoint.o' failed <snip> Verified by setting 'ENABLE_PIE=1' for Tegra platform builds. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifd184f89b86b4360fda86a6ce83fd8495f930bbc
* Merge "plat/arm/fvp: Support performing SDEI platform setup in runtime" into ↵Mark Dykes2020-05-1514-52/+303
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| * plat/arm/fvp: Support performing SDEI platform setup in runtimeBalint Dobszay2020-05-1514-52/+303
|/ | | | | | | | | | | | This patch introduces dynamic configuration for SDEI setup and is supported when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays and processing the configuration at compile time, the config is moved to dts files. It will be retrieved at runtime during SDEI init, using the fconf layer. Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge "Tegra: introduce support for SMCCC_ARCH_SOC_ID" into integrationManish Pandey2020-05-152-0/+34
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| * Tegra: introduce support for SMCCC_ARCH_SOC_IDVarun Wadekar2020-05-122-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch returns the SOC version and revision values from the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers. Verified using TFTF SMCCC_ARCH_SOC_ID test. <snip> > Executing 'SMCCC_ARCH_SOC_ID test' TEST COMPLETE Passed SOC Rev = 0x102 SOC Ver = 0x36b0019 <snip> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44
* | Merge "Implement workaround for AT speculative behaviour" into integrationMark Dykes2020-05-145-10/+87
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| * | Implement workaround for AT speculative behaviourManish V Badarkhe2020-05-145-10/+87
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During context switching from higher EL (EL2 or higher) to lower EL can cause incorrect translation in TLB due to speculative execution of AT instruction using out-of-context translation regime. Workaround is implemented as below during EL's (EL1 or EL2) "context_restore" operation: 1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1 bits for EL1 or EL2 (stage1 and stage2 disabled) 2. Save all system registers except TCR and SCTLR (for EL1 and EL2) 3. Do memory barrier operation (isb) to ensure all system register writes are done. 4. Restore TCR and SCTLR registers (for EL1 and EL2) Errata details are available for various CPUs as below: Cortex-A76: 1165522 Cortex-A72: 1319367 Cortex-A57: 1319537 Cortex-A55: 1530923 Cortex-A53: 1530924 More details can be found in mail-chain: https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html Currently, Workaround is implemented as build option which is default disabled. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0
* | Merge changes I35c5abd9,I99e64245 into integrationManish Pandey2020-05-137-241/+254
|\ \ | | | | | | | | | | | | | | | * changes: SPMD: extract SPMC DTB header size from SPMD SPMD: code/comments cleanup
| * | SPMD: extract SPMC DTB header size from SPMDOlivier Deprez2020-05-134-72/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently BL2 passes TOS_FW_CONFIG address and size through registers to BL31. This corresponds to SPMC manifest load address and size. The SPMC manifest is mapped in BL31 by dynamic mapping. This patch removes BL2 changes from generic code (which were enclosed by SPD=spmd) and retrieves SPMC manifest size directly from within SPMD. The SPMC manifest load address is still passed through a register by generic code. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f
| * | SPMD: code/comments cleanupOlivier Deprez2020-05-136-181/+193
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | As a follow-up to bdd2596d4, and related to SPM Dispatcher EL3 component and SPM Core S-EL2/S-EL1 component: update with cosmetic and coding rules changes. In addition: -Add Armv8.4-SecEL2 arch detection helper. -Add an SPMC context (on current core) get helper. -Return more meaningful error return codes. -Remove complexity in few spmd_smc_handler switch-cases. -Remove unused defines and structures from spmd_private.h Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe
* | Merge "doc: Reorganize maintainers.rst file" into integrationjoanna.farley2020-05-131-51/+70
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| * | doc: Reorganize maintainers.rst fileSandrine Bailleux2020-05-131-51/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maintainers.rst file provides the list of all TF-A modules and their code owners. As there are quite a lot of modules (and more to come) in TF-A, it is sometimes hard to find the information. Introduce categories (core code, drivers/libraries/framework, ...) and classify each module in the right one. Note that the core code category is pretty much empty right now but the plan would be to expand it with further modules (e.g. PSCI, SDEI, TBBR, ...) in a future patch. Change-Id: Id68a2dd79a8f6b68af5364bbf1c59b20c05f8fe7 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | Merge "doc: Update various process documents" into integrationjoanna.farley2020-05-133-56/+72
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| * doc: Update various process documentsSandrine Bailleux2020-05-133-56/+72
|/ | | | | | | | | | Most of the changes consist in using the new code owners terminology (from [1]). [1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ Change-Id: Icead20e9335af12aa47d3f1ac5d04ca157b20c82 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Merge "Fix SMCCC_ARCH_SOC_ID implementation" into integrationMark Dykes2020-05-081-10/+18
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| * Fix SMCCC_ARCH_SOC_ID implementationManish V Badarkhe2020-05-051-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0e753437e75b ("Implement SMCCC_ARCH_SOC_ID SMC call") executes and return the result of SMCCC_ARCH_SOC_ID(soc_id_type) to the SMCCC_ARCH_FEATURES(SMCCC_ARCH_SOC_ID) itself. Moreover it expect to pass soc_id_type for SMCCC_ARCH_FEATURES(SMCCC_ARCH_SOC_ID) which is incorrect. Fix the implementation by returning SMC_OK for SMCCC_ARCH_FEATURES(SMCCC_ARCH_SOC_ID) always and move the current implementation under "smccc_arch_id" function which gets called from SMC handler on receiving "SMCCC_ARCH_SOC_ID" command. This change is tested over linux operating system Change-Id: I61a980045081eae786b907d408767ba9ecec3468 Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | Merge changes from topic "fdt_wrappers_rework" into integrationSandrine Bailleux2020-05-077-26/+75
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: arm_fpga: Read UART address from DT arm_fpga: Read GICD and GICR base addresses from DT arm_fpga: Read generic timer counter frequency from DT arm_fpga: Use Generic UART
| * | arm_fpga: Read UART address from DTAndre Przywara2020-05-052-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm_fpga port requires a DTB, to launch a BL33 payload. To make this port more flexible, we can also use the information in the DT to configure the console driver. For a start, find the DT node pointed to by the stdout-path property, and read the base address from there. This assumes for now that the stdout-path points to a PL011 UART. This allows to remove platform specific addresses from the image. We keep the original base address for the crash console. Change-Id: I46a990de2315f81cae4d7913ae99a07b0bec5cb1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | arm_fpga: Read GICD and GICR base addresses from DTAndre Przywara2020-05-052-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we use a DTB with all platform information to pass this on to a kernel loaded as BL33, we can as well make use of it for our own purposes. Every DT would contain a node for the GIC(v3) interrupt controller, so we can read the base address for the distributor and redistributors from there. This avoids hard coding this information in the code and allows for a more flexible binary. Change-Id: Ic530e223a21a45bc30a07a21048116d5af69e972 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | arm_fpga: Read generic timer counter frequency from DTAndre Przywara2020-05-053-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Generic Timer DT binding describes an (optional) property to declare the counter frequency. Its usage is normally discouraged, as the value should be read from the CNTFRQ_EL0 system register. However in our case we can use it to program this register in the first place, which avoids us to hard code a counter frequency into the code. We keep some default value in, if the DT lacks that property for whatever reason. Change-Id: I5b71176db413f904f21eb16f3302fbb799cb0305 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | arm_fpga: Use Generic UARTAndre Przywara2020-05-055-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SCP firmware on the ARM FPGA initialises the UART already. This allows us to treat the PL011 as an SBSA Generic UART, which does not require any further setup. This in particular removes the need for any baudrate and base clock related settings to be hard coded into the BL31 image. Change-Id: I16fc943526267356b97166a7068459e06ff77f0f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "fdt_wrappers_rework" into integrationSandrine Bailleux2020-05-077-92/+80
|\ \ \ | |/ / | | | | | | | | | | | | | | | * changes: plat/stm32: Use generic fdt_get_stdout_node_offset() fdt/wrappers: Introduce code to find UART DT node plat/stm32: Use generic fdt_get_reg_props_by_name()
| * | plat/stm32: Use generic fdt_get_stdout_node_offset()Andre Przywara2020-05-051-48/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have an implementation for getting the node offset of the stdout-path property in the generic fdt_wrappers code, use that to replace the current ST platform specific implementation. Change-Id: I5dd05684e7ca3cb563b5f71c885e1066393e057e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | fdt/wrappers: Introduce code to find UART DT nodeAndre Przywara2020-05-054-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stdout-path property in the /chosen node of a DTB points to a device node, which is used for boot console output. On most (if not all) ARM based platforms this is the debug UART. The ST platform code contains a function to parse this property and chase down eventual aliases to learn the node offset of this UART node. Introduce a slightly more generalised version of this ST platform function in the generic fdt_wrappers code. This will be useful for other platforms as well. Change-Id: Ie6da47ace7833861b5e35fe8cba49835db3659a5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | plat/stm32: Use generic fdt_get_reg_props_by_name()Andre Przywara2020-05-057-44/+25
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functionality is generic and actually widely useful outside of the STM32 code. Re-implement fdt_get_reg_props_by_name() on top of the newly introduced fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c. This is removes the assumption that #address-cells and #size-cells are always one. Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "rcar_gen3: plat: Zero-terminate the string in unsigned_num_print()" ↵Sandrine Bailleux2020-05-051-0/+1
|\ \ | | | | | | | | | into integration
| * | rcar_gen3: plat: Zero-terminate the string in unsigned_num_print()Marek Vasut2020-04-281-0/+1
| | | | | | | | | | | | | | | | | | | | | Make sure the string generated in unsigned_num_print() is zero-terminated. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic0ac1ebca255002522159a9152ab41991f043d05
* | | Merge changes I85eb75cf,Ic6d9f927 into integrationSandrine Bailleux2020-05-0514-15/+60
|\ \ \ | | | | | | | | | | | | | | | | | | | | * changes: fconf: Update dyn_config compatible string doc: Add binding document for fconf.
| * | | fconf: Update dyn_config compatible stringLouis Mayencourt2020-04-3011-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dynamic configuration properties are fconf properties. Modify the compatible string from "arm,.." to "fconf,.." to reflect this. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I85eb75cf877c5f4d3feea3936d4c348ca843bc6c
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